FreeCalypso > hg > fc-tourmaline
view src/g23m-gprs/gmm/gmm_rdyp.h @ 268:f2e52cab0a73
abb_inth.c: check all interrupt causes, not just one
The original code used if - else if - else if etc constructs, thus
the first detected interrupt was the only one handled. However,
Iota ITSTATREG is a clear-on-read register, thus if we only handle
the first detected interrupt and skip checking the others, then the
other interrupts will be lost, if more than one interrupt happened
to occur in one ABB interrupt handling cycle - a form of rare race
condition. Change the code to check all interrupts that were read
in this cycle.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 13 Jun 2021 18:17:53 +0000 |
parents | fa8dc04885d8 |
children |
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/* +----------------------------------------------------------------------------- | Project : GPRS (8441) | Modul : gmm_rdyp.h +----------------------------------------------------------------------------- | Copyright 2002 Texas Instruments Berlin, AG | All rights reserved. | | This file is confidential and a trade secret of Texas | Instruments Berlin, AG | The receipt of or possession of this file does not convey | any rights to reproduce or disclose its contents or to | manufacture, use, or sell anything it may describe, in | whole, or in part, without the specific written consent of | Texas Instruments Berlin, AG. +----------------------------------------------------------------------------- | Purpose : Definitions for gmm_rdyp.c +----------------------------------------------------------------------------- */ #ifndef GMM_RDYP_H #define GMM_RDYP_H EXTERN void rdy_t3316 (void); EXTERN void rdy_cgrlc_trigger_ind ( T_CGRLC_TRIGGER_IND *cgrlc_trigger_ind ); /* TCS 2.1 */ EXTERN void rdy_cgrlc_standby_state_ind ( T_CGRLC_STANDBY_STATE_IND *cgrlc_standby_state_ind ); /* TCS 2.1 */ EXTERN void rdy_cgrlc_ready_state_ind ( T_CGRLC_READY_STATE_IND *cgrlc_ready_state_ind ); /* TCS 2.1 */ #endif /* !GMM_RDYP_H */