FreeCalypso > hg > fc-tourmaline
view src/cs/system/main/gcc/irqfiq.S @ 303:f76436d19a7a default tip
!GPRS config: fix long-standing AT+COPS chance hanging bug
There has been a long-standing bug in FreeCalypso going back years:
sometimes in the AT command bring-up sequence of an ACI-only MS,
the AT+COPS command would produce only a power scan followed by
cessation of protocol stack activity (only L1 ADC traces), instead
of the expected network search sequence. This behaviour was seen
in different FC firmware versions going back to Citrine, and seemed
to follow some law of chance, not reliably repeatable.
This bug has been tracked down and found to be specific to !GPRS
configuration, stemming from our TCS2/TCS3 hybrid and reconstruction
of !GPRS support that was bitrotten in TCS3.2/LoCosto version.
ACI module psa_mms.c, needed only for !GPRS, was missing in the TCS3
version and had to be pulled from TCS2 - but as it turns out,
there is a new field in the MMR_REG_REQ primitive that needs to be
set correctly, and that psa_mms.c module is the place where this
initialization needed to be added.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Thu, 08 Jun 2023 08:23:37 +0000 |
| parents | 4e78acac3d88 |
| children |
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/* * This module contains the assembly shells for IRQ and FIQ, separated * from the architectured vectors only by some simple unconditional * branch instructions. * * Note that TI's way of handling interrupts sacrifices Nucleus' ability * to nest interrupts and minimize the IRQ-disabled window: if my (Falcon's) * understanding is correct, TI's code leaves all further IRQs disabled * for the full execution duration of an IRQ handler. (IRQ handlers are * really LISRs, but TI's GSM fw does not use Nucleus' LISR framework.) */ .text .code 32 .globl _INT_IRQ _INT_IRQ: STMDB sp!,{r0-r4} @ used to be a1-a4 /* * Thanks to TI for discovering and documenting this apparent ARM7TDMI bug: BUG correction 1st part ------------------- It looks like there is an issue with ARM7 IRQ masking in the CPSR register which leads to crashes in Nucleus+ scheduler. Basically the code below (correct as LOCKOUT = 0xC0) is used in many places by N+ but do not prevent from having an interrupt after the execution of the third line (I mean execution, not fetch). MRS a1,CPSR ; Pickup current CPSR ORR a1,a1,#LOCKOUT ; Build interrupt lockout value MSR CPSR,a1 ; Lockout interrupts * IRQ INTERRUPT ! * Next instructions... SW workaround: When a task is interrupted at this point an interrupted context is stored on its task and will be resumed later on at the next instruction but to make a long story short it leads to some problem as the OS does not expect to be interrupted there. Further testing tends to show that the CPSR *seems* to be loaded with the proper masking value but that the IRQ is still triggered (has been hardwarewise requested during the instruction exectution by the ARM7 core?) */ MRS a1,spsr @ check for the IRQ bug: TST a1,#0x80 @ if the I - flag is set, BNE IRQBUG @ then postpone execution of this IRQ /* Bug correction 1st part end --------------- */ SUB r4,lr,#4 @ Save IRQ's lr (return address) BL TCT_Interrupt_Context_Save @ Call context save routine BL IQ_IRQ_isr @ Call int. service routine /* IRQ interrupt processing is complete. Restore context- Never returns! */ B TCT_Interrupt_Context_Restore /* BUG correction 2nd part ------------------ */ IRQBUG: LDMFD sp!,{r0-r4} @ return from interrupt SUBS pc,r14,#4 /* BUG correction 2nd part end -------------- */ .globl _INT_FIQ _INT_FIQ: STMDB sp!,{r0-r4} @ used to be a1-a4 SUB r4,lr,#4 @ Save FIQ's lr (return address) BL TCT_Interrupt_Context_Save @ Call context save routine BL IQ_FIQ_isr @ Call the FIQ ISR /* FIQ interrupt processing is complete. Restore context- Never returns! */ B TCT_Interrupt_Context_Restore