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annotate src/cs/drivers/drv_app/ffs/board/intelsbdrv.c @ 19:399779c700da

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top make-all.sh script added
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 05:59:55 +0000
parents 92470e5d0b9e
children
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1 /******************************************************************************
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2 * Flash File System (ffs)
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3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com
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4 *
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5 * FFS AMD single bank low level flash driver RAM code
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6 *
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7 * $Id: intelsbdrv.c 1.13 Thu, 08 Jan 2004 15:05:23 +0100 tsj $
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8 *
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9 ******************************************************************************/
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10
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11 #include "ffs.cfg"
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12
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13 #include "ffs/ffs.h"
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14 #include "ffs/board/drv.h"
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15 #include "ffs/board/ffstrace.h"
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16
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17
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18 #define INTEL_UNLOCK_SLOW 1
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19
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20
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21 #undef tlw
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22 #define tlw(contents)
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23 #undef ttw
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24 #define ttw(contents)
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25
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26 // Status bits for Intel flash memory devices
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27 #define INTEL_STATE_MACHINE_DONE (1<<7)
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28 #define FLASH_READ(addr) (*(volatile uint16 *) (addr))
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29 #define FLASH_WRITE(addr, data) (*(volatile uint16 *) (addr)) = data
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30
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31 #ifdef __GNUC__
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32 asm(".globl ffsdrv_ram_intel_begin");
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33 asm("ffsdrv_ram_intel_begin:");
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34 #else
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35 asm(" .label _ffsdrv_ram_intel_begin");
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36 asm(" .def _ffsdrv_ram_intel_begin");
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37 #endif
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38
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39 uint32 intel_int_disable(void);
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40 void intel_int_enable(uint32 tmp);
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41
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42 /******************************************************************************
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43 * INTEL Single Bank Driver Functions
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44 ******************************************************************************/
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45 // Actually we should have disabled and enable the interrupts in this
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46 // function, but when the interrupt functions are used Target don't run!
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47 // Anyway, currently the interrupts are already disabled at this point thus
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48 // it does not cause any problems.
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49 int ffsdrv_ram_intel_sb_init(void)
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50 {
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51 uint32 cpsr, i;
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52 volatile char *addr;
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53 uint16 status;
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54
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55 for (i = 0; i < dev.numblocks; i++)
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56 {
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57 addr = block2addr(i);
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58
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59 *addr = 0x50; // Intel Clear Status Register
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60 *addr = 0xFF; // Intel read array
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61
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62 *addr = 0x60; // Intel Config Setup
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63 *addr = 0xD0; // Intel Unlock Block
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64
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65 // Wait for unlock to finish
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66 do {
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67 status = FLASH_READ(addr);
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68 } while (!(status & INTEL_STATE_MACHINE_DONE));
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69
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70 *addr = 0x70; // Intel Read Status Register
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71 status = FLASH_READ(addr);
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72
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73 // Is there an erase suspended?
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74 if ((status & 0x40) != 0) {
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75 *addr = 0xD0; // Intel erase resume
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76
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77 *addr = 0x70; // Intel Read Status Register
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78 // wait for erase to finish
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79 do {
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80 status = FLASH_READ(addr);
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81 } while (!(status & INTEL_STATE_MACHINE_DONE));
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82 }
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83
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84 *addr = 0xFF; // Intel Read Array
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85 }
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86
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87 return 0;
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88 }
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89
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90 void ffsdrv_ram_intel_sb_write_halfword(volatile uint16 *addr, uint16 value)
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91 {
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92 uint32 cpsr;
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93
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94 ttw(ttr(TTrDrv, "wh(%x,%x)" NL, addr, value));
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95
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96 if (~*addr & value) {
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97 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value));
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98 return;
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99 }
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100
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101 cpsr = intel_int_disable();
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102 tlw(led_on(LED_WRITE));
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103
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104 #if (INTEL_UNLOCK_SLOW == 1)
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105 *addr = 0x60; // Intel Config Setup
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106 *addr = 0xD0; // Intel Unlock Block
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107 #endif
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108
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109 *addr = 0x50; // Intel Clear Status Register
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110 *addr = 0x40; // Intel program byte/word
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111 *addr = value;
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112 while ((*addr & 0x80) == 0)
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113 ;
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114 *addr = 0xFF; // Intel read array
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115 tlw(led_off(LED_WRITE));
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116 intel_int_enable(cpsr);
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117 }
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118
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119 void ffsdrv_ram_intel_sb_erase(uint8 block)
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120 {
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121 volatile char *addr;
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122 uint32 cpsr;
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123 uint16 poll;
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124
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125 ttw(ttr(TTrDrvEra, "e(%d)" NL, block));
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126
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127 addr = block2addr(block);
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128
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129 cpsr = intel_int_disable();
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130 tlw(led_on(LED_ERASE));
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131
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132 #if (INTEL_UNLOCK_SLOW == 1)
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133 *addr = 0x60; // Intel Config Setup
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134 *addr = 0xD0; // Intel Unlock Block
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135 #endif
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136
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137 *addr = 0x50; // Intel Clear Status Register
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 *addr = 0x20; // Intel Erase Setup
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 *addr = 0xD0; // Intel Erase Confirm
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 *addr = 0x70; // Intel Read Status Register
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 // Wait for erase to finish.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 while ((*addr & 0x80) == 0) {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 tlw(led_toggle(LED_ERASE));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 // Poll interrupts, taking interrupt mask into account.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 if (INT_REQUESTED)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 // 1. suspend erase
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 // 2. enable interrupts
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 // .. now the interrupt code executes
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 // 3. disable interrupts
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 // 4. resume erase
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 tlw(led_on(LED_ERASE_SUSPEND));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 *addr = 0xB0; // Intel Erase Suspend
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 *addr = 0x70; // Intel Read Status Register
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 while (((poll = *addr) & 0x80) == 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 ;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 // If erase is complete, exit immediately
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 if ((poll & 0x40) == 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 break;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 *addr = 0xFF; // Intel read array
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 tlw(led_off(LED_ERASE_SUSPEND));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 intel_int_enable(cpsr);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 // Other interrupts and tasks run now...
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 cpsr = intel_int_disable();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 tlw(led_on(LED_ERASE_SUSPEND));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 *addr = 0xD0; // Intel erase resume
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 // The following "extra" Read Status command is required because Intel has
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 // changed the specification of the W30 flash! (See "1.8 Volt Intel®
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 // Wireless Flash Memory with 3 Volt I/O 28F6408W30, 28F640W30, 28F320W30
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 // Specification Update")
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 *addr = 0x70; // Intel Read Status Register
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 tlw(led_off(LED_ERASE_SUSPEND));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 *addr = 0xFF; // Intel read array
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 tlw(led_on(LED_ERASE));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 tlw(led_off(LED_ERASE));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 intel_int_enable(cpsr);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 // TODO: remove below function, not in use anymore.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 void ffsdrv_ram_intel_erase(uint8 block)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 uint32 cpsr;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 uint16 status;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 ttw(ttr(TTrDrvErase, "e(%d)" NL, block));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 tlw(led_on(LED_ERASE));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 dev.addr = (uint16 *) block2addr(block);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 cpsr = intel_int_disable();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 dev.state = DEV_ERASE;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206 *dev.addr = 0x60; // Intel Config setup
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 *dev.addr = 0xD0; // Intel Unlock block
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 *dev.addr = 0x50; // Intel clear status register (not really necessary)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 *dev.addr = 0x20; // Intel erase setup
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 *dev.addr = 0xD0; // Intel erase confirm
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 intel_int_enable(cpsr);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 while ((*dev.addr & 0x80) == 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 ;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 *dev.addr = 0xFF; // Intel read array
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 dev.state = DEV_READ;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 tlw(led_off(LED_WRITE));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 /******************************************************************************
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 * Interrupt Enable/Disable
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 ******************************************************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 #ifdef __GNUC__
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 #define NOINLINE __attribute__ ((noinline))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 #define NOINLINE
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 uint32 NOINLINE intel_int_disable(void)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 #ifdef __GNUC__
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 asm(" .code 16");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 asm(" .state16");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 asm(" mov A1, #0xC0");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 asm(" ldr A2, tct_intel_disable");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 asm(" bx A2 ");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 #ifdef __GNUC__
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 asm(".balign 4");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 asm("tct_intel_disable:");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 asm(" .word TCT_Control_Interrupts");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 asm("tct_intel_disable .field _TCT_Control_Interrupts+0,32");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 asm(" .global _TCT_Control_Interrupts");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 void NOINLINE intel_int_enable(uint32 cpsr)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 #ifdef __GNUC__
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 asm(" .code 16");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 asm(" .state16");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 asm(" ldr A2, tct_intel_enable");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 asm(" bx A2 ");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 #ifdef __GNUC__
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 asm(".balign 4");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 asm("tct_intel_enable:");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 asm(" .word TCT_Control_Interrupts");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 asm("tct_intel_enable .field _TCT_Control_Interrupts+0,32");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 asm(" .global _TCT_Control_Interrupts");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 // Even though we have this end label, we cannot determine the number of
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 // constant/PC-relative data following the code!
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 #ifdef __GNUC__
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278 asm(".globl ffsdrv_ram_intel_end");
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279 asm("ffsdrv_ram_intel_end:");
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280 #else
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Mychaela Falconia <falcon@freecalypso.org>
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281 asm(" .state32");
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282 asm(" .label _ffsdrv_ram_intel_end");
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283 asm(" .def _ffsdrv_ram_intel_end");
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284 #endif