ffs-editor: src/cs/layer1/tpu_drivers/source0/tpudrv12.h annotate

annotate src/cs/layer1/tpu_drivers/source0/tpudrv12.h @ 14:4f94a09e0a6a

ETM patches for passing link

author	Mychaela Falconia <falcon@freecalypso.org>
date	Fri, 15 May 2020 04:31:50 +0000
parents	92470e5d0b9e
children

rev	line source
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /**************** Revision Controle System Header *********************
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 * GSM Layer 1 software
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 * Copyright (c) Texas Instruments 1998
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * Filename tpudrv12.h
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 * Copyright 2003 (C) Texas Instruments
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 **************** Revision Controle System Header *********************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 //--- Configuration values
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 #define FEM_TEST 0 // 1 => ENABLE the FEM_TEST mode
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12 #define RF_VERSION 1 // 1 or V1, 5 for V5, etc
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 #define SAFE_INIT_WA 0 // 1 => ENABLE the "RITA safe init"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 // TeST - Enable Main VCO buffer for test
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 #define MAIN_VCO_ACCESS_WA 0 // 1 => ENABLE the Main VCO buffer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 #include "rf.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 #include "fc-target.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 //--- RITA PG declaration
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 #define R_PG_10 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 #define R_PG_13 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 #define R_PG_20 2 // For RFPG 2.2, use 2.0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 #define R_PG_23 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 //--- PA declaration
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28 #define PA_MGF9009 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 #define PA_RF3146 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 #define PA_RF3133 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 #define PA_PF08123B 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 #define PA_AWT6108 4
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34 #if (RF_PA == PA_MGF9009 \|\| RF_PA == PA_PF08123B)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 #define PA_CTRL_INT 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 #define PA_CTRL_INT 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40 //- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 // AlphaRF7 => "PG #1.3" for TPU purposes (not an official PC number)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 // This is also used in l1_rf12.h to select the SWAP_IQ
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43 #if (RF_PG >= R_PG_20)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 #define PLL2_WA 0 // 0 => DISABLE the PLL2_WA (Rene's "Work-Around")
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #define ALPHA_RF7_WA 0 // 0 => DISABLE the Alpha RF7 work-arounds
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #elif (RF_PG == R_PG_13)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 //- Bit definitions for TST register programings, etc
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 #define BIT_0 0x000001
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 #define BIT_1 0x000002
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60 #define BIT_2 0x000004
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #define BIT_3 0x000008
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #define BIT_4 0x000010
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #define BIT_5 0x000020
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 #define BIT_6 0x000040
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 #define BIT_7 0x000080
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 #define BIT_8 0x000100
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 #define BIT_9 0x000200
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 #define BIT_10 0x000400
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 #define BIT_11 0x000800
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70 #define BIT_12 0x001000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 #define BIT_13 0x002000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 #define BIT_14 0x004000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 #define BIT_15 0x008000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 #define BIT_16 0x010000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 #define BIT_17 0x020000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 #define BIT_18 0x040000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 #define BIT_19 0x080000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78 #define BIT_20 0x100000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79 #define BIT_21 0x200000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 #define BIT_22 0x400000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 #define BIT_23 0x800000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 //--- TRF6151 definitions ------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 //- BASE REGISTER definitions
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 #define REG_RX 0x000000 // MODE0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 #define REG_PLL 0x000001 // MODE1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88 #define REG_PWR 0x000002 // MODE2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #define REG_CFG 0x000003 // MODE3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 //- TeST REGISTER definitions => Used for WA only
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92 // TeST - PLL2 WA => Define PLL2 TEST register
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 #define TST_PLL2 0x00001E // MODE 14
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 // TeST - Enable Main VCO buffer for test => Define TST_VCO3 register
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96 #define TST_VCO3 0x00000F // MODE 15 (016+151)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97 #define TST_VCO4 0x000024 // MODE 36 (216+41)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 // Alpha RF7 WA TeST registers
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 #define TST_LDO 0x000027 // MODE 39 (216+71)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 #define TST_PLL1 0x00001D // MODE 29 (116+131)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102 #define TST_TX2 0x000037 // MODE 55 (316+71)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 // More Alpha RF7 WA TeST registers
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105 #define TST_TX3 0x00003C // MODE 61 (316+121)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 #define TST_TX4 0x00003D // MODE 61 (316+131)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108 // PG 2.1 WA TeST registers
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109 #define TST_PLL3 0x00001F // MODE 31 (116+151)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 // #define TST_PLL4 0x00002C // MODE 44 (216+121)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 #define TST_MISC 0x00003E // MODE 62 (316+141) => Used for setting the VCXO current
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112 #define TST_LO 0x00001C // MODE 28 (116+121)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114 // Registers used to improve the Modulation Spectrum in DCS/PCS for PG2.1 V1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 // UPDATE_SERIAL_REGISTER_COPY is a "dummy addres" that,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 // when accessed, triggers the copy of the serial registers.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 // This is necessary to switch into "manual operation mode"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 #define UPDATE_SERIAL_INTERFACE_COPY 0x000007
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119 #define TX_LOOP_MANUAL BIT_3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 //- REG_RX - MODE0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 #define BLOCK_DETECT_0 BIT_3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124 #define BLOCK_DETECT_1 BIT_4
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 #define RST_BLOCK_DETECT_0 BIT_5
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 #define RST_BLOCK_DETECT_1 BIT_6
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127 #define READ_EN BIT_7
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128 #define RX_CAL_MODE BIT_8
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 #define RF_GAIN (BIT_10 \| BIT_9)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 //- REG_PLL - MODE1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133 //PLL_REGB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134 //PLL_REGA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136 //- REG_PWR - MODE2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 #define BANDGAP_MODE_OFF 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 #define BANDGAP_MODE_ON_ENA BIT_4
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 #define BANDGAP_MODE_ON_DIS (BIT_4 \| BIT_3)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 #define REGUL_MODE_ON BIT_5
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141 // BIT[8..6] band
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 #define BAND_SELECT_GSM BIT_6
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 #define BAND_SELECT_DCS BIT_7
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 #define BAND_SELECT_850_LO BIT_8
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145 #define BAND_SELECT_850_HI (BIT_8 \| BIT_6)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146 #define BAND_SELECT_PCS (BIT_8 \| BIT_7)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 #define SYNTHE_MODE_OFF 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149 #define SYNTHE_MODE_RX BIT_9
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 #define SYNTHE_MODE_TX BIT_10
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 #define RX_MODE_OFF 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152 #define RX_MODE_A BIT_11
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 #define RX_MODE_B1 BIT_12
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 #define RX_MODE_B2 (BIT_12 \| BIT_11)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155 #define TX_MODE_OFF 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156 #define TX_MODE_ON BIT_13
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 #define PACTRL_APC_OFF 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 #define PACTRL_APC_ON BIT_14
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159 #define PACTRL_APC_DIS 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 #define PACTRL_APC_ENA BIT_15
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 //- REG_CFG - MODE3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 // Common PA controller settings:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 #define PACTRL_TYPE_PWR 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 #define PACTRL_TYPE_CUR BIT_3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167 #define PACTRL_IDIOD_30_UA 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 #define PACTRL_IDIOD_300_UA BIT_4
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170 // PA controller Clara-like (Power Sensing) settings:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 #define PACTRL_VHOME_610_MV (BIT_7 \| BIT_5)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172 #define PACTRL_VHOME_839_MV (BIT_7 \| BIT_5)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 #define PACTRL_VHOME_1000_MV (BIT_6 \| BIT_9)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174 #define PACTRL_VHOME_1600_MV (BIT_8 \| BIT_5)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 #define PACTRL_RES_OPEN 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176 #define PACTRL_RES_150_K BIT_10
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177 #define PACTRL_RES_300_K BIT_11
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 #define PACTRL_RES_NU (BIT_10 \| BIT_11)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 #define PACTRL_CAP_0_PF 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180 #define PACTRL_CAP_12_5_PF BIT_12
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 #define PACTRL_CAP_25_PF (BIT_13 \| BIT_12)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 #define PACTRL_CAP_50_PF BIT_13
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184 // PACTRL_CFG contains the configuration of the PACTRL that will
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185 // be put into the REG_CFG register at initialization time
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 // WARNING - Do not forget to set the PACTRL_TYPE (PWR or CUR)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 // in this #define!!!
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 #if (RF_PA == 0) // MGF9009 (LCPA)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 #define PACTRL_CFG \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190 PACTRL_IDIOD_300_UA \| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 PACTRL_CAP_25_PF \| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192 PACTRL_VHOME_1000_MV \| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 PACTRL_RES_300_K
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 #elif (RF_PA == 1) // 3146
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 #define PACTRL_CFG 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197 #elif (RF_PA == 2) // 3133
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 #define PACTRL_CFG 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200 #elif (RF_PA == 3) // PF08123B
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 #define PACTRL_CFG \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202 PACTRL_TYPE_PWR \| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203 PACTRL_CAP_50_PF \| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 PACTRL_RES_300_K \| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205 PACTRL_VHOME_610_MV
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 #elif (RF_PA == 4) // AWT6108
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 #define PACTRL_CFG 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 #error Unknown PA specifiec!
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212 // Temperature sensor
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 #define TEMP_SENSOR_OFF 0x0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214 #define TEMP_SENSOR_ON BIT_14
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 // Internal Logic Init Disable
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216 #define ILOGIC_INIT_DIS BIT_15
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217 // ILOGIC_INIT_DIS must be ALWAYS set when programming the REG_CFG register
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 // It was introduced in PG 1.2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 // For previous PGs this BIT was unused, so it can be safelly programmed
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 // for all PGs
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223 // RF signals connected to TSPACT [0..7]
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225 #ifdef CONFIG_TARGET_PIRELLI
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 #define RF_RESET_LINE BIT_5
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228 #define RF_RESET_LINE BIT_0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231 #define RF_SER_ON RF_RESET_LINE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 #define RF_SER_OFF 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234 #define TEST_TX_ON 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235 #define TEST_RX_ON 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237 #if defined(CONFIG_TARGET_LEONARDO) \|\| defined(CONFIG_TARGET_ESAMPLE) \|\| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238 defined(CONFIG_TARGET_TANGO)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 // 4-band config (E-sample, P2, Leonardo)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 #define FEM_7 BIT_2 // act2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 #define FEM_8 BIT_1 // act1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243 #define FEM_9 BIT_4 // act4
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 #define PA_HI_BAND BIT_3 // act3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246 #define PA_LO_BAND 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 #define PA_OFF 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249 #define FEM_PINS (FEM_7 \| FEM_8 \| FEM_9)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251 #define FEM_OFF ( FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253 #define FEM_SLEEP ( 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 // This configuration is always inverted.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257 // RX_UP/DOWN and TX_UP/DOWN
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_7 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 #define RU_850 ( PA_OFF \| FEM_PINS ^ FEM_9 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_7 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_8 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_8 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278 #elif defined(CONFIG_TARGET_GTAMODEM)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 // Openmoko's triband configuration is a bastardized version
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281 // of TI's quadband one from Leonardo/E-Sample
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 #define FEM_7 BIT_2 // act2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284 #define FEM_8 BIT_1 // act1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285 #define FEM_9 BIT_4 // act4
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287 #define PA_HI_BAND BIT_3 // act3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288 #define PA_LO_BAND 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289 #define PA_OFF 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291 #define FEM_PINS (FEM_7 \| FEM_8 \| FEM_9)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293 #define FEM_OFF ( FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295 #define FEM_SLEEP ( 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297 // This configuration is always inverted.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299 // RX_UP/DOWN and TX_UP/DOWN
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_9 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_9 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_7 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 #define RU_1900 ( PA_OFF \| FEM_PINS ^ FEM_8 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_7 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320 #elif defined(CONFIG_TARGET_FCFAM)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323 * In our FreeCalypso hw family, we would like to be able to use
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324 * both triband and quadband RFFEs. Our current FCDEV3B is triband,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325 * copied from Openmoko, and the same is expected to be the case for
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326 * future low-budget designs, but if someone pays for a new RF layout,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327 * we can use a quadband RFFE instead. If we ever have two different
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328 * hw platforms or variants that differ in the RFFE but are otherwise
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 * firmware-compatible, we would like to have the same fw build
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330 * work with both triband and quadband RFFEs. How is it possible?
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 * The trick is that we define our set of TSPACT RFFE control signals
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332 * starting with our current OM-based triband version, and add one
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333 * more signal to support potential future quadband designs.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336 #define FEM_RX_1900 BIT_1 // act1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337 #define FEM_TX_HIGH BIT_2 // act2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 #define FEM_TX_LOW BIT_4 // act4
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339 #define FEM_RX_850 BIT_5 // act5
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	340
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341 #define PA_HI_BAND BIT_3 // act3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342 #define PA_LO_BAND 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343 #define PA_OFF 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 #define FEM_PINS (FEM_TX_LOW \| FEM_TX_HIGH \| FEM_RX_850 \| FEM_RX_1900)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347 #define FEM_OFF ( FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349 #define FEM_SLEEP ( 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 // This configuration is always inverted.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353 // RX_UP/DOWN and TX_UP/DOWN
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359 #define RU_850 ( PA_OFF \| FEM_PINS ^ FEM_RX_850 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369 #define RU_1900 ( PA_OFF \| FEM_PINS ^ FEM_RX_1900 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 #elif defined(CONFIG_TARGET_MGC2GSMT)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377 * The common MGC2GSMT version of Huawei GTM900-B is very closely based
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378 * on Leonardo (2-band version), but the two FEM Tx control signals
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379 * are reversed.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 #define FEM_TX_LOW BIT_1 // act1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383 #define FEM_TX_HIGH BIT_2 // act2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385 #define PA_HI_BAND BIT_3 // act3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386 #define PA_LO_BAND 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 #define PA_OFF 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389 #define FEM_PINS (FEM_TX_LOW \| FEM_TX_HIGH)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391 #define FEM_OFF ( FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393 #define FEM_SLEEP ( 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395 // This configuration is always inverted.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397 // RX_UP/DOWN and TX_UP/DOWN
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418 #elif defined(CONFIG_TARGET_PIRELLI)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 #define ANTSW_RX_PCS BIT_4
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421 #define ANTSW_TX_HIGH BIT_10
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422 #define ANTSW_TX_LOW BIT_11
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424 #define PA_HI_BAND BIT_3 // act3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425 #define PA_LO_BAND 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 #define PA_OFF 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428 #define PA_ENABLE BIT_0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430 // Pirelli uses a non-inverting buffer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432 #define FEM_OFF ( 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434 #define FEM_SLEEP ( 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436 // RX_UP/DOWN and TX_UP/DOWN (triband)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 #define RU_900 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438 #define RD_900 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439 #define TU_900 ( PA_LO_BAND \| ANTSW_TX_LOW )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440 #define TD_900 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442 #define RU_850 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443 #define RD_850 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444 #define TU_850 ( PA_LO_BAND \| ANTSW_TX_LOW )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 #define TD_850 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447 #define RU_1800 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 #define RD_1800 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449 #define TU_1800 ( PA_HI_BAND \| ANTSW_TX_HIGH )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450 #define TD_1800 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 #define RU_1900 ( PA_OFF \| ANTSW_RX_PCS )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453 #define RD_1900 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454 #define TU_1900 ( PA_HI_BAND \| ANTSW_TX_HIGH )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455 #define TD_1900 ( PA_OFF \| 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457 #elif defined(CONFIG_TARGET_COMPAL)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459 #define PA_HI_BAND BIT_8 // act8
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460 #define PA_LO_BAND 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 #define PA_OFF 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463 #define PA_ENABLE BIT_1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465 // FEM control signals are active low
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466 #define FEM_PINS (BIT_6 \| BIT_2)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 #define FEM_OFF ( FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470 #define FEM_SLEEP ( 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472 #define FEM_TX_HIGH BIT_6
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473 #if USE_TSPACT2_FOR_TXLOW
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474 #define FEM_TX_LOW BIT_2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476 #define FEM_TX_LOW BIT_6
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479 // RX_UP/DOWN and TX_UP/DOWN
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480 #define RU_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481 #define RD_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482 #define TU_900 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483 #define TD_900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485 #define RU_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486 #define RD_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 #define TU_850 ( PA_LO_BAND \| FEM_PINS ^ FEM_TX_LOW )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488 #define TD_850 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490 #define RU_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491 #define RD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492 #define TU_1800 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 #define TD_1800 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495 #define RU_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496 #define RD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497 #define TU_1900 ( PA_HI_BAND \| FEM_PINS ^ FEM_TX_HIGH )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498 #define TD_1900 ( PA_OFF \| FEM_PINS ^ 0 )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500 #endif // FreeCalypso target selection
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 #define TC1_DEVICE_ABB TC1_DEVICE0 // TSPEN0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503 #ifdef CONFIG_TARGET_PIRELLI
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504 #define TC1_DEVICE_RF TC1_DEVICE1 // TSPEN1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506 #define TC1_DEVICE_RF TC1_DEVICE2 // TSPEN2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510 //--- TIMINGS ----------------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 /------------------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513 /* Download delay values */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 /------------------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515 // 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 #define T TPU_CLOCK_RANGE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 // - TPU instruction into TSP timings ---
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521 // 1 tpu instruction = 1 qbit
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 #define DLT_1 1 // 1 tpu instruction = 1 qbit
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523 #define DLT_2 2 // 2 tpu instruction = 2 qbit
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524 #define DLT_3 3 // 3 tpu instruction = 3 qbit
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	525 #define DLT_4 4 // 4 tpu instruction = 4 qbit
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526 #define SL_SU_DELAY2 DLT_3 // Needed to compile with old l1_rf12
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	528 // - Serialization timings ---
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529 // The following values where calculated with Katrin Matthes...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530 //#define SL_7 3 // To send 7 bits to the ABB, 14*T (1/6.5MHz) are needed,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	531 // // i.e. 14 / 6 qbit = 2.333 ~ 3 qbit
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532 //#define SL_2B 6 // To send 2 bytes to the RF, 34*T (1/6.5MHz) are needed,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533 // // i.e. 34 / 6 qbit = 5.7 ~ 6 qbit
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534 // ... while the following values are based on the HYP004.doc document
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 #define SL_7 2 // To send 7 bits to the ABB, 12*T (1/6.5MHz) are needed,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536 // i.e. 12 / 6 qbit = 2 qbit
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537 #define SL_2B 4 // To send 2 bytes to the RF, 21*T (1/6.5MHz) are needed,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 // i.e. 21 / 6 qbit = 3.5 ~ 4 qbit
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	539
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540 // - TPU command execution + serialization length ---
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 #define DLT_1B 4 // 3*move + serialization of 7 bits
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	542 #define DLT_2B 7 // 4*move + serialization of 2 bytes
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543 //#define DLT_1B DLT_3 + SL_7 // 3*move + serialization of 7 bits
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544 //#define DLT_2B DLT_4 + SL_2B // 4*move + serialization of 2 bytes
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547 // - INIT (delta or DLT) timings ---
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 #define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549 #define DLT_I2 8 // Time required to set RF_SER_OFF
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 #define DLT_I3 5 // Time required to set RF_SER_ON
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551 #define DLT_I4 110 // Regulator Turn-ON time
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554 // - tdt & rdt ---
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555 // MAX GSM (not GPRS) rdt and tdt values are...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 //#define rdt 380 // MAX GSM rx delta timing
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	557 //#define tdt 400 // MAX GSM tx delta timing
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	558 // but current rdt and tdt values are...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 #define rdt 0 // rx delta timing
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560 #define tdt 0 // tx delta timing
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	562 // - RX timings ---
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563 // - RX down:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	564 // The times below are offsets to when BDLENA goes down
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565 #define TRF_R10 ( 0 - DLT_1B ) // disable BDLENA & BDLON -> power DOWN ABB (end of RX burst), needs DLT_1B to execute
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566 #define TRF_R9 ( - 30 - DLT_2B ) // disable RF SWITCH, power DOWN Rita (go to Idle2 mode)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	567
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568 // - RX up:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	569 // The times below are offsets to when BDLENA goes high
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	570 // Burst data comes here
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	571 #define TRF_R8 ( PROVISION_TIME - 0 - DLT_1B ) // enable BDLENA, disable BDLCAL (I/Q comes 32qbit later)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	572 #define TRF_R7 ( PROVISION_TIME - 7 - DLT_1 ) // enable RF SWITCH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	573 #define TRF_R6 ( PROVISION_TIME - 67 - DLT_1B ) // enable BDLCAL -> ABB DL filter init
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	574 #define TRF_R5 ( PROVISION_TIME - 72 - DLT_1B ) // enable BDLON -> power ON ABB DL path
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	575 #define TRF_R4 ( PROVISION_TIME - 76 - DLT_2B - rdt ) // power ON RX
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	576 #define TRF_R3 (PROVISION_TIME - 143 - DLT_2B - rdt ) // select the AGC & LNA gains + start DC offset calibration (stops automatically)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	577 //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	578 #define TRF_R2 (PROVISION_TIME - 198 - DLT_2B - rdt ) // set BAND + power ON RX Synth
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	579 #define TRF_R1 (PROVISION_TIME - 208 - DLT_2B - rdt ) // set RX Synth channel
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	580
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	581 // - TX timings ---
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	582 // - TX down:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	583 // The times below are offsets to when BULENA goes down
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	584
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	585 #if (PA_CTRL_INT == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	586 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	587 #define TRF_T12_5 ( 32 - DLT_2B ) // Power OFF TX loop => power down RF.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	588 #define TRF_T12_3 ( 23 - DLT_1 ) // Disable TXEN.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	589 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	590
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	591 #if (PA_CTRL_INT == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	592 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	593 #define TRF_T12_2 ( 32 - DLT_2B ) // power down RF step 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	594 #define TRF_T12 ( 18 - DLT_2B ) // power down RF step 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	595 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	596
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	597 #define TRF_T11 ( 0 - DLT_1B ) // disable BULENA -> end of TX burst
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	598 #define TRF_T10_5 ( - 40 - DLT_1B ) // ADC read
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	599
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	600 // - TX up:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	601 // The times below are offsets to when BULENA goes high
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	602 //burst data comes here
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	603 #define TRF_T10_4 ( 22 - DLT_1 ) // enable RF SWITCH + TXEN
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	604 #define TRF_T10 ( 17 - DLT_1 ) // enable RF SWITCH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	605
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	606 #if (PA_CTRL_INT == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	607 #define TRF_T9 ( 8 - DLT_2B ) // enable PACTRL
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	608 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	609
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	610 #define TRF_T8 ( - 0 - DLT_1B ) // enable BULENA -> start of TX burst
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	611 #define TRF_T7 ( - 50 - DLT_1B - tdt ) // disable BULCAL -> stop ABB UL calibration
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	612 #define TRF_T6 ( - 130 - DLT_1B - tdt ) // enable BULCAL -> start ABB UL calibration
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	613 #define TRF_T5 ( - 158 - DLT_2B - tdt ) // power ON TX
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	614 #define TRF_T4 ( - 190 - DLT_1B - tdt ) // enable BULON -> power ON ABB UL path
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	615 // TRF_T3_MAN_1, TRF_T3_MAN_2 & TRF_T3_MAN_3 are only executed in DCS for PG 2.0 and above
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	616 #define TRF_T3_MAN_3 ( - 239 - DLT_2B - tdt ) // PG2.1: Set the right TX loop charge pump current for DCS & PCS
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	617 #define TRF_T3_MAN_2 ( - 249 - DLT_2B - tdt ) // PG2.1: Go into "TX Manual mode"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	618 #define TRF_T3_MAN_1 ( - 259 - DLT_2B - tdt ) // PG2.1: IN DCS, use manual mode: Copy Serial Interface Registers for "Manual operation"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	619 #define TRF_T3 ( - 259 - DLT_2B - tdt ) // PG2.1: In GSM & PCS go to "Automatic TX mode"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	620 #define TRF_T2 ( - 269 - DLT_2B - tdt ) // PG2.0: set BAND + Power ON Main TX PLL + PACTRL ON
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	621 #define TRF_T1 ( - 279 - DLT_2B - tdt ) // set TX Main PLL channel
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	622

FreeCalypso > hg > ffs-editor

annotate src/cs/layer1/tpu_drivers/source0/tpudrv12.h @ 14:4f94a09e0a6a