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annotate src/cs/layer1/cust0/l1_rf12.h @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 *
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4 * Filename l1_rf12.h
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5 * Copyright 2003 (C) Texas Instruments
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6 *
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7 ************* Revision Controle System Header *************/
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8
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9 #ifndef __L1_RF_H__
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10 #define __L1_RF_H__
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11
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12 #include "fc-target.h"
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13
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14 #define RF_RITA_10 0x2030 // Check with TIDK
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15
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16 //#define RF_HW_BAND_EGSM
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17 //#define RF_HW_BAND_DCS
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18 #define RF_HW_BAND_PCS 0x4
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19 #define RF_HW_BAND_DUAL_US 0x80
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20 #define RF_HW_BAND_DUAL_EXT 0x20
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21
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22 //#define RF_HW_BAND_SUPPORT (0x0020 | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS
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23 // radio_band_support E-GSM/DCS + GSM850/PCS
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24 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_DUAL_US)
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25
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26 // L1 RF SW Multiband configuration
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27 //--------------------------
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28
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29 // RF_SW_MULTIBAND_SUPPORT values
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30 #define SINGLE_BAND_900 1
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31 #define SINGLE_BAND_1800 2
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32 #define SINGLE_BAND_850 3
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33 #define SINGLE_BAND_1900 4
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34 #define DUAL_BAND_900_1800 5
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35 #define DUAL_BAND_850_1900 6
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36 #define TRI_BAND_900_1800_1900 7
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37 #define TRI_BAND_850_1900_1800 8
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38 #define QUAD_BAND 9
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39
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40 //IMPORTANT !: To change RF_SW_MULTIBAND_SUPPORT value, it must be synchronized with other multiband settings in the software
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41 // To match the protocol stack settings( e.g EF_RFCAP ) in order to make sure that the value of STD sent in MPHC_INIT_L1_REQ is supported by L1
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42 // And also match the RF HW support: RF_HW_BAND_SUPPORT
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43 #define RF_SW_MULTIBAND_SUPPORT QUAD_BAND
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44
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45 // Generate band dependancy options
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46 #define RF_SW_BAND900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
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47 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND) )
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48
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49 #define RF_SW_BAND1800 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1800) ||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
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50 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
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51 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
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52
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53 #define RF_SW_BAND850 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_850)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
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54 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
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55
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56 #define RF_SW_BAND1900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
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57 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900)||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
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58 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
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59
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60 /************************************/
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61 /* SYNTHESIZER setup time... */
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62 /************************************/
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63 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit.
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64 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
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65
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66 /************************************/
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67 /* time for TPU scenario ending... */
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68 /************************************/
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69 //
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70 // The following values are used to take into account any TPU activity AFTER
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71 // BDLON (or BDLENA) down (for RX) and BULON down (for TX)
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72 // - If there are no TPU commands after BDLON (or BDLENA) down and BULON down,
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73 // these defines must be ZERO
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74 // - If there IS some TPU command after BDLON (or BDLENA) and BULON down,
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75 // these defines must be equal to the time difference (in qbits) between
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76 // the BDLON (or BDLENA) or BULON time and the last TPU command on
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77 // the TPU scenario
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78 #define RX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BDLENA down
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79 #define TX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BULON down
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80
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81
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82 /******************************************************/
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83 /* TXPWR configuration... */
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84 /* Fixed TXPWR value when GSM management is disabled. */
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85 /******************************************************/
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86
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87 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
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88 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252
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89 //#define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE)
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90 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15
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91 #endif
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92
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93
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94 /************************************/
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95 /* ANALOG delay (in qbits) */
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96 /************************************/
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97 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
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98 #define UL_DELAY_1RF 7 // time spent in the first uplink RF block
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99 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
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100 #if (ANLG_FAM == 1)
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101 #define UL_ABB_DELAY 3 // modulator input to output delay
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102 #endif
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103 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
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104 #define UL_ABB_DELAY 3 // modulator input to output delay
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105 #endif
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106
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107 /************************************/
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108 /* TX Propagation delay... */
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109 /************************************/
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110 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
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111 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
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112 #endif
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113
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114 /************************************/
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115 /* Initial value for APC DELAY */
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116 /************************************/
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117 #if (ANLG_FAM == 1)
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118 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
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119 #define APCDEL_DOWN 2 // minimum value: 2
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120 #define APCDEL_UP (6+5) // minimum value: 6
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121 #endif
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122
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123 #if (ANLG_FAM == 2) || (ANLG_FAM == 3)
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124 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
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125 #define APCDEL_DOWN (2+0) // minimum value: 2
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parents:
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126 #define APCDEL_UP (6+3+1) // minimum value: 6
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parents:
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127 // REMOVE // Jerome Modif for ARF7: (6+3) instead of (6+8)
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parents:
diff changeset
128 #endif
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129
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130 #define GUARD_BITS 7
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131
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132 /************************************/
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133 /* Initial value for AFC... */
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134 /************************************/
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135 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
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136
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diff changeset
137 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames and RF BAND GAP stable after 4 frames
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138 // Rita (RF=12) LDO wakeup requires 6 frames
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139
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140 /************************************/
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parents:
diff changeset
141 /* Baseband registers */
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142 /************************************/
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143 #if (ANLG_FAM == 1)
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144 // Omega registers values will be programmed at 1st DSP communication interrupt
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145 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
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146 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
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parents:
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147 #define C_VBUCTRL ((0x106 << 6) | VBUCTRL | TRUE) // Uplink gain amp 0dB, Sidetone gain to mute
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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148 #define C_VBDCTRL ((0x026 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control 0 dB
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parents:
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149 // RITA does not need an APCOFFSET because the PACTRL is internal:
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150 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // value at reset-Changed from 0x0016- CR 27.12
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parents:
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151 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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152 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
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Mychaela Falconia <falcon@freecalypso.org>
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153 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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154 #define C_DAI_ON_OFF (0x000) // value at reset
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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155 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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156 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
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Mychaela Falconia <falcon@freecalypso.org>
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157 // BULRUDEL will be initialized on rach only ....
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diff changeset
158 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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159 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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160 #endif
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161
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parents:
diff changeset
162 #if (ANLG_FAM == 2)
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163
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parents:
diff changeset
164 // IOTA registers values will be programmed at 1st DSP communication interrupt
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165
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166 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
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parents:
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167 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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168 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3 dB, Sidetone gain to -17dB
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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170 // RITA does not need an APCOFFSET because the PACTRL is internal:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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171 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // x2 slope 128
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 #if (RF_PA == 0 || RF_PA == 3) || defined(CONFIG_TARGET_PIRELLI)
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parents:
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173 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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174 #elif defined(CONFIG_TARGET_C1XX)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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175 #define C_APCOFF ((0x060 << 6) | APCOFF | TRUE) // x2 slope 128
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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176 #elif defined(CONFIG_TARGET_J100)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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177 #define C_APCOFF ((0x074 << 6) | APCOFF | TRUE) // x2 slope 128
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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178 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4)
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parents:
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179 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128
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Mychaela Falconia <falcon@freecalypso.org>
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180 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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181 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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182 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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183 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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184 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
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185
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186
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parents:
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187 // audio patch for H2-sample:
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parents:
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188 #if (RAZ_VULSWITCH_REGAUDIO == 1)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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189 #define C_VBCTRL1 ((0x003 << 6) | VBCTRL1 | TRUE) // VBDFAUXG = 1, VULSWITCH=0, VDLAUX=1, VDLEAR=1 // jkb h2sample change
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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190 #else
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parents:
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191 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
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parents:
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192 #endif
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193
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194
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195 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE) // MICBIASEL=0, VDLHSO=0, MICAUX=0
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parents:
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196 // BULRUDEL will be initialized on rach only ....
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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197 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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198 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) //
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199 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V
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200 // Monoslot, Vpp=8/15*Vref
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parents:
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201 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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202 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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203
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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204 #if (ANLG_FAM == 3)
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205
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parents:
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206 // SYREN registers values will be programmed at 1st DSP communication interrupt
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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207
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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209 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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210 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3dB, Sidetone gain to -17 dB
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 #if (RF_PA == 0 || RF_PA == 3)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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213 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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216 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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219 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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220 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE) // VULSWITCH=1 AUXI 28,2 dB
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE) // HSMIC on, SPKG gain @ 2,5dB
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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223
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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224 // BULRUDEL will be initialized on rach only ....
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6)<<6) | APCDEL1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
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226 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) //
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 // Monoslot, Vpp=8/15*Vref
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE) // HSOAUTO enabled only
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE) // Init to zero
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE) // Speech on all outputs
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE) // Init to zero
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE) // Init to zero
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 #define C_BBCFG (0x44) // Syren Like BDLF Filter - DC OFFSET removal OFF
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241
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diff changeset
242 #endif
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243
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244
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diff changeset
245 /************************************/
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parents:
diff changeset
246 /* Automatic frequency compensation */
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parents:
diff changeset
247 /************************************/
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parents:
diff changeset
248 /********************* C_Psi_sta definition *****************************/
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parents:
diff changeset
249 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
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parents:
diff changeset
250 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
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parents:
diff changeset
251 /* regarding Vega V/N = 2.4/4096 */
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parents:
diff changeset
252 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
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parents:
diff changeset
253 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
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parents:
diff changeset
254 /* = 0.000195748 */
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parents:
diff changeset
255 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
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parents:
diff changeset
256 /************************************************************************/
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257
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diff changeset
258 #ifdef CONFIG_TARGET_PIRELLI
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259
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parents:
diff changeset
260 /* matching Pirelli's fw as read out via rftr 9 */
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parents:
diff changeset
261 #define C_Psi_sta_inv 6974L // (1/C_Psi_sta)
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diff changeset
262 #define C_Psi_st 8L // C_Psi_sta * 0.8 F0.16
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parents:
diff changeset
263 #define C_Psi_st_32 492713L // F0.32
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parents:
diff changeset
264 #define C_Psi_st_inv 8717L // (1/C_Psi_st)
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265
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parents:
diff changeset
266 #elif defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_FCFAM)
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parents:
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267
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parents:
diff changeset
268 /*
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parents:
diff changeset
269 * We calibrate our VCXO per unit following OM's precedent,
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parents:
diff changeset
270 * thus the compiled-in AFC params don't really matter on FC/OM targets,
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parents:
diff changeset
271 * but let's put in some numbers that are representative of our VCXO,
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parents:
diff changeset
272 * as opposed to the totally wrong numbers corresponding to the
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parents:
diff changeset
273 * significantly different VCXO on the original Leonardo.
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274 */
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275
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diff changeset
276 #define C_Psi_sta_inv 3462L // (1/C_Psi_sta)
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parents:
diff changeset
277 #define C_Psi_st 15L // C_Psi_sta * 0.8 F0.16
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parents:
diff changeset
278 #define C_Psi_st_32 992326L // F0.32
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parents:
diff changeset
279 #define C_Psi_st_inv 4328L // (1/C_Psi_st)
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parents:
diff changeset
280
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parents:
diff changeset
281 #else
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diff changeset
282
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parents:
diff changeset
283 /* original TCS211 values */
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parents:
diff changeset
284 #define C_Psi_sta_inv 5419L // (1/C_Psi_sta)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 #define C_Psi_st 10L // C_Psi_sta * 0.8 F0.16
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parents:
diff changeset
286 #define C_Psi_st_32 634112L // F0.32
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parents:
diff changeset
287 #define C_Psi_st_inv 6773L // (1/C_Psi_st)
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parents:
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288
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parents:
diff changeset
289 #endif
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290
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 #if (VCXO_ALGO == 1)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 // Linearity parameters
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293
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 #ifdef CONFIG_TARGET_COMPAL
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parents:
diff changeset
295 /* matching Compal's fw as read out via rftr 9 */
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parents:
diff changeset
296 #define C_AFC_DAC_CENTER ((1000)*8)
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parents:
diff changeset
297 #define C_AFC_DAC_MIN ((-500)*8)
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parents:
diff changeset
298 #define C_AFC_DAC_MAX ((2500)*8)
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parents:
diff changeset
299 #else
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parents:
diff changeset
300 /* original TCS211 values */
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parents:
diff changeset
301 #define C_AFC_DAC_CENTER ((111)*8)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 #define C_AFC_DAC_MIN ((-1196)*8)
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parents:
diff changeset
303 #define C_AFC_DAC_MAX ((1419)*8)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 #endif
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parents:
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305
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10
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parents:
diff changeset
307 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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308
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parents:
diff changeset
309 typedef struct
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parents:
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310 {
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parents:
diff changeset
311 WORD16 eeprom_afc;
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parents:
diff changeset
312 UWORD32 psi_sta_inv;
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parents:
diff changeset
313 UWORD32 psi_st;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 UWORD32 psi_st_32;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 UWORD32 psi_st_inv;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 #if (VCXO_ALGO)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 // VCXO adjustment parameters
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 // Parameters used when assuming linearity
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 WORD16 dac_center;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 WORD16 dac_min;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 WORD16 dac_max;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 WORD16 snr_thr;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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325 }
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 T_AFC_PARAMS;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327
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parents:
diff changeset
328 /************************************/
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 /* Swap IQ definitions... */
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Mychaela Falconia <falcon@freecalypso.org>
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diff changeset
330 /************************************/
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 #if (RF_PG == R_PG_10)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 // PG 1.0 -> 1 (Swap RX only)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 // GSM 850 => TX is ALWAYS swapped compared to GSM 900
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 #define SWAP_IQ_GSM 1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 #define SWAP_IQ_DCS 1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 #define SWAP_IQ_PCS 1
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 #define SWAP_IQ_GSM850 3 // Swap TX compared to GSM 900
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339 #else
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 // All PG versions ABOVE 1.0 -> 0 (No Swap)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 // GSM 850 => TX is ALWAYS swapped compared to GSM 900
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 #define SWAP_IQ_GSM 0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 #define SWAP_IQ_DCS 0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 #define SWAP_IQ_PCS 0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 #define SWAP_IQ_GSM850 2 // Swap TX compared to GSM 900
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 /************************************/
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349 /************************************/
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 // typedef
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 /************************************/
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 /************************************/
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 /*************************************************************/
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 /* Define structure for apc of TX Power ******/
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 /*************************************************************/
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 typedef struct
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 { // pcm-file "rf/tx/level.gsm|dcs"
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359 UWORD16 apc; // 0..31
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363 T_TX_LEVEL;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366 /* Automatic Gain Control */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368 /* Define structure for sub-band definition of TX Power ******/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371 UWORD16 upper_bound; //highest physical arfcn of the sub-band
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 WORD16 agc_calib; // AGC for each TXPWR
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 }T_RF_AGC_BAND;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 /* Ramp definitions */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 UWORD8 ramp_up [16]; // Ramp-up profile
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 UWORD8 ramp_down [16]; // Ramp-down profile
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 T_TX_RAMP;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388 // RF structure definition
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 //========================
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 // Number of bands supported
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 #define GSM_BANDS 2
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 #define MULTI_BAND1 0
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 #define MULTI_BAND2 1
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396 // RF table sizes
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 #define AGC_TABLE_SIZE 20
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 #define MIN_AGC_INDEX 6
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 // RX parameters and tables
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 //-------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 // AGC parameters and tables
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 UWORD16 low_agc_noise_thr;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 UWORD16 high_agc_sat_thr;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 UWORD16 low_agc;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421 UWORD16 high_agc;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 UWORD8 il2agc_pwr[121];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 UWORD8 il2agc_max[121];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424 UWORD8 il2agc_av[121];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 T_AGC;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428 // Calibration parameters
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 UWORD16 g_magic;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432 UWORD16 lna_att;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 UWORD16 lna_switch_thr_low;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 UWORD16 lna_switch_thr_high;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 T_RX_CAL_PARAMS;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438 // RX temperature compensation
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 WORD16 temperature;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 WORD16 agc_calib;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444 T_RX_TEMP_COMP;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446 // RF RX structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449 T_AGC agc;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451 T_RF_RX; //common
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 // RF RX structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 T_RX_CAL_PARAMS rx_cal_params;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
457 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
460 T_RF_RX_BAND;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
463 // TX parameters and tables
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 //-------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466 // TX temperature compensation
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469 WORD16 temperature;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
470 #if (ORDER2_TX_TEMP_CAL==1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471 WORD16 a;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472 WORD16 b;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473 WORD16 c;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475 WORD16 apc_calib;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
476 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
477 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478 T_TX_TEMP_CAL;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
479
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
480 // Ramp up and ramp down delay
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
481 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
482 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
483 UWORD16 up;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
484 UWORD16 down;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
485 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
486 T_RAMP_DELAY;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
487
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
488 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
490 UWORD16 arfcn_limit;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
491 WORD16 chan_cal;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
492 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
493 T_TX_CHAN_CAL;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
495 // RF TX structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
496 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
497 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
498 T_RAMP_DELAY ramp_delay;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
499 UWORD8 guard_bits; // number of guard bits needed for ramp up
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
500 UWORD8 prg_tx;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502 T_RF_TX; //common
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
503
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
504 // RF TX structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
505 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
507 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
512 T_RF_TX_BAND;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
513
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
514 // band structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
515 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
516 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
517 T_RF_RX_BAND rx;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
518 T_RF_TX_BAND tx;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
519 UWORD8 swap_iq;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
520 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
521 T_RF_BAND;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
522
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
523 // RF structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
524 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
525 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
526 // common for all bands
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
527 UWORD16 rf_revision;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
528 UWORD16 radio_band_support;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
529 T_RF_RX rx;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
530 T_RF_TX tx;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
531 T_AFC_PARAMS afc;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
532 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
533 T_RF;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
534
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
535 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
536 /* MADC definitions */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
537 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
538 // Omega: 5 external channels if touch screen not used, 3 otherwise
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
539 enum ADC_INDEX {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
540 ADC_VBAT,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
541 ADC_VCHARG,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
542 ADC_ICHARG,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
543 ADC_VBACKUP,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
544 ADC_BATTYP,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
545 ADC_BATTEMP,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
546 ADC_ADC3, // name of this ??
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
547 ADC_RFTEMP,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
548 ADC_ADC4,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
549 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
550 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
551
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
552 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
553 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
554 WORD16 converted[ADC_INDEX_END]; // converted
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
555 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
556 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
557 T_ADC;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
558
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
559 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
560 /* MADC calibration */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
561 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
562 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
563 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
564 UWORD16 a[ADC_INDEX_END];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
565 WORD16 b[ADC_INDEX_END];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
566 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
567 T_ADCCAL;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
568
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
569 // Conversion table: ADC value -> temperature
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
570 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
571 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
572 UWORD16 adc; // ADC reading is 10 bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
573 WORD16 temp; // temp is in approx. range -30..+80
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
574 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
575 T_TEMP;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
576
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
577 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
578 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
579 char *name;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
580 void *addr;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
581 int size;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
582 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
583 T_CONFIG_FILE;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
584
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
585 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
586 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
587 char *name; // name of ffs file suffix
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
588 T_RF_BAND *addr; // address to default flash structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
589 UWORD16 max_carrier; // max carrier
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
590 UWORD16 max_txpwr; // max tx power
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
591 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
592 T_BAND_CONFIG;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
593
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
594 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
595 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
596 UWORD8 band[GSM_BANDS]; // index to band address
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
597 UWORD8 txpwr_tp; // tx power turning point
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
598 UWORD16 first_arfcn; // first index
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
599 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
600 T_STD_CONFIG;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
601 enum GSMBAND_DEF
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
602 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
603 BAND_NONE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
604 BAND_EGSM900,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
605 BAND_DCS1800,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
606 BAND_PCS1900,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
607 BAND_GSM850,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
608 // put new bands here
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
609 BAND_GSM900 //last entry
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
610 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
611
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
612 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
613 /* ABB (Omega) Initialization */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
614 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
615
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
616 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
617 #define ABB_TABLE_SIZE 16
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
618 #elif (ANLG_FAM == 3)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
619 #define ABB_TABLE_SIZE 22
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
620 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
621
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
622 // Note that this translation is probably not needed at all. But until L1 is
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
623 // (maybe) changed to simply initialize the ABB from a table of words, we
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
624 // use this to make things more easy-readable.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
625
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
626 #if (ANLG_FAM == 1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
627 enum ABB_REGISTERS {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
628 ABB_AFCCTLADD = 0,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
629 ABB_VBUCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
630 ABB_VBDCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
631 ABB_BBCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
632 ABB_APCOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
633 ABB_BULIOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
634 ABB_BULQOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
635 ABB_DAI_ON_OFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
636 ABB_AUXDAC,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
637 ABB_VBCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
638 ABB_APCDEL1
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
639 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
640 #elif (ANLG_FAM == 2)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
641 enum ABB_REGISTERS {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
642 ABB_AFCCTLADD = 0,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
643 ABB_VBUCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
644 ABB_VBDCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
645 ABB_BBCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
646 ABB_BULGCAL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
647 ABB_APCOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
648 ABB_BULIOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
649 ABB_BULQOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
650 ABB_DAI_ON_OFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
651 ABB_AUXDAC,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
652 ABB_VBCTRL1,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
653 ABB_VBCTRL2,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
654 ABB_APCDEL1,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
655 ABB_APCDEL2
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
656 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
657 #elif (ANLG_FAM == 3)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
658 enum ABB_REGISTERS {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
659 ABB_AFCCTLADD = 0,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
660 ABB_VBUCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
661 ABB_VBDCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
662 ABB_BBCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
663 ABB_BULGCAL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
664 ABB_APCOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
665 ABB_BULIOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
666 ABB_BULQOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
667 ABB_DAI_ON_OFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
668 ABB_AUXDAC,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
669 ABB_VBCTRL1,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
670 ABB_VBCTRL2,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
671 ABB_APCDEL1,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
672 ABB_APCDEL2,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
673 ABB_VBPOP,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
674 ABB_VAUDINITD,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
675 ABB_VAUDCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
676 ABB_VAUOCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
677 ABB_VAUSCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
678 ABB_VAUDPLL
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
679 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
680 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
681 #endif