FreeCalypso > hg > ffs-editor

annotate src/cs/system/main/init.c @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
parents
children c07376e250c1
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0
92470e5d0b9e src: partial import from FC Selenite
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1 /*
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2 * INIT.C
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3 *
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4 * This module allows to initialize the board:
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5 * - wait states,
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6 * - unmask selected interrupts,
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7 * - initialize clock,
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8 * - disable watchdog.
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9 * Dummy functions used by the EVA3 library are defined.
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10 */
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11
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12 /* Config Files */
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13
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14 #ifndef _WINDOWS
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15 #include "l1sw.cfg"
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16 #include "rf.cfg"
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17 #include "chipset.cfg"
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18 #include "board.cfg"
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19 #include "swconfig.cfg"
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20 #include "fc-target.h"
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21 #if (OP_L1_STANDALONE == 0)
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22 #include "rv.cfg"
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23 #include "sys.cfg"
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24 #include "debug.cfg"
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25 #ifdef BLUETOOTH_INCLUDED
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26 #include "btemobile.cfg"
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27 #endif
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28 #ifdef BLUETOOTH
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29 #include "bluetooth.cfg"
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30 #endif
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31 #endif
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32
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33 #if (OP_L1_STANDALONE == 0)
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34 #include "rv/rv_defined_swe.h"
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35 #endif
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36 #endif
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37
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38 /* Include Files */
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39 #include <assert.h>
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40 #include <ctype.h>
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41 #include <stdarg.h>
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42 #include <stdlib.h>
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43 #include <string.h>
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44
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45 #include "nucleus.h"
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46
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47 #include "sys_types.h"
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48 #include "l1_types.h"
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49 #include "l1_confg.h"
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50 #include "l1_const.h"
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51
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52 #if TESTMODE
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53 #include "l1tm_defty.h"
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54 #endif // TESTMODE
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55
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56 #if (AUDIO_TASK == 1)
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57 #include "l1audio_const.h"
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58 #include "l1audio_cust.h"
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59 #include "l1audio_defty.h"
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60 #endif // AUDIO_TASK
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61
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62 #if (L1_GTT == 1)
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63 #include "l1gtt_const.h"
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64 #include "l1gtt_defty.h"
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65 #endif
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66
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67 #if (L1_MP3 == 1)
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68 #include "l1mp3_defty.h"
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69 #endif
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70
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71 #if (L1_MIDI == 1)
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72 #include "l1midi_defty.h"
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73 #endif
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74
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75 #if (L1_AAC == 1)
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76 #include "l1aac_defty.h"
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77 #endif
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78 #if (L1_DYN_DSP_DWNLD == 1)
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79 #include "l1_dyn_dwl_defty.h"
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80 #endif
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81
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82 #if (TRACE_TYPE == 4)
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83 #include "l1_defty.h"
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84 #endif
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85
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86
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87 #if ((OP_L1_STANDALONE == 1) && (CODE_VERSION != SIMULATION) && (PSP_STANDALONE == 0))
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88
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89 #if (AUDIO_TASK == 1)
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90 #include "l1audio_signa.h"
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91 #include "l1audio_msgty.h"
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92 #endif // AUDIO_TASK
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93
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94 #if (L1_GTT == 1)
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95 #include "l1gtt_signa.h"
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96 #include "l1gtt_msgty.h"
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97 #endif
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98
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99 #include "l1_defty.h"
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100 #include "cust_os.h"
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101 #include "l1_msgty.h"
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102 #include "nu_main.h"
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103 #include "l1_varex.h"
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104 #include "l1_proto.h"
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105 #include "hw_debug.h"
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106 #include "l1_trace.h"
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107
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108 #endif /* ((OP_L1_STANDALONE == 1) && (CODE_VERSION != SIMULATION) && (PSP_STANDALONE==0)) */
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109
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110
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111 #include "armio/armio.h"
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112 #include "timer/timer.h"
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113
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114 #if (OP_L1_STANDALONE == 0)
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115 #include "rvf/rvf_api.h"
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116 #include "rvm/rvm_api.h" /* A-M-E-N-D-E-D! */
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117 #include "sim/sim.h"
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118 #endif
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119
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120 #include "abb/abb.h"
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121
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122 #include "inth/iq.h"
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123 #include "tpudrv.h"
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124 #include "memif/mem.h"
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125 #include "clkm/clkm.h"
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126 #include "inth/inth.h"
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127
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128 #if (OP_L1_STANDALONE == 1)
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129 #include "uart/serialswitch_core.h"
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130 #else
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131 #include "uart/serialswitch.h"
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132 #endif
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133 #include "uart/traceswitch.h"
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134
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135
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136 #include "dma/dma.h"
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137 #include "rhea/rhea_arm.h"
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 #include "ulpd/ulpd.h"
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 #if (PSP_STANDALONE == 0)
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parents:
diff changeset
142 #if (OP_L1_STANDALONE == 0)
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parents:
diff changeset
143 extern void ffs_main_init(void);
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 extern void create_tasks(void);
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 #if TI_NUC_MONITOR == 1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 extern void ti_nuc_monitor_tdma_action( void );
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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148
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 #if WCP_PROF == 1
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parents:
diff changeset
150 #if PRF_CALIBRATION == 1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 extern NU_HISR prf_CalibrationHISR;
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parents:
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152 #endif
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parents:
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153 #endif
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parents:
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154
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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155 #else
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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156 void l1ctl_pgm_clk32(UWORD32 nb_hf, UWORD32 nb_32khz);
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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157 extern void L1_trace_string(char *s);
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 #endif /* (OP_L1_STANDALONE) */
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parents:
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159 #endif
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parents:
diff changeset
160
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parents:
diff changeset
161 #if (OP_L1_STANDALONE == 1)
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parents:
diff changeset
162 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) || TESTMODE)
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parents:
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163 #include "uart/uart.h"
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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164 /*
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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165 * Serial Configuration set up.
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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166 */
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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167
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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168 extern char ser_cfg_info[NUMBER_OF_TR_UART];
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parents:
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169 #include "rvt_gen.h"
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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170 extern T_RVT_USER_ID trace_id;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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171 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 #endif /* (OP_L1_STANDALONE == 1) */
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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173
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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174 /*
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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175 * Serial Configuration set up.
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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176 */
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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177
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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178 /*
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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179 ** One config is:
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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180 ** {XXX_BT_HCI, // Bluetooth HCI
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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181 ** XXX_FAX_DATA, // Fax/Data AT-Cmd
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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182 ** XXX_TRACE, // L1/Riviera Trace Mux
92470e5d0b9e src: partial import from FC Selenite
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parents:
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183 ** XXX_TRACE}, // Trace PS
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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184 **
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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185 ** with XXX being DUMMY, UART_IRDA or UART_MODEM
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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186 */
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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187
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 #if ((((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) ||\
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 (TESTMODE)) && (OP_L1_STANDALONE == 1)) || (OP_L1_STANDALONE == 0))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 #if (OP_L1_STANDALONE == 1)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 static T_AppliSerialInfo appli_ser_cfg_info =
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 #else
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 T_AppliSerialInfo appli_ser_cfg_info =
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 #endif /* OP_L1_STANDALONE */
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 #ifdef CONFIG_RVTMUX_ON_MODEM
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 UART_MODEM_TRACE,
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 DUMMY_TRACE}, // 0x0248
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 #else // RVTMUX_ON_MODEM
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 UART_MODEM_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 UART_IRDA_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 DUMMY_TRACE}, // default config = 0x0168
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 #ifdef BTEMOBILE
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 12, // 12 serial config allowed
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 #else // BTEMOBILE
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 9, // 9 serial config allowed
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 {
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 // Configs with Condat Panel only
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 DUMMY_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 UART_IRDA_TRACE}, // 0x1048
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 DUMMY_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 UART_MODEM_TRACE}, // 0x2048
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 // Configs with L1/Riviera Trace only
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 UART_IRDA_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 DUMMY_TRACE}, // 0x0148
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 UART_MODEM_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 DUMMY_TRACE}, // 0x0248
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 // Configs with AT-Cmd only
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 UART_MODEM_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 DUMMY_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 DUMMY_TRACE}, // 0x0068
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 // Configs with Condat Panel and L1/Riviera Trace
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 UART_MODEM_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 UART_IRDA_TRACE}, // 0x1248
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 UART_IRDA_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 UART_MODEM_TRACE}, // 0x2148
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 // Configs with Condat Panel and AT-Cmd
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 UART_MODEM_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 DUMMY_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 UART_IRDA_TRACE}, // 0x1068
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 #ifdef BTEMOBILE
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 // Configs with L1/Riviera Trace and Bluetooth HCI
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252 {UART_IRDA_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 UART_MODEM_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 DUMMY_TRACE}, // 0x0249
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 {UART_MODEM_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 UART_IRDA_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 DUMMY_TRACE}, // 0x014A
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 // Configs with AT-Cmd and Bluetooth HCI
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 {UART_IRDA_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 UART_MODEM_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 DUMMY_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 DUMMY_TRACE}, // 0x0069
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 #endif // BTEMOBILE
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 // Configs with L1/Riviera Trace and AT-Cmd
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 UART_MODEM_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 UART_IRDA_TRACE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 DUMMY_TRACE} // 0x0168
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 #endif /* (TRACE_TYPE ...) || (OP_L1_STANDALONE == 0) */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 * Init_Target
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 *
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279 * Performs low-level HW Initialization.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 void Init_Target(void)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 #if (BOARD == 5)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 #define WS_ROM (1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 #define WS_RAM (1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 #define WS_APIF (1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 #define WS_CS2 (7) /* LCD on EVA3. */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 #define WS_CS0 (7) /* DUART on EVA3. UART16750 and latch on A-Sample. */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 #define WS_CS1 (7) /* LCD on A-Sample. */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 IQ_InitWaitState (WS_ROM, WS_RAM, WS_APIF, WS_CS2, WS_CS0, WS_CS1);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 IQ_InitClock (2); /* Internal clock division factor. */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 IQ_MaskAll (); /* Mask all interrupts. */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 IQ_SetupInterrupts (); /* IRQ priorities. */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 TM_DisableWatchdog ();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 * Reset all TSP and DBG fdefault values
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303 AI_ResetTspIO ();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 AI_ResetDbgReg ();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 AI_ResetIoConfig ();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308 * Warning! The external reset signal is connected to the Omega and the
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 * external device. If the layer 1 is used its initialization removes
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 * the external reset. If the application does not use the layer 1
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311 * you must remove the external reset (bit 2 of the reset control
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 * register 0x505808).
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 AI_ResetTspIO();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 AI_ResetDbgReg();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 AI_ResetIoConfig();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 * Configure all IOs (see RD300 specification).
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 AI_ConfigBitAsInput (1);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 AI_EnableBit (1);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 AI_ConfigBitAsOutput (2);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327 AI_EnableBit (2);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 AI_ConfigBitAsInput (11);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 AI_EnableBit (11);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 AI_ConfigBitAsOutput (13);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 AI_EnableBit (13);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 AI_Power (1); /* Maintain power supply. */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 #elif (BOARD == 6) || (BOARD == 7) || (BOARD == 8) || (BOARD == 9) || \
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45) || \
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339 (BOARD == 35) || (BOARD == 46) || (BOARD == 70) || (BOARD == 71)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 #if (PSP_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 // RIF/SPI rising edge clock for ULYSSE
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)|| (ANLG_FAM == 11))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 #if ((CHIPSET >= 3))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 #if (CHIPSET == 12)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 F_CONF_RIF_RX_RISING_EDGE;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 F_CONF_SPI_RX_RISING_EDGE;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349 #elif (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 //do the DRP init here for Locosto
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 #if (L1_DRP == 1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 // drp_power_on(); This should be done after the script is downloaded.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 #if (BOARD==35)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 #elif defined(CONFIG_TARGET_PIRELLI)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359 * Pirelli's version of this Init_Target() function
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 * in their fw sets the ASIC_CONF register to 0x6050,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 * which means PWL on the LT/PWL pin and LPG on the
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 * DSR_MODEM pin.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6050;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 #elif defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_GTM900)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 * The DSR_MODEM/LPG Calypso signal is unconnected on
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368 * Openmoko's modem, so let's mux it as LPG (output)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369 * so it doesn't float, like Foxconn seem to have done
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 * on the Pirelli.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371 *
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 * On the GTM900 module this signal is explicitly defined as LPG.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6040;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 #endif /* (BOARD == 35) */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 #endif /* ANLG(ANALOG)) */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 #if (BOARD == 40) || (BOARD == 41) || \
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 (BOARD == 42) || (BOARD == 43) || (BOARD == 45)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 // enable 8 Ohm amplifier for audio on D-sample
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 AI_ConfigBitAsOutput (1);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 AI_SetBit(1);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388 #elif (BOARD == 70) || (BOARD == 71)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 //Locosto I-sample or UPP costo board.BOARD
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 // Initialize the ARMIO bits as per the I-sample spec
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 // FIXME
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393 #endif /* (OP_L1_STANDALONE == 1) */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 #endif /* PSP_STANDALONE ==0 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396 // Watchdog
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 TM_DisableWatchdog(); /* Disable Watchdog */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 #if (CHIPSET == 12) || (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400 TM_SEC_DisableWatchdog();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 #if (CHIPSET == 12)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 #if 0 /* example of configuration for DMA debug */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 #if (BOARD == 6) /* debug on EVA 4 , GPO2 must not be changed */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 /* TPU_FRAME, NMIIT, IACKn */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 F_DBG_IRQ_CONFIG(C_DBG_IRQ_IRQ4|C_DBG_IRQ_NMIIT|C_DBG_IRQ_IACKN);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 /* NDMA_REQ_VIEW1, NDMA_REQ_VIEW0, DMA_V(1), DMA_S(1), DMAREQ_P1(3:0)*/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414 F_DBG_DMA_P1_NDFLASH_CONFIG(C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_1 |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_0 |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_3 |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_2 |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_1 |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_0 |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 C_DBG_DMA_P1_NDFLASH_DMA_REQ_S_1 |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421 C_DBG_DMA_P1_NDFLASH_DMA_REQ_V1 );
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422 /* DMA_REQ_S(2)*/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 F_DBG_DMA_P2_CONFIG(C_DBG_DMA_P2_DMA_REQ_S2);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 /* DMA_CLK_REQ, BRIDGE_CLK */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 F_DBG_CLK1_CONFIG(C_DBG_CLK1_DMA_CLK_REQ |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427 C_DBG_CLK1_BRIDGE_CLK );
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 /* XIO_nREADY */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430 F_DBG_IMIF_CONFIG(C_DBG_IMIF_XIO_NREADY_MEM);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432 /* DSP_nIRQ_VIEW1, DSP_nIRQ_VIEW0, BRIDGE_EN */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 F_DBG_KB_USIM_SHD_CONFIG(C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_1 |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_0 |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 C_DBG_KB_USIM_SHD_BRIDGE_EN );
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437 /* RHEA_nREADY , RHEA_nSTROBE */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438 F_DBG_USIM_CONFIG(C_DBG_USIM_RHEA_NSTROBE |
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439 C_DBG_USIM_RHEA_NREADY );
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 /* XIO_STROBE */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 F_DBG_MISC2_CONFIG(C_DBG_MISC2_X_IOSTRBN);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444 /* DMA_CLK_REQ */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 F_DBG_CLK2_CONFIG(C_DBG_CLK2_DMA_CLK_REQ2);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447 /* DSP_IRQ_SEL0=DMA, DSP_IRQ_SEL1=DMA, DMA_REQ_SEL0=RIF_RX, DMA_REQ_SEL1=RIF_RX */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 F_DBG_VIEW_CONFIG(0,0,C_DBG_DSP_INT_DMA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449 C_DBG_DSP_INT_DMA,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450 C_DMA_CHANNEL_RIF_RX,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451 C_DMA_CHANNEL_RIF_RX);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 #endif /* (BOARD == 6) */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 #endif /* DMA debug example */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
457 * Configure ASIC in order to output the DPLL and ARM clock
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459 // (*( volatile UWORD16* )(0xFFFEF008)) = 0x8000; // DPLL
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
460 // (*( volatile UWORD16* )(0xFFFEF00E)) = 0x0004; // ARM clock
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461 // (*( volatile UWORD16* )(0xfffef004)) = 0x0600; // DSP clock + nIACK
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462 #endif /* (CHIPSET == 12) || CHIPSET == 15*/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
463
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466 * Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 // IRQ, Timer and bridge may SLEEP
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469 // In first step, same configuration as SAMSON
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
470 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471 #if (CHIPSET == 12)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_BRIDGE_DIS | CLKM_DPLL_DIS);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473 #elif (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_CPORT_EN | CLKM_BRIDGE_DIS | 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
476 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
477 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
479 // Select VTCXO input frequency
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
480 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
481 CLKM_UNUSED_VTCXO_26MHZ;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
482
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
483 // Rita RF uses 26MHz VCXO
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
484 #if (RF_FAM == 12)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
485 CLKM_USE_VTCXO_26MHZ;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
486 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
487 // Renesas RF uses 26MHz on F-sample but 13MHz on TEB
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
488 #if (RF_FAM == 43) && (BOARD == 46)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489 CLKM_USE_VTCXO_26MHZ;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
490 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
491 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
492
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
493
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494 // Control HOM/SAM automatic switching
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
495 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
496 *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
497
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
498 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
499 * The following part has been reconstructed from disassembly.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
500 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501 RHEA_INITRHEA(0,0,0xFF);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
503 #if (CHIPSET == 8)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
504 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
505 #elif (CHIPSET == 10) || (CHIPSET == 11)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
507 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508 #error "We only have DPLL setup for CHIPSETs 8 and 10"
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
512 * FreeCalypso change: memory timings and widths are target-dependent;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
513 * please refer to the MEMIF-wait-states document in the freecalypso-docs
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
514 * repository for the full explanation.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
515 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
516 #ifdef CONFIG_TARGET_PIRELLI
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
517 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
518 * Pirelli's version of this Init_Target() function
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
519 * in their fw does the following:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
520 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
521 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
522 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
523 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
524 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
525 MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
526 #elif defined(CONFIG_TARGET_C155)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
527 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
528 * C155/156 official fw MEMIF config is almost the same as Pirelli's,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
529 * only nCS4 WS is different, but nCS4 is unused on this model...
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
530 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
531 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
532 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
533 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
534 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
535 MEM_INIT_CS4(6, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
536 #elif defined(CONFIG_TARGET_C11X) || defined(CONFIG_TARGET_C139) || \
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
537 defined(CONFIG_TARGET_GTAMODEM)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
538 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
539 * The original settings from Openmoko,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
540 * only nCS0 and nCS1 are actually used,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
541 * same as on Mot C1xx phones,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
542 * the nCS2/3/4 settings are dummies from TI.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
543 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
544 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
545 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
546 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
547 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
548 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
549 #elif defined(CONFIG_TARGET_J100)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
550 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
551 * Same as Mot C11x/12x/139/140 and Openmoko except for nCS2 WS:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
552 * it appears that SE J100 has its ringtone melody generator chip
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
553 * hooked up there.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
554 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
555 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
556 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
557 MEM_INIT_CS2(6, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
558 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
559 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
560 #elif (CHIPSET == 8)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
561 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
562 * Our only Calypso C05 target is Mother Mychaela's D-Sample board.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
563 * WS=3 with the ARM7 core running at 39 MHz gives us 92 ns,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
564 * so we should be good on this board.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
565 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
566 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
567 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
568 MEM_INIT_CS2(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
569 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
570 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
571 #elif (CHIPSET == 10) || (CHIPSET == 11)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
572 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
573 * Default for Calypso C035 targets in the absence of a more specific
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
574 * selection above. We put the WS=4 memory-oriented setting on all
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
575 * chip selects so we automatically cover targets with a second flash
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
576 * chip select no matter if it's nCS2, nCS3 or nCS4, as well as even
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
577 * weirder targets with XRAM somewhere other than nCS1.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
578 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
579 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
580 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
581 MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
582 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
583 MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
584 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
585 #error "Unknown MEMIF configuration"
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
586 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
587 MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
588 MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
589 RHEA_INITAPI(0,1);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
590 RHEA_INITARM(0,0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
591 DPLL_SET_PLL_ENABLE;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
592
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
593 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
594 * Disable and Clear all pending interrupts
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
595 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
596 #if (CHIPSET == 12) || (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
597 F_INTH_DISABLE_ALL_IT; // MASK all it
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
598 F_INTH2_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH2 IRQ
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
599 F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
600 F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
601 F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
602 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
603 INTH_DISABLEALLIT;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
604 #if 0 /* not present in our reference binary object */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
605 INTH_RESETALLIT;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
606 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
607 INTH_CLEAR; /* reset IRQ/FIQ source */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
608 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
609
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
610 // INTH
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
611 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
612 #if (CHIPSET == 12) || (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
613 #if (GSM_IDLE_RAM != 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
614 f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram); // setup configuration IT handlers
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
615 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
616 f_inth_setup((T_INTH_CONFIG *)a_inth_config); // setup configuration IT handlers
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
617 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
618 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
619 IQ_SetupInterrupts();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
620 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
621
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
622
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
623 #if (CHIPSET == 12) || (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
624 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
625
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
626 f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
627 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
628 f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
629 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
630 f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
631 f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
632 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
633
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
634 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
635 // DMA
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
636 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
637 // channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
638 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
639 DMA_ALLOCDMA(1,0,1,1); // Channel 1 used by DSP with RIF RX
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
640 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
641 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
642
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
643 /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
644
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
645 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
646
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
647 // RHEA Bridge
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
648 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
649 // ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
650 RHEA_INITRHEA(0,0,0x7F);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
651
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
652 #if (CHIPSET == 6)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
653 // WS_H = 1 , WS_L = 15
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
654 RHEA_INITAPI(1,15); // should be 0x01E1 for 65 Mhz
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
655 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
656 // WS_H = 0 , WS_L = 7
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
657 RHEA_INITAPI(0,7); // should be 0x0101 for 65 Mhz
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
658 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
659
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
660 // Write_en_0 = 0 , Write_en_1 = 0
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
661 RHEA_INITARM(0,0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
662
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
663 // INTH
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
664 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
665 INTH_DISABLEALLIT; // MASK all it
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
666 INTH_CLEAR; // reset IRQ/FIQ source
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
667 IQ_SetupInterrupts();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
668
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
669 // DMA
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
670 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
671 // channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
672 DMA_ALLOCDMA(1,0,1,1); // should be 0x25 (channel 1 = lead)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
673
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
674 #if (CHIPSET == 6)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
675 // Memory WS configuration for ULYSS/G1 (26 Mhz) board
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
676 //-----------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
677 MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
678 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
679
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
680 // CLKM
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
681 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
682 CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
683
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
684 #if (CHIPSET == 6)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
685 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS | CLKM_VTCXO_26);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
686 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
687 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
688 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
689
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
690 #endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
691
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
692 // Freeze ULPD timer ....
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
693 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
694 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_INIT_REG ) = 0;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
695 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
696
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
697 // reset INC_SIXTEEN and INC_FRAC
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
698 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
699 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
700 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
701 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
702 ULDP_INCSIXTEEN_UPDATE(132); //32768.29038 =>132, 32500 => 133
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
703 // 26000 --> 166
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
704 ULDP_INCFRAC_UPDATE(15840); //32768.29038 =>15840, 32500 => 21845
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
705 // 26000 --> 43691
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
706 #endif /* OP_L1_STANDALONE */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
707
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
708 // program ULPD WAKE-UP ....
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
709 //=================================================
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
710 #if (CHIPSET == 2)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
711 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 2 frame
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
712 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 31 periods
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
713 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
714 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
715 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
716 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
717 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
718 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
719 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
720 *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
721 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
722
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
723 // Set Gauging versus HF (PLL)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
724 //=================================================
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
725 ULDP_GAUGING_SET_HF; // Enable gauging versus HF
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
726 ULDP_GAUGING_HF_PLL; // Gauging versus PLL
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
727
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
728 // current supply for quartz oscillation
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
729 //=================================================
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
730 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
731 #if ((CHIPSET != 9) && (CHIPSET != 12) && (CHIPSET !=15)) // programming model changed for Ulysse C035, stay with default value
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
732 *(volatile SYS_UWORD16 *)QUARTZ_REG = 0x27;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
733 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
734 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
735 #if ((BOARD == 6) || (BOARD == 8) || (BOARD == 9) || (BOARD == 35) || (BOARD == 40) || (BOARD == 41))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
736 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x27;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
737 #elif (BOARD == 7)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
738 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x24;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
739 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
740 #endif /* OP_L1_STANDALONE */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
741
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
742 // stop Gauging if any (debug purpose ...)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
743 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
744 if ( *((volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG) & ULDP_GAUGING_EN)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
745 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
746 volatile UWORD32 j;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
747 ULDP_GAUGING_STOP; /* Stop the gauging */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
748 /* wait for gauging it*/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
749 // one 32khz period = 401 periods of 13Mhz
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
750 for (j=1; j<50; j++);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
751 while (! (* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
752 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
753
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
754 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
755 AI_ClockEnable ();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
756
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
757 #if (BOARD == 7)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
758 // IOs configuration of the B-Sample in order to optimize the power consumption
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
759 AI_InitIOConfig();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
760
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
761 // Set LPG instead of DSR_MODEM
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
762 *((volatile SYS_UWORD16 *) ASIC_CONF) |= 0x40;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
763 // Reset the PERM_ON bit of LCR_REG
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
764 *((volatile SYS_UWORD16 *) MEM_LPG) &= ~(0x80);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
765 #elif ((BOARD == 8) || (BOARD == 9))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
766 // IOs configuration of the C-Sample in order to optimize the power consumption
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
767 AI_InitIOConfig();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
768
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
769 // set the debug latch to 0x00.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
770 *((volatile SYS_UWORD8 *) 0x2800000) = 0x00;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
771 #elif ((BOARD == 35) || (BOARD == 46))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
772 AI_InitIOConfig();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
773 // CSMI INTERFACE
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
774 // Initialize CSMI clients for GSM control
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
775 // and Fax/Data services
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
776 CSMI_Init();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
777 GC_Initialize(); // GSM control initialization
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
778 CU_Initialize(); // Trace initialization
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
779 CF_Initialize(); // Fax/Data pre-initialization
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
780 #elif ((BOARD == 40) || (BOARD == 41))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
781 // IOs configuration of the D-Sample in order to optimize the power consumption
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
782 AI_InitIOConfig();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
783
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
784 #ifdef BTEMOBILE
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
785 // Reset BT chip by toggling the Island's nRESET_OUT signal
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
786 *((volatile SYS_UWORD16 *) 0xFFFFFD04) |= 0x04;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
787 *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
788 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
789
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
790 // set the debug latch to 0x0000.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
791 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
792 * FreeCalypso change: this write is only correct when running
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
793 * on an actual D-Sample board, but not on any of the real-world
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
794 * Calypso target devices.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
795 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
796 #ifdef CONFIG_TARGET_DSAMPLE
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
797 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
798 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
799 #endif // BOARD
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
800
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
801 // Enable HW Timers 1 & 2
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
802 TM_EnableTimer (1);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
803 TM_EnableTimer (2);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
804
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
805 #endif /* (OP_L1_STANDALONE == 0) */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
806
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
807 #endif /* #if (BOARD == 5) */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
808 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
809
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
810 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
811 * Init_Drivers
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
812 *
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
813 * Performs Drivers Initialization.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
814 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
815 void Set_Switch_ON_Cause(void);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
816 void Init_Drivers(void)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
817 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
818
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
819 #if (CHIPSET==15)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
820 bspI2c_init();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
821 bspTwl3029_init();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
822
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
823 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
824 Set_Switch_ON_Cause();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
825 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
826
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
827
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
828 /* Turn on DRP We will make VRMCC to device group Modem
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
829 * And Switch it on.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
830 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
831 bspTwl3029_Power_setDevGrp(NULL,BSP_TWL3029_POWER_VRMMC,BSP_TWL3029_POWER_DEV_GRP_MODEM);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
832 wait_ARM_cycles(convert_nanosec_to_cycles(100000*2));
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
833 bspTwl3029_Power_enable(NULL,BSP_TWL3029_POWER_VRMMC,BSP_TWL3029_POWER_STATE_ACTIVE);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
834 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
835
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
836 #if (CHIPSET!=15)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
837 #if ABB_SEMAPHORE_PROTECTION
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
838 // Create the ABB semaphore
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
839 ABB_Sem_Create();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
840 #endif // SEMAPHORE_PROTECTION
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
841 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
842
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
843 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
844 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
845 * Initialize FFS invoking restore procedure by MPU-S
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
846 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
847 #if ((BOARD == 35) || (BOARD == 46))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
848 GC_FfsRestore();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
849 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
850
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
851 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
852 * FFS main initialization.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
853 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
854
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
855 ffs_main_init();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
856
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
857
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
858 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
859 * Initialize Riviera manager and create tasks thanks to it.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
860 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
861 #if (CHIPSET!=15) || (REMU==0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
862 rvf_init();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
863 rvm_init(); /* A-M-E-M-D-E-D! */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
864 create_tasks();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
865 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
866 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
867 * SIM Main Initialization.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
868 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
869 #if (CHIPSET!=15)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
870 SIM_Initialize ();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
871 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
872 bspUicc_bootInit();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
873 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
874 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
875 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
876
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
877 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
878 * Init_Serial_Flows
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
879 *
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
880 * Performs Serialswitch + related serial data flows initialization.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
881 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
882 void Init_Serial_Flows (void)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
883 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
884 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
885
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
886 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
887 * Initialize Serial Switch module.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
888 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
889 #if ((BOARD==35) || (BOARD == 46))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
890 SER_InitSerialConfig (GC_GetSerialConfig());
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
891 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
892 SER_InitSerialConfig (&appli_ser_cfg_info);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
893 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
894 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
895 * Then Initialize the Serial Data Flows and the associated UARTs:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
896 * - G2-3 Trace if GSM/GPRS Protocol Stack
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
897 * - AT-Cmd/Fax & Data Flow
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
898 *
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
899 * Layer1/Riviera Trace Flow and Bluetooth HCI Flow are initialized
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
900 * by the appropriate SW Entities.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
901 *
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
902 * G2-3 Trace => No more Used
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
903 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
904 SER_tr_Init(SER_PROTOCOL_STACK, TR_BAUD_38400, NULL);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
905
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
906 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
907 * Fax & Data / AT-Command Interpreter Serial Data Flow Initialization
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
908 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
909
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
910 #if ((BOARD != 35) && (BOARD != 46))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
911 (void) SER_fd_Initialize ();
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
912 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
913 #else /* OP_L1_STANDALONE */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
914
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
915 #if (TESTMODE || (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==6) || (TRACE_TYPE==7))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
916 #if ((BOARD == 35) || (BOARD == 46))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
917 ser_cfg_info[UA_UART_0] = '0';
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
918 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
919 ser_cfg_info[UA_UART_0] = 'G';
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
920 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
921 #if (CHIPSET !=15)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
922 ser_cfg_info[UA_UART_1] = 'R'; // Riviear Demux on UART MODEM
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
923 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
924 ser_cfg_info[UA_UART_0] = 'R'; // Riviear Demux on UART MODEM
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
925 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
926
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
927 /* init Uart Modem */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
928 SER_InitSerialConfig (&appli_ser_cfg_info);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
929
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
930 #if TESTMODE || (TRACE_TYPE == 1) || (TRACE_TYPE == 7)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
931 SER_tr_Init (SER_LAYER_1, TR_BAUD_115200, rvt_activate_RX_HISR);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
932
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
933 rvt_register_id("OTHER",&trace_id,(RVT_CALLBACK_FUNC)NULL);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
934 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
935 SER_tr_Init (SER_LAYER_1, TR_BAUD_38400, NULL);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
936 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
937
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
938 L1_trace_string(" \n\r");
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
939
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
940 #endif /* TRACE_TYPE */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
941
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
942 #endif /* OP_L1_STANDALONE */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
943 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
944
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
945 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
946 * Init_Unmask_IT
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
947 *
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
948 * Unmask all used interrupts.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
949 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
950 void Init_Unmask_IT (void)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
951 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
952 IQ_Unmask(IQ_FRAME);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
953 IQ_Unmask(IQ_UART_IRDA_IT);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
954 IQ_Unmask(IQ_UART_IT);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
955 IQ_Unmask(IQ_ARMIO);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
956 #if (L1_DYN_DSP_DWNLD == 1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
957 IQ_Unmask(IQ_API);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
958 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
959 }