FreeCalypso > hg > ffs-editor

annotate src/cs/system/main/gcc/bootentry.S @ 17:9a8a20d45be7

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Timer2 for Nucleus RTOS ticks
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 04:54:15 +0000
parents 92470e5d0b9e
children
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0
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1 /*
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2 * This assembly module is our counterpart to TI's int.s: all boot entry
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3 * point code that needs to be at the beginning of the flash resides here.
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4 */
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5
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6 #include "asm_defs.h"
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7 #include "fc-target.h"
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8 #include "rf.cfg"
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9
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10 #if defined(FLASH) && !defined(CONFIG_TARGET_COMPAL)
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11 /*
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12 * Put something sensible in the boot ROM overlay area, just for the
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13 * heck of it, or for extra robustness.
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14 */
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15 .section bootrom.overlay,"ax",%progbits
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16 .code 32
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17 .org 0
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18 b BootROM_disabled_entry
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19 #include "vectors.S"
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20 BootROM_disabled_entry:
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21 /* copy the boot ROM switch code to IRAM and jump to it */
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22 ldr r4, =__romswitch_flash_addr
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23 ldr r5, =__romswitch_ram_addr
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24 ldr r2, =__romswitch_size
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25 1: ldr r0, [r4], #4
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26 str r0, [r5], #4
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27 subs r2, r2, #4
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28 bhi 1b
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29 ldr pc, =__romswitch_ram_addr
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30
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31 .section bootrom.switch,"ax",%progbits
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32 .code 32
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33 .org 0
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34 @ enable the Calypso boot ROM
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35 ldr r1, =0xFFFFFB10
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36 mov r2, #0x0100
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37 strh r2, [r1]
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38 @ jump to it!
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39 mov pc, #0
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40 #endif
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41
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42 .section .inttext,"ax",%progbits
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43 .code 32
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44
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45 #ifdef FLASH
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46 .org 0
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47 #ifndef CONFIG_TARGET_COMPAL
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48 /* sane targets with Calypso boot ROM enabled by the PCB wiring */
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49 /* provide the necessary magic words for the boot ROM */
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50 .word 0
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51 .word _Firmware_boot_entry
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52 #elif defined(CONFIG_TARGET_C11X) || defined(CONFIG_TARGET_C139) || \
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53 defined(CONFIG_TARGET_J100)
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54 /*
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55 * On this target we'll put a patched version of Compal's boot code in
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56 * flash sector 0 (the brickable one); the main fw images will then be
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57 * flashed starting at 0x10000, which is where our modified boot code
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58 * expects them to be. The interface between our hacked boot code and
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59 * the main fw has been made to mimic TI's TCS211 reference fw.
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60 */
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61 #include "vectors.S"
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62 .org 0x58 /* entry point at 0x10058 */
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63 b _Firmware_boot_entry
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64 #elif defined(CONFIG_TARGET_C155)
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65 /*
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66 * On this target the hand-off point between the bootloader and the main
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67 * fw image coincides with a flash erase block boundary, thus we can reuse
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68 * the original bootloader without having to reflash the brickable sector
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69 * at all. The following bits will appear at 0x20000.
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70 */
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71 .asciz "FreeCalypso firmware for C155/156 target"
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72 .org 0xE0
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73 /* C155/156 bootloader jumps here */
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74 b _Firmware_boot_entry
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75 #include "vectors.S"
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76 #else
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77 #error "Unsupported flash boot configuration"
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78 #endif
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79 #endif
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80
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81 /* definitions from TI's int.s */
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82
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83 #define IRQ_STACK_SIZE 128
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84 #define FIQ_STACK_SIZE 512
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85 #define SYSTEM_SIZE 1024
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86 #define TIMER_SIZE 1024
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87 #define TIMER_PRIORITY 2
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88
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89 @ TI's literal pool before the entry point
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90
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91 addrCS0: .word 0xfffffb00 @ CS0 address space
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92
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93 EX_MPU_CONF_REG: .word 0xFFFEF006 @ Extended MPU configuration register address
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94 EX_FLASH_VALUE: .short 0x0008 @ set bit to enable A22
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95
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96 .balign 4
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97
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98 CNTL_ARM_CLK_REG: .word 0xFFFFFD00 @ CNTL_ARM_CLK register address
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99 DPLL_CNTRL_REG: .word 0xFFFF9800 @ DPLL control register address
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100 EXTRA_CONTROL_REG: .word 0xFFFFFB10 @ Extra Control register CONF address
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101 MPU_CTL_REG: .word 0xFFFFFF08 @ MPU_CTL register address
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102
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103 CNTL_ARM_CLK_RST: .short 0x1081 @ Initialization of CNTL_ARM_CLK register
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104 @ Use DPLL, Divide by 1
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105 DPLL_CONTROL_RST: .short 0x2002 @ Configure DPLL in default state
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106 DISABLE_DU_MASK: .short 0x0800 @ Mask to Disable the DU module
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107 ENABLE_DU_MASK: .short 0xF7FF @ Mask to Enable the DU module
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108 MPU_CTL_RST: .short 0x0000 @ Reset value of MPU_CTL register - All protections disabled
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109
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110 @ FreeCalypso change, please see MEMIF-wait-states document
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111 @ in the freecalypso-docs repository for the explanation.
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112
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113 #if (RF_FAM == 12)
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114 CS0_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable
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115 CS1_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable
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116 CS2_MEM_REG: .short 0x2a2 @ 1 Dummy Cycle 16 bit 2 WS SW BP enable
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117 #else
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118 CS0_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
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119 CS1_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
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120 CS2_MEM_REG: .short 0x2a1 @ 1 Dummy Cycle 16 bit 1 WS SW BP enable
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121 #endif
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122 CS3_MEM_REG: .short 0x283 @ 1 Dummy Cycle 8 bit 3 WS SW BP enable
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123 CS4_MEM_REG: .short 0xe85 @ default reset value
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124 CS6_MEM_REG: .short 0x2c0 @ Internal RAM init : 0 WS, 32 bits, little, write enable
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125 CS7_MEM_REG: .short 0x040 @ Internal BOOT ROM init : 0 WS, 32 bits, little, write disable
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126 CTL_MEM_REG: .short 0x02a @ rhea strobe 0/1 + API access size adaptation
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127
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128 .balign 4
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129
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130 .globl _Firmware_boot_entry
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131 _Firmware_boot_entry:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 @ TI's code from int.s follows
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
134 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 @ Configure DPLL register with reset value
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 ldr r1,DPLL_CNTRL_REG @ Load address of DPLL register in R1
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 ldrh r2,DPLL_CONTROL_RST @ Load DPLL reset value in R2
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 strh r2,[r1] @ Store DPLL reset value in DPLL register
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 @ Wait that DPLL goes in BYPASS mode
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 Wait_DPLL_Bypass:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 ldr r2,[r1] @ Load DPLL register
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 and r2,r2,#1 @ Perform a mask on bit 0
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 cmp r2,#1 @ Compare DPLL lock bit
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 beq Wait_DPLL_Bypass @ Wait Bypass mode (i.e. bit[0]='0')
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 @ Configure CNTL_ARM_CLK register with reset value: DPLL is used to
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 @ generate ARM clock with division factor of 1.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 ldr r1,CNTL_ARM_CLK_REG @ Load address of CNTL_ARM_CLK register in R1
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 ldrh r2,CNTL_ARM_CLK_RST @ Load CNTL_ARM_CLK reset value in R2
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 strh r2,[r1] @ Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 @ Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161 ldr r1,EXTRA_CONTROL_REG @ Load address of Extra Control register CONF
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 ldrh r2,ENABLE_DU_MASK @ Load mask to write in Extra Control register CONF
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 ldrh r0,[r1] @ Load Extra Control register CONF in r0
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 and r0,r0,r2 @ Enable DU module
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 strh r0,[r1] @ Store configuration in Extra Control register CONF
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 @ Disable all MPU protections
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170 ldr r1,MPU_CTL_REG @ Load address of MPU_CTL register
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 ldrh r2,MPU_CTL_RST @ Load reset value of MPU_CTL register
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 strh r2,[r1] @ Store reset value of MPU_CTL register
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 @ MEMIF timing setup
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 ldr r1,addrCS0
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 ldrh r2,CS0_MEM_REG @ ROM initialization
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 strh r2,[r1] @ CS0
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 ldrh r2,CS1_MEM_REG @ RAM Initialization
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 strh r2,[r1,#2] @ CS1
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 ldrh r2,CS2_MEM_REG @ RAM Initialization
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 strh r2,[r1,#4] @ CS2
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 ldrh r2,CS3_MEM_REG @ Parallel I/O on B-Sample
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 strh r2,[r1,#6] @ CS3 (unused on EVA4?)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 ldrh r2,CS4_MEM_REG @ Latch on B-Sample
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 strh r2,[r1,#0xa] @ CS4 (unused on EVA4)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 ldrh r2,CS6_MEM_REG @ Internal SRAM initialization
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 strh r2,[r1,#0xc] @ CS6 Internal RAM
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 ldrh r2,CS7_MEM_REG @ Internal SRAM initialization
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 strh r2,[r1,#0x8] @ CS7 Internal Boot ROM
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198 ldrh r2,CTL_MEM_REG @ API-RHEA configuration
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 strh r2,[r1,#0xe]
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201 @ enable ADD22
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 ldr r1,EX_MPU_CONF_REG
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 ldrh r2,[r1]
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 ldr r0,EX_FLASH_VALUE
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206 orr r0, r0, r2
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 strh r0,[r1]
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 /* Ensure that the processor is in supervisor mode. */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 MRS a1,CPSR @ Pickup current CPSR
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 BIC a1,a1,#MODE_MASK @ Clear the mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213 ORR a1,a1,#SUP_MODE @ Set the supervisor mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 ORR a1,a1,#LOCKOUT @ Ensure IRQ and FIQ interrupts are
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215 @ locked out
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 MSR CPSR,a1 @ Setup the new CPSR
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218 /*
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 * FreeCalypso Selenite: if this is a flash build,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 * copy IRAM code and .data from flash to RAM.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223 #ifdef FLASH
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224 /* copy iram.text to where it's supposed to be */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 ldr r8, =__iramtext_flash_addr
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 ldr r9, =__iramtext_ram_addr
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 ldr r10, =__iramtext_size
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228 1: ldmia r8!, {r0-r7}
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 stmia r9!, {r0-r7}
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 subs r10, r10, #0x20
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
231 bhi 1b
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
232 /* likewise copy .data from flash to XRAM */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
233 ldr r8, =__initdata_flash_addr
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 ldr r9, =__initdata_ram_addr
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 ldr r10, =__initdata_size
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 1: ldmia r8!, {r0-r7}
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 stmia r9!, {r0-r7}
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 subs r10, r10, #0x20
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 bhi 1b
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
241
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 /* Both flash and XRAM builds: zero .bss */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 ldr r0, =__intbss_start
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 ldr r1, =__intbss_size
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
246 bl bzero
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
247 ldr r0, =__extbss_start
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
248 ldr r1, =__extbss_size
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 bl bzero
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 @ TI's int.s code continues
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 @ Initialize the system stack pointers. This is done after the BSS is
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
255 @ cleared because the TCD_System_Stack pointer is a BSS variable! It is
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 @ assumed that the .cmd file is written to direct where these stacks should
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257 @ be allocated and to align them on double word boundaries.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 LDR a1,StackSegment @ Pickup the begining address from .cmd file
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260 @ (is aligned on 8 byte boundary)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 MOV a2,#SYSTEM_SIZE @ Pickup system stack size
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 SUB a2,a2,#4 @ Subtract one word for first addr
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 ADD a3,a1,a2 @ Build start of system stack area
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 MOV v7,a1 @ Setup initial stack limit
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 LDR a4,System_Limit @ Pickup system stack limit address
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 STR v7,[a4, #0] @ Save stack limit
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 MOV sp,a3 @ Setup initial stack pointer
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 LDR a4,System_Stack @ Pickup system stack address
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 STR sp,[a4, #0] @ Save stack pointer
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 MOV a2,#IRQ_STACK_SIZE @ Pickup IRQ stack size in bytes
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 ADD a3,a3,a2 @ Allocate IRQ stack area
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 MRS a1,CPSR @ Pickup current CPSR
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273 BIC a1,a1,#MODE_MASK @ Clear the mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274 ORR a1,a1,#IRQ_MODE @ Set the IRQ mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 MSR CPSR,a1 @ Move to IRQ mode
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 MOV sp,a3 @ Setup IRQ stack pointer
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 MOV a2,#FIQ_STACK_SIZE @ Pickup FIQ stack size in bytes
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 ADD a3,a3,a2 @ Allocate FIQ stack area
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279 MRS a1,CPSR @ Pickup current CPSR
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280 BIC a1,a1,#MODE_MASK @ Clear the mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 ORR a1,a1,#FIQ_MODE @ Set the FIQ mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 MSR CPSR,a1 @ Move to the FIQ mode
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283 MOV sp,a3 @ Setup FIQ stack pointer
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 MRS a1,CPSR @ Pickup current CPSR
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 BIC a1,a1,#MODE_MASK @ Clear the mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 ORR a1,a1,#ABORT_MODE @ Set the Abort mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 MSR CPSR,a1 @ Move to the Abort mode
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 LDR sp,Exception_Stack @ Setup Abort stack pointer
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291 MRS a1,CPSR @ Pickup current CPSR
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 BIC a1,a1,#MODE_MASK @ Clear the mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 ORR a1,a1,#UNDEF_MODE @ Set the Undefined mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 MSR CPSR,a1 @ Move to the Undefined mode
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 LDR sp,Exception_Stack @ Setup Undefined stack pointer
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 @ (should never be used)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298 @ go to Supervisor Mode
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 MRS a1,CPSR @ Pickup current CPSR
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 BIC a1,a1,#MODE_MASK @ Clear mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 ORR a1,a1,#SUP_MODE @ Set the supervisor mode bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 MSR CPSR,a1 @ All interrupt stacks are setup,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303 @ return to supervisor mode
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 @ /* Define the global data structures that need to be initialized by this
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 @ routine. These structures are used to define the system timer
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307 @ management HISR. */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308 @ TMD_HISR_Stack_Ptr = (VOID *) a3;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 @ TMD_HISR_Stack_Size = TIMER_SIZE;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 @ TMD_HISR_Priority = TIMER_PRIORITY;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 @ TMD_HISR_Stack_Ptr points at the top (the lowest address) of the allocated
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 @ area. The Timer HISR (called "SYSTEM H") and its related stack will be created
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 @ in TMI_Initialize(). The current stack pointer will be set at the bottom (the
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 @ lowest address) of the expected area.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 LDR a4,HISR_Stack_Ptr @ Pickup variable's address
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 ADD a3,a3,#4 @ Increment to next available word
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 STR a3,[a4, #0] @ Setup timer HISR stack pointer
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 MOV a2,#TIMER_SIZE @ Pickup the timer HISR stack size
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 BIC a2,a2,#3 @ Insure word alignment
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 ADD a3,a3,a2 @ Allocate the timer HISR stack
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 @ from available memory
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 LDR a4,HISR_Stack_Size @ Pickup variable's address
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325 STR a2,[a4, #0] @ Setup timer HISR stack size
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 MOV a2,#TIMER_PRIORITY @ Pickup timer HISR priority (0-2)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327 LDR a4,HISR_Priority @ Pickup variable's address
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 STR a2,[a4, #0] @ Setup timer HISR priority
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 /* TI's original code called f_load_int_mem() at this point */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 /* let's do our internal ROM enable step here */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333 ldr r1, EXTRA_CONTROL_REG
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 ldrh r0, [r1, #0]
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 bic r0, #0x0300
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 orr r0, #0x0100
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 strh r0, [r1, #0]
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339 @ We now fill up the System, IRQ, FIQ and System Timer HISR stacks with 0xFE for
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340 @ checking the status of the stacks later.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 @ inputs:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 @ a3 still has the bottom of all four stacks and is aligned.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 @ algorithm:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 @ We start from the top of all four stacks (*System_Limit), which is
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 @ necessarily aligned. We store 0xFEFEFEFE until we have filled the
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 @ bottom of the fourth stack
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 @ outputs:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 @ memory has 0xFE on all four stacks: System, FIQ, IRQ and System Timer HISR
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349 @ a3 still has the bottom of all four stacks
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 LDR a2,System_Limit @ pickup system stack limit address
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 LDR a1,[a2] @ a1 = StackSegment
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 LDR a4,=0xFEFEFEFE
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 fill_stack:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 STR a4,[a1],#4 @ store a word and increment by four
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 CMP a1,a3 @ is this the last address?
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 BLT fill_stack @ if not, loop back
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 @ /* Call INC_Initialize with a pointer to the first available memory
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 @ address after the compiler's global data. This memory may be used
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363 @ by the application. */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364 @ INC_Initialize(first_available_memory);
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 @
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366 MOV a1,a3 @ Pass the first available memory
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 B INC_Initialize @ to high-level initialization
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369 @ literal pool from int.s (after the code)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371 StackSegment:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 .word _Stack_segment_start
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 System_Limit:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 .word TCT_System_Limit
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 System_Stack:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 .word TCD_System_Stack
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380 HISR_Stack_Ptr:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 .word TMD_HISR_Stack_Ptr
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 HISR_Stack_Size:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 .word TMD_HISR_Stack_Size
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 HISR_Priority:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 .word TMD_HISR_Priority
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 Exception_Stack:
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 .word _Except_Stack_SP