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annotate src/cs/layer1/cust0/l1_rf2.h @ 27:cb3f6fe694e1 default tip

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README: document SE K2x0 addition
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 21 Dec 2023 21:44:43 +0000
parents 92470e5d0b9e
children
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 *
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4 * Filename l1_rf2.h
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5 * Copyright 2003 (C) Texas Instruments
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6 *
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7 ************* Revision Controle System Header *************/
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8
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9 #ifndef __L1_RF_H__
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10 #define __L1_RF_H__
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11
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12 /************************************/
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13 /************************************/
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14 // # define
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15 /************************************/
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16 /************************************/
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17 /* SYNTHESIZER setup time... */
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18 /************************************/
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19
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20 #define RX_SYNTH_SETUP_TIME 215L // Synthesizer setup time in quarter bit.
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21 #define TX_SYNTH_SETUP_TIME 270L // Synthesizer setup time in quarter bit.
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22
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23 /************************************/
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24 /* time for TPU scenario ending... */
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25 /************************************/
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26
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27 #define RX_TPU_SCENARIO_ENDING (4-3) // execution time of BDLENA down
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28 // minus serialization time
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29 #define TX_TPU_SCENARIO_ENDING (4-3) // execution time of BULON down
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30 // minus serialization time
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31
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32 /************************************/
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33 /* TXPWR configuration... */
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34 /************************************/
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35
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36 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
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37 #define FIXED_TXPWR ((0x1FF << 6) | AUXAPC | FALSE) // TXPWR=15
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38 // #define FIXED_TXPWR ((0xFF << 6) | AUXAPC | FALSE)
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39 #endif
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40
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41 /************************************/
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42 /* TX Propagation delay... */
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43 /************************************/
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44
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45 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
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46 // #define PRG_TX ( 52L )
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47 #define PRG_TX ( 8L)
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48 #endif
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49
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50 /************************************/
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51 /*(ANALOG)delay (in qbits) */
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52 /************************************/
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53
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54 #define UL_ABB_DELAY 0 // modulator input to output delay
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55
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56 /************************************/
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57 /* Initial value for AFC... */
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58 /************************************/
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59
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60 #define EEPROM_AFC ((-952-2400)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
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61
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62 #define SETUP_AFC_AND_RF 2 // time to have a stable output of the AFC and RF Band Gap(in Frames)
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63 // !! minimum Value : 1 Frame due to the fact there is no
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64 // hisr() in the first wake-up frame !!!!
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65
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66 #if (ANLG_FAM == 1)
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67 /************************************/
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68 /* Omega power on... */
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69 /************************************/
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70 // Omega registers values will be programmed at 1st DSP communication interrupt
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71 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
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72 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
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73 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Uplink gain amp 3 dB, Sidetone gain to -17 dB
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74 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // Downlink gain amp 0dB, Volume control -12 dB
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75 #define C_BBCTRL ((0x000 << 6) | BBCTRL | TRUE ) // value at reset
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76 #define C_APCOFF ((0x000 << 6) | APCOFF | TRUE )
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77 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
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78 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
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79 #define C_DAI_ON_OFF 0x0000 // value at reset
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80 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
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81 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE ) // VULSWITCH=0, VDLAUX=1, VDLEAR=1
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82
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83 // BULRUDEL will be initialized on rach only ....
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84 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | FALSE)
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85 #endif
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86
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87 #if (ANLG_FAM == 2)
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88 /************************************/
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89 /* Iota power on... */
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90 /************************************/
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91 // Iota registers values will be programmed at 1st DSP communication interrupt
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92 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
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93 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
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94 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Uplink gain amp 3 dB, Sidetone gain to -17 dB
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95 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // Downlink gain amp 0dB, Volume control -12 dB
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96 #define C_BBCTRL ((0x000 << 6) | BBCTRL | TRUE ) // value at reset
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97 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
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98 #define C_APCOFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
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99 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
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100 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
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101 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
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102 #define C_DAI_ON_OFF 0x0000 // value at reset
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103 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
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104 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE ) // MICBIASEL=0, VDLHSO=0, MICAUX=0
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105
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106 // BULRUDEL will be initialized on rach only ....
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107 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | TRUE )
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108 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE )
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109 #endif
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110
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111 #if (ANLG_FAM == 3)
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112 // SYREN registers values will be programmed at 1st DSP communication interrupt
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113 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
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114 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
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115 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
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116 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
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117 #define C_BBCTRL ((0x000 << 6) | BBCTRL | TRUE ) // Internal autocalibration, Output common mode=1.35V
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118 // Monoslot, Vpp=8/15*Vref
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119 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
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120 #define C_APCOFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
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121 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
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122 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
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123 #define C_DAI_ON_OFF 0x0000 // value at reset
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124 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
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125 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1 AUXI 28,2 dB
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126 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE ) // HSMIC on, SPKG gain @ 2,5dB
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127
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diff changeset
128 // BULRUDEL will be initialized on rach only ....
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129 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | TRUE )
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130 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE )
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131
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132 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE ) // HSOAUTO enabled only
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133 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
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134 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE ) // Init to zero
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135 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE ) // Speech on all outputs
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136 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE ) // Init to zero
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137 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE ) // Init to zero
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138
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139 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
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140
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141 #define C_BBCFG 0x44 // Syren Like BDLF Filter - DC OFFSET removal OFF
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142
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143 #endif
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144
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145 /************************************/
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parents:
diff changeset
146 /* Automatic frequency compensation */
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parents:
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147 /************************************/
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148
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parents:
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149 /********************* C_Psi_sta definition *****************************/
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parents:
diff changeset
150 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
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151 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
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152 /* regarding Vega V/N = 2.4/4096 */
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153 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
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parents:
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154 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
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parents:
diff changeset
155 /* = 0.000195748 */
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parents:
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156 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
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parents:
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157 /************************************************************************/
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158
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159 #define C_Psi_sta_inv 9307L // (1/C_Psi_sta)
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parents:
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160 #define C_Psi_st 6 // C_Psi_sta * 0.8 F0.16
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parents:
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161 #define C_Psi_st_32 369173L // F0.32
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parents:
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162 #define C_Psi_st_inv 11634L // (1/C_Psi_st)
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163
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164 typedef struct
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165 {
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166 WORD16 eeprom_afc;
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parents:
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167 UWORD32 psi_sta_inv;
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parents:
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168 UWORD32 psi_st;
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parents:
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169 UWORD32 psi_st_32;
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170 UWORD32 psi_st_inv;
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171 }
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172 T_AFC_PARAMS;
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173
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174 /************************************/
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parents:
diff changeset
175 /* Swap IQ definitions... */
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176 /************************************/
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parents:
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177 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
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178
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179 #define SWAP_IQ_GSM 0
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180 #define SWAP_IQ_DCS 0
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parents:
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181 #define SWAP_IQ_PCS 0 // not supported by rf2
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parents:
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182 #define SWAP_IQ_GSM850 0 // not supported by rf2
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183
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184 /************************************/
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parents:
diff changeset
185 /************************************/
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parents:
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186 // typedef
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187 /************************************/
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parents:
diff changeset
188 /************************************/
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189
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190 /*************************************************************/
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parents:
diff changeset
191 /* Define structure for apc of TX Power ******/
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parents:
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192 /*************************************************************/
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193 typedef struct
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194 { // pcm-file "rf/tx/level.gsm|dcs"
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195 UWORD16 apc; // 0..31
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196 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
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parents:
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197 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
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198 }
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199 T_TX_LEVEL;
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200
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201 /************************************/
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parents:
diff changeset
202 /* Automatic Gain Control */
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203 /************************************/
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parents:
diff changeset
204 /* Define structure for sub-band definition of TX Power ******/
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parents:
diff changeset
205 typedef struct
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parents:
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206 {
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parents:
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207 UWORD16 upper_bound; // highest physical arfcn of the sub-band
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parents:
diff changeset
208 WORD16 agc_calib; // AGC for each TXPWR
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parents:
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209 }T_RF_AGC_BAND;
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210
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211 /************************************/
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parents:
diff changeset
212 /* Ramp definitions */
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213 /************************************/
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214
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215 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
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parents:
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216 typedef struct
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parents:
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217 {
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218 UWORD8 ramp_up [16]; // Ramp-up profile
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parents:
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219 UWORD8 ramp_down [16]; // Ramp-down profile
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parents:
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220 }
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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221 T_TX_RAMP;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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222 #endif
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223
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224
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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225 // RF structure definition
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Mychaela Falconia <falcon@freecalypso.org>
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226 //========================
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227
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parents:
diff changeset
228 enum RfRevision {
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229 RF_IGNORE = 0x0000,
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230 RF_SL2 = 0x1000,
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parents:
diff changeset
231 RF_GAIA_20X = 0x2000,
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parents:
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232 RF_GAIA_20A = 0x2001,
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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233 RF_GAIA_20B = 0x2002,
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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234 RF_ATLAS_20B = 0x2020,
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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235 RF_PASCAL_20 = 0x2030
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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236 };
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parents:
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237
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238 // Number of bands supported
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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239 #define GSM_BANDS 2
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240
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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241 #define MULTI_BAND1 0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 #define MULTI_BAND2 1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243 // RF table sizes
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parents:
diff changeset
244 #define RF_RX_CAL_CHAN_SIZE 9 // number of AGC sub-bands
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parents:
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245 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
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246
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parents:
diff changeset
247 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
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parents:
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248 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
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parents:
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249 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
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parents:
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250 #define RF_TX_RAMP_SIZE 15 // number of ramp definitions
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parents:
diff changeset
251 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
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parents:
diff changeset
252
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parents:
diff changeset
253 #define AGC_TABLE_SIZE 1
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parents:
diff changeset
254
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parents:
diff changeset
255 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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256
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 // RX parameters and tables
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 //-------------------------
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
260
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
261 // AGC parameters and tables
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
262 typedef struct
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
263 {
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 UWORD16 low_agc_noise_thr;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 UWORD16 high_agc_sat_thr;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 UWORD16 low_agc;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
267 UWORD16 high_agc;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
268 UWORD8 il2agc_pwr[121];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
269 UWORD8 il2agc_max[121];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
270 UWORD8 il2agc_av[121];
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
271 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
272 T_AGC;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
273
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
274 // Calibration parameters
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
275 typedef struct
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
276 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
277 UWORD16 g_magic;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
278 UWORD16 lna_att;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
279 UWORD16 lna_switch_thr_low;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
280 UWORD16 lna_switch_thr_high;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
281 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
282 T_RX_CAL_PARAMS;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
283
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
284 // RX temperature compensation
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
285 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
286 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
287 WORD16 temperature;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
288 WORD16 agc_calib;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
289 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
290 T_RX_TEMP_COMP;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
291
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
292 // RF RX structure
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
293 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
294 {
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
295 T_AGC agc;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
296 }
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
297 T_RF_RX; //common
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
298
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
299 // RF RX structure
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
300 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
301 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
302 T_RX_CAL_PARAMS rx_cal_params;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
303 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
304 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
305 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
306 T_RF_RX_BAND;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
307
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
308
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
309 // TX parameters and tables
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
310 //-------------------------
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
311
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
312 // TX temperature compensation
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
313 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
314 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
315 WORD16 temperature;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
316 #if (ORDER2_TX_TEMP_CAL==1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
317 WORD16 a;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
318 WORD16 b;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
319 WORD16 c;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
320 #else
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
321 WORD16 apc_calib;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
322 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
323 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
324 T_TX_TEMP_CAL;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
325
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
326 // Ramp up and ramp down delay
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
327 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
328 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
329 UWORD16 up;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
330 UWORD16 down;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
331 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
332 T_RAMP_DELAY;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
333
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
334 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
335 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
336 UWORD16 arfcn_limit;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
337 WORD16 chan_cal;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
338 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
339 T_TX_CHAN_CAL;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
340
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
341 // RF TX structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
342 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
343 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
344 T_RAMP_DELAY ramp_delay;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
345 UWORD8 guard_bits; // number of guard bits needed for ramp up
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
346 UWORD8 prg_tx;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
347 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
348 T_RF_TX; //common
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
349
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
350 // RF TX structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
351 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
352 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
353 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
354 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
355 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
356 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
357 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
358 T_RF_TX_BAND;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
359
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
360 // band structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
361 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
362 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
363 T_RF_RX_BAND rx;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
364 T_RF_TX_BAND tx;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
365 UWORD8 swap_iq;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
366 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
367 T_RF_BAND;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
368
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
369 // RF structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
370 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
371 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
372 // common for all bands
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
373 UWORD16 rf_revision;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
374 UWORD16 radio_band_support;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
375 T_RF_RX rx;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
376 T_RF_TX tx;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
377 T_AFC_PARAMS afc;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
378 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
379 T_RF;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
380
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
381 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
382 /* MADC definitions */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
383 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
384 // Omega: 5 external channels if touch screen not used, 3 otherwise
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
385 enum ADC_INDEX {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
386 ADC_VBAT,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
387 ADC_VCHARG,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
388 ADC_ICHARG,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
389 ADC_VBACKUP,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
390 ADC_BATTYP,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
391 ADC_BATTEMP,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
392 ADC_RFTEMP,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
393 ADC_ADC3,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
394 ADC_ADC4,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
395 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
396 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
397
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
398 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
399 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
400 WORD16 converted[ADC_INDEX_END]; // converted
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
401 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
402 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
403 T_ADC;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
404
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
405 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
406 /* MADC calibration */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
407 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
408 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
409 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
410 UWORD16 a[ADC_INDEX_END];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
411 WORD16 b[ADC_INDEX_END];
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
412 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
413 T_ADCCAL;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
414
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
415 // Conversion table: ADC value -> temperature
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
416 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
417 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
418 UWORD16 adc; // ADC reading is 10 bits
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
419 WORD16 temp; // temp is in approx. range -30..+80
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
420 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
421 T_TEMP;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
422
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
423 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
424 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
425 char *name;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
426 void *addr;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
427 int size;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
428 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
429 T_CONFIG_FILE;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
430
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
431 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
432 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
433 char *name; // name of ffs file suffix
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
434 T_RF_BAND *addr; // address to default flash structure
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
435 UWORD16 max_carrier; // max carrier
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
436 UWORD16 max_txpwr; // max tx power
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
437 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
438 T_BAND_CONFIG;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
439
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
440 typedef struct
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
441 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
442 UWORD8 band[GSM_BANDS]; // index to band address
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
443 UWORD8 txpwr_tp; // tx power turning point
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
444 UWORD16 first_arfcn; // first index
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
445 }
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
446 T_STD_CONFIG;
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
447
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
448 enum GSMBAND_DEF
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
449 {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
450 BAND_NONE,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
451 BAND_EGSM900,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
452 BAND_DCS1800,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
453 BAND_PCS1900,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
454 BAND_GSM850,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
455 // put new bands here
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
456 BAND_GSM900 //last entry
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
457 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
458
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
459
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
460 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
461 /* ABB (Omega) Initialization */
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
462 /************************************/
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
463 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
464 #define ABB_TABLE_SIZE 16
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
465 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
466
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
467 #if (ANLG_FAM == 3)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
468 #define ABB_TABLE_SIZE 22
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
469 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
470
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
471 // Note that this translation is probably not needed at all. But until L1 is
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
472 // (maybe) changed to simply initialize the ABB from a table of words, we
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
473 // use this to make things more easy-readable.
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
474 #if (ANLG_FAM == 1)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
475 enum ABB_REGISTERS {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
476 ABB_AFCCTLADD = 0,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
477 ABB_VBUCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
478 ABB_VBDCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
479 ABB_BBCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
480 ABB_APCOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
481 ABB_BULIOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
482 ABB_BULQOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
483 ABB_DAI_ON_OFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
484 ABB_AUXDAC,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
485 ABB_VBCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
486 ABB_APCDEL1
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
487 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
488 #elif (ANLG_FAM == 2)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
489 enum ABB_REGISTERS {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
490 ABB_AFCCTLADD = 0,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
491 ABB_VBUCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
492 ABB_VBDCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
493 ABB_BBCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
494 ABB_BULGCAL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
495 ABB_APCOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
496 ABB_BULIOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
497 ABB_BULQOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
498 ABB_DAI_ON_OFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
499 ABB_AUXDAC,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
500 ABB_VBCTRL1,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
501 ABB_VBCTRL2,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
502 ABB_APCDEL1,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
503 ABB_APCDEL2
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
504 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
505 #elif (ANLG_FAM == 3)
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
506 enum ABB_REGISTERS {
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
507 ABB_AFCCTLADD = 0,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
508 ABB_VBUCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
509 ABB_VBDCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
510 ABB_BBCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
511 ABB_BULGCAL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
512 ABB_APCOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
513 ABB_BULIOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
514 ABB_BULQOFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
515 ABB_DAI_ON_OFF,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
516 ABB_AUXDAC,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
517 ABB_VBCTRL1,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
518 ABB_VBCTRL2,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
519 ABB_APCDEL1,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
520 ABB_APCDEL2,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
521 ABB_VBPOP,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
522 ABB_VAUDINITD,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
523 ABB_VAUDCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
524 ABB_VAUOCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
525 ABB_VAUSCTRL,
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
526 ABB_VAUDPLL
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
527 };
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
528 #endif
92470e5d0b9e src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
529 #endif