ffs-editor: src/cs/layer1/cust0/l1

annotate src/cs/layer1/cust0/l1_rf8.h @ 27:cb3f6fe694e1 default tip

README: document SE K2x0 addition

author	Mychaela Falconia <falcon@freecalypso.org>
date	Thu, 21 Dec 2023 21:44:43 +0000
parents	92470e5d0b9e
children

rev	line source
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /*********** Revision Controle System Header ***********
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 * GSM Layer 1 software
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 * Filename l1_rf8.h
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * Copyright 2003 (C) Texas Instruments
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 *********** Revision Controle System Header ***********/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9 #ifndef __L1_RF_H__
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 #define __L1_RF_H__
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 /* SYNTHESIZER setup time... */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1) //RX Synthesizer setup time in qbit.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21 /* time for TPU scenario ending... */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 #define RX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 // execution time of BDLENA down
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 // minus serialization time
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26 #define TX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 // execution time of BULON down
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 // minus serialization time
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 /******************************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 /* TXPWR configuration... */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 /* Fixed TXPWR value when GSM management is disabled. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 /******************************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34 #if ((ANLG_FAM == 1) \|\| (ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 // #define FIXED_TXPWR ((0xFC << 6) \| AUXAPC \| FALSE) // TXPWR=10, value=252
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 // #define FIXED_TXPWR ((0x28 << 6) \| AUXAPC \| FALSE)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37 #define FIXED_TXPWR ((0x68 << 6) \| AUXAPC \| FALSE) // TXPWR=15
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 /(ANALOG)delay (in qbits) /
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 #if (ANLG_FAM == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 #define UL_ABB_DELAY 0 // modulator input to output delay, theoretical value is 6, needs to be checked
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #if ((ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #define UL_ABB_DELAY 3 // modulator input to output delay
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 /* TX Propagation delay... */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #if ((ANLG_FAM == 1) \|\| (ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 /* Initial value for APC DELAY */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 #if (ANLG_FAM == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 #define APCDEL_DOWN 2 // minimum value: 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 #define APCDEL_UP (6+5) // minimum value: 6
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 #if (ANLG_FAM == 2) \|\| (ANLG_FAM == 3)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 #define APCDEL_DOWN (2+0) // minimum value: 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78 #define APCDEL_UP (6+2) // minimum value: 6
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 #define GUARD_BITS 7
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84 /* Initial value for AFC... */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 #define EEPROM_AFC ((-1180)8) // F13.3 required!!!!! (default : -9528, initial deviation of -2400 forced)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #define SETUP_AFC_AND_RF 2 // time to have a stable output of the AFC and RF BAND GAP(in Frames)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90 // !! minimum Value : 1 Frame due to the fact there is no
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 // hisr() in the first wake-up frame !!!!
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94 /* Baseband registers */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97 #if (ANLG_FAM == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98 // Omega registers values will be programmed at 1st DSP communication interrupt
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 #define C_DEBUG1 (0x0000 \| FALSE) // Enable f_tx delay of 400000 cyc DEBUG
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 #define C_AFCCTLADD ((0x000 << 6) \| AFCCTLADD \| TRUE ) // Value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 #define C_VBUCTRL ((0x0C9 << 6) \| VBUCTRL \| TRUE ) // Side tone -17 dB, PGA_UL 3 dB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102 #define C_VBDCTRL ((0x006 << 6) \| VBDCTRL \| TRUE ) // PGA_DL 0dB, Volume -12 dB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103 #define C_APCOFF ((0x040 << 6) \| APCOFF \| TRUE)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 #define C_BULIOFF ((0x0FF << 6) \| BULIOFF \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105 #define C_BULQOFF ((0x0FF << 6) \| BULQOFF \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 #define C_DAI_ON_OFF ((0x000 << 6) \| APCOFF \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107 #define C_AUXDAC ((0x000 << 6) \| AUXDAC \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108 #define C_VBCTRL ((0x00B << 6) \| VBCTRL \| TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 // BULRUDEL will be initialized on rach only ....
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) \| ((APCDEL_UP-6) << 6) \| APCDEL1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112 #define C_BBCTRL ((0x181 << 6) \| BBCTRL \| TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 #if (ANLG_FAM == 2)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 // IOTA registers values will be programmed at 1st DSP communication interrupt
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 #define C_DEBUG1 (0x0000 \| TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 #define C_AFCCTLADD ((0x000 << 6) \| AFCCTLADD \| TRUE ) // Value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119 #define C_VBUCTRL ((0x0C9 << 6) \| VBUCTRL \| TRUE ) // Side tone -17 dB, PGA_UL 3 dB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120 #define C_VBDCTRL ((0x006 << 6) \| VBDCTRL \| TRUE ) // PGA_DL 0dB, Volume -12 dB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121 #define C_APCOFF ((0x040 << 6) \| APCOFF \| TRUE)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 #define C_BULIOFF ((0x0FF << 6) \| BULIOFF \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 #define C_BULQOFF ((0x0FF << 6) \| BULQOFF \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124 #define C_DAI_ON_OFF ((0x000 << 6) \| APCOFF \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 #define C_AUXDAC ((0x000 << 6) \| AUXDAC \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 #define C_VBCTRL1 ((0x00B << 6) \| VBCTRL1 \| TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127 #define C_VBCTRL2 ((0x000 << 6) \| VBCTRL2 \| TRUE ) // MICBIASEL=0, VDLHSO=0, MICAUX=0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 // BULRUDEL will be initialized on rach only ....
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) \| ((APCDEL_UP-6) << 6) \| APCDEL1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131 #define C_APCDEL2 ((0x000 << 6) \| APCDEL2 \| TRUE ) //
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133 #define C_BBCTRL ((0x0C1 << 6) \| BBCTRL \| TRUE ) // Internal autocalibration, Output common mode=1.35V
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134 // Monoslot, Vpp=8/15*Vref
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135 #define C_BULGCAL ((0x000 << 6) \| BULGCAL \| TRUE ) // IAG=0 dB, QAG=0 dB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 #if (ANLG_FAM == 3)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 // SYREN registers values will be programmed at 1st DSP communication interrupt
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 #define C_DEBUG1 (0x0000 \| TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141 #define C_AFCCTLADD ((0x000 << 6) \| AFCCTLADD \| TRUE ) // Value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 #define C_VBUCTRL ((0x0C9 << 6) \| VBUCTRL \| TRUE ) // Side tone - 17 dB, PGA_UL 3dB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 #define C_VBDCTRL ((0x006 << 6) \| VBDCTRL \| TRUE ) // PGA_DL 0dB, Volume -12 dB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 #define C_APCOFF ((0x07C << 6) \| APCOFF \| TRUE)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145 #define C_BULIOFF ((0x0FF << 6) \| BULIOFF \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146 #define C_BULQOFF ((0x0FF << 6) \| BULQOFF \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147 #define C_DAI_ON_OFF ((0x000 << 6) \| APCOFF \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 #define C_AUXDAC ((0x000 << 6) \| AUXDAC \| TRUE ) // value at reset
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149 #define C_VBCTRL1 ((0x108 << 6) \| VBCTRL1 \| TRUE ) // VULSWITCH=1 AUXI 28,2 dB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 #define C_VBCTRL2 ((0x001 << 6) \| VBCTRL2 \| TRUE ) // HSMIC on, SPKG gain @ 2,5dB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152 // BULRUDEL will be initialized on rach only ....
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) \| ((APCDEL_UP-6)<<6) \| APCDEL1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 #define C_APCDEL2 ((0x000 << 6) \| APCDEL2 \| TRUE )
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155 #define C_BBCTRL ((0x0C1 << 6) \| BBCTRL \| TRUE ) // Internal autocalibration, Output common mode=1.35V
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156 // Monoslot, Vpp=8/15*Vref
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 #define C_BULGCAL ((0x000 << 6) \| BULGCAL \| TRUE ) // IAG=0 dB, QAG=0 dB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159 #define C_VBPOP ((0x004 << 6) \| VBPOP \| TRUE ) // HSOAUTO enabled only
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161 #define C_VAUDCTRL ((0x000 << 6) \| VAUDCTRL \| TRUE ) // Init to zero
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162 #define C_VAUOCTRL ((0x155 << 6) \| VAUOCTRL \| TRUE ) // Speech on all outputs
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 #define C_VAUSCTRL ((0x000 << 6) \| VAUSCTRL \| TRUE ) // Init to zero
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 #define C_VAUDPLL ((0x000 << 6) \| VAUDPLL \| TRUE ) // Init to zero
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 #define C_BBCFG 0x44 // Syren Like BDLF Filter - DC OFFSET removal OFF
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174 /* Automatic frequency compensation */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176 /******************* C_Psi_sta definition ***************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177 /* C_Psi_sta = (2piFr) / (N * Fb) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 /* (1) = (2piVppm0.9) / (NVFb) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 /* regarding Vega V/N = 2.4/4096 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 /* (1) = (2pi2.4160.9) / (40961270.83) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 /* = 0.000195748 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184 /************************************************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 #define C_Psi_sta_inv 11677L // (1/C_Psi_sta)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 #define C_Psi_st 4L // C_Psi_sta * 0.8 F0.16
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 #define C_Psi_st_32 294257L // F0.32
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 #define C_Psi_st_inv 14596L // (1/C_Psi_st)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 WORD16 eeprom_afc;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 UWORD32 psi_sta_inv;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 UWORD32 psi_st;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196 UWORD32 psi_st_32;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197 UWORD32 psi_st_inv;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199 T_AFC_PARAMS;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202 /* Swap IQ definitions... */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 #define SWAP_IQ_GSM 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 #define SWAP_IQ_DCS 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 #define SWAP_IQ_PCS 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 #define SWAP_IQ_GSM850 0 //TBD
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212 /* RF bands supported */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 #define RF_HW_BAND_SUPPORT (0x0020 \| 0x0004) // radio_band_support E-GSM/DCS + PC
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 // typedef
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223 /*************************************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224 /* Define structure for apc of TX Power ******/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225 /*************************************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228 { // pcm-file "rf/tx/level.gsm\|dcs"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 UWORD16 apc; // 0..31
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233 T_TX_LEVEL;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236 /* Automatic Gain Control */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238 /* Define structure for sub-band definition of TX Power ******/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 UWORD16 upper_bound; //highest physical arfcn of the sub-band
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243 WORD16 agc_calib; // AGC for each TXPWR
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244 }T_RF_AGC_BAND;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 /* Ramp definitions */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250 #if ((ANLG_FAM == 1) \|\| (ANLG_FAM == 2) \|\| (ANLG_FAM == 3))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253 UWORD8 ramp_up [16]; // Ramp-up profile
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254 UWORD8 ramp_down [16]; // Ramp-down profile
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256 T_TX_RAMP;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260 // RF structure definition
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261 //========================
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 enum RfRevision {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264 RF_IGNORE = 0x0000,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265 RF_SL2 = 0x1000,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266 RF_GAIA_20X = 0x2000,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267 RF_GAIA_20A = 0x2001,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 RF_GAIA_20B = 0x2002,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269 RF_ATLAS_20B = 0x2020,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 RF_PASCAL_20 = 0x2030
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271 };
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273 // Number of bands supported
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 #define GSM_BANDS 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276 #define MULTI_BAND1 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277 #define MULTI_BAND2 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279 // RF table sizes
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289 #define AGC_TABLE_SIZE 36
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294 // RX parameters and tables
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295 //-------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297 // AGC parameters and tables
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 UWORD16 low_agc_noise_thr;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301 UWORD16 high_agc_sat_thr;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 UWORD16 low_agc;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303 UWORD16 high_agc;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304 UWORD8 il2agc_pwr[121];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 UWORD8 il2agc_max[121];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306 UWORD8 il2agc_av[121];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308 T_AGC;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 // Calibration parameters
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 UWORD16 g_magic;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314 UWORD16 lna_att;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 UWORD16 lna_switch_thr_low;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 UWORD16 lna_switch_thr_high;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318 T_RX_CAL_PARAMS;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320 // RX temperature compensation
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323 WORD16 temperature;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324 WORD16 agc_calib;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326 T_RX_TEMP_COMP;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328 // RF RX structure
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 T_AGC agc;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333 T_RF_RX; //common
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335 // RF RX structure
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 T_RX_CAL_PARAMS rx_cal_params;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	340 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342 T_RF_RX_BAND;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 // TX parameters and tables
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346 //-------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348 // TX temperature compensation
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 WORD16 temperature;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352 #if (ORDER2_TX_TEMP_CAL==1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353 WORD16 a;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 WORD16 b;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 WORD16 c;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357 WORD16 apc_calib;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 T_TX_TEMP_CAL;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363 // Ramp up and ramp down delay
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 UWORD16 up;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 UWORD16 down;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369 T_RAMP_DELAY;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373 UWORD16 arfcn_limit;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 WORD16 chan_cal;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376 T_TX_CHAN_CAL;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378 // RF TX structure
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381 T_RAMP_DELAY ramp_delay;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 UWORD8 guard_bits; // number of guard bits needed for ramp up
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383 UWORD8 prg_tx;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385 T_RF_TX; //common
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 // RF TX structure
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395 T_RF_TX_BAND;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397 // band structure
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400 T_RF_RX_BAND rx;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401 T_RF_TX_BAND tx;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402 UWORD8 swap_iq;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404 T_RF_BAND;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406 // RF structure
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409 // common for all bands
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410 UWORD16 rf_revision;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411 UWORD16 radio_band_support;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412 T_RF_RX rx;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413 T_RF_TX tx;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 T_AFC_PARAMS afc;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416 T_RF;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419 /* MADC definitions */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421 // Omega: 5 external channels if touch screen not used, 3 otherwise
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422 enum ADC_INDEX {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423 ADC_VBAT,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424 ADC_VCHARG,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425 ADC_ICHARG,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 ADC_VBACKUP,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427 ADC_BATTYP,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428 ADC_BATTEMP,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429 ADC_ADC3, // name of this ??
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430 ADC_RFTEMP,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431 ADC_ADC4,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 };
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 WORD16 converted[ADC_INDEX_END]; // converted
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440 T_ADC;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443 /* MADC calibration */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447 UWORD16 a[ADC_INDEX_END];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 WORD16 b[ADC_INDEX_END];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450 T_ADCCAL;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 // Conversion table: ADC value -> temperature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455 UWORD16 adc; // ADC reading is 10 bits
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 WORD16 temp; // temp is in approx. range -30..+80
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458 T_TEMP;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462 char *name;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463 void *addr;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464 int size;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466 T_CONFIG_FILE;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470 char *name; // name of ffs file suffix
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471 T_RF_BAND *addr; // address to default flash structure
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472 UWORD16 max_carrier; // max carrier
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473 UWORD16 max_txpwr; // max tx power
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475 T_BAND_CONFIG;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477 typedef struct
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479 UWORD8 band[GSM_BANDS]; // index to band address
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480 UWORD8 txpwr_tp; // tx power turning point
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481 UWORD16 first_arfcn; // first index
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483 T_STD_CONFIG;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485 enum GSMBAND_DEF
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 BAND_NONE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488 BAND_EGSM900,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489 BAND_DCS1800,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490 BAND_PCS1900,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491 BAND_GSM850,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492 // put new bands here
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 BAND_GSM900 //last entry
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494 };
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498 /* ABB (Omega) Initialization */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501 #if ((ANLG_FAM == 1) \|\| (ANLG_FAM == 2))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 #define ABB_TABLE_SIZE 16
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505 #if (ANLG_FAM == 3)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506 #define ABB_TABLE_SIZE 22
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509 // Note that this translation is probably not needed at all. But until L1 is
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510 // (maybe) changed to simply initialize the ABB from a table of words, we
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511 // use this to make things more easy-readable.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513 #if (ANLG_FAM == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 enum ABB_REGISTERS {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515 ABB_AFCCTLADD = 0,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516 ABB_VBUCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 ABB_VBDCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518 ABB_BBCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519 ABB_APCOFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 ABB_BULIOFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521 ABB_BULQOFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 ABB_DAI_ON_OFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523 ABB_AUXDAC,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524 ABB_VBCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	525 ABB_APCDEL1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526 };
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	528
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529 #if (ANLG_FAM == 2)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530 enum ABB_REGISTERS {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	531 ABB_AFCCTLADD = 0,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532 ABB_VBUCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533 ABB_VBDCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534 ABB_BBCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 ABB_BULGCAL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536 ABB_APCOFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537 ABB_BULIOFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 ABB_BULQOFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	539 ABB_DAI_ON_OFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540 ABB_AUXDAC,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 ABB_VBCTRL1,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	542 ABB_VBCTRL2,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543 ABB_APCDEL1,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544 ABB_APCDEL2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545 };
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 #if (ANLG_FAM == 3)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549 enum ABB_REGISTERS {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 ABB_AFCCTLADD = 0,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551 ABB_VBUCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552 ABB_VBDCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553 ABB_BBCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554 ABB_BULGCAL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555 ABB_APCOFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 ABB_BULIOFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	557 ABB_BULQOFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	558 ABB_DAI_ON_OFF,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 ABB_AUXDAC,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560 ABB_VBCTRL1,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561 ABB_VBCTRL2,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	562 ABB_APCDEL1,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563 ABB_APCDEL2,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	564 ABB_VBPOP,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565 ABB_VAUDINITD,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566 ABB_VAUDCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	567 ABB_VAUOCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568 ABB_VAUSCTRL,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	569 ABB_VAUDPLL
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	570 };
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	571 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	572 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	573

FreeCalypso > hg > ffs-editor

annotate src/cs/layer1/cust0/l1_rf8.h @ 27:cb3f6fe694e1 default tip