ffs-editor: src/cs/layer1/include/l1

annotate src/cs/layer1/include/l1_confg.h @ 27:cb3f6fe694e1 default tip

README: document SE K2x0 addition

author	Mychaela Falconia <falcon@freecalypso.org>
date	Thu, 21 Dec 2023 21:44:43 +0000
parents	92470e5d0b9e
children

rev	line source
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /*********** Revision Controle System Header ***********
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 * GSM Layer 1 software
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 * L1_CONFG.H
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * Filename l1_confg.h
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 * Copyright 2003 (C) Texas Instruments
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 *********** Revision Controle System Header ***********/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 #ifndef __L1_CONFG_H__
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11 #define __L1_CONFG_H__
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13 #ifndef _WINDOWS
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 #include "l1sw.cfg" // Configuration Software
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 #include "board.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16 #include "chipset.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 #include "rf.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 #include "swconfig.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19 #include "sys.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 // Traces...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 // TRACE_TYPE == 1 -> L1/L3 interface trace
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26 // TRACE_TYPE == 2 -> Trace mode: ~33~~1~011...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 // TRACE_TYPE == 3 -> same as above (2) plus FER or stats trace
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28 // TRACE_TYPE == 4 -> L1/L3 interface trace on A-sample with protocol stack
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 // TRACE_TYPE == 5 -> trace for full simulation
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 // TRACE_TYPE == 6 -> CPU load trace for hisr
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 // TRACE_TYPE == 7 -> CPU LOAD trace for layer 1 hisr for all TDMA. Output on
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32 // UART at 38400 bps =>
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33 // format : <hisr cpu value in microseconds> <frame number>
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 // Code PB reported workaround
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 //------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39 // Code Version possible choices
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40 //------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 #define SIMULATION 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 #define NOT_SIMULATION 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44 // RCL functions Version possible choices
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 //------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46 #define POLL_FORCED 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #define RLC_SCENARIO 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 #define MODEM_FLOW 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 // possible choices for UART trace output
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51 //------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52 #define MODEM_UART 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #define IRDA_UART 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #if (CHIPSET == 12)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55 #define MODEM2_UART 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 //============
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 // CODE CHOICE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60 //============
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61 #if (OP_L1_STANDALONE==0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #define CODE_VERSION NOT_SIMULATION
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #else // OP_L1_STANDALONE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 #ifdef WIN32
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 #define CODE_VERSION SIMULATION
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66 #else // WIN32
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 #define CODE_VERSION NOT_SIMULATION
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 #endif // WIN32
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 #endif // OP_L1_STANDALONE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 //---------------------------------------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 // Test with full simulation.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 //---------------------------------------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74 #if (CODE_VERSION == SIMULATION)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 // Test Scenari...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 #define SCENARIO_FILE 1 // Test Scenario comes from input files.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78 #define SCENARIO_MEM 0 // Test Scenario comes from RAM.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 // Traces...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81 #undef TRACE_TYPE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82 #define TRACE_TYPE 5
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 #define LOGFILE_TRACE 1 // trace in an output logfile
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84 #define FLOWCHART 0 // Message sequence/flow chart trace.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85 #define NUCLEUS_TRACE 0 // Nucleus error trace
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86 #define EOTD_TRACE 1 // EOTD log trace
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 // Control algorithms...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92 #define AFC_ALGO 1 // AFC algorithm.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93 #define TOA_ALGO 1 // TOA algorithm.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94 #define AGC_ALGO 1 // AGC algorithm.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 #define TA_ALGO 0 // TA (Timing Advance) algorithm.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96 #undef VCXO_ALGO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97 #define VCXO_ALGO 0 // VCXO algo
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98 #undef DCO_ALGO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 #define DCO_ALGO 0 // DCO algo (TIDE)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 #undef ORDER2_TX_TEMP_CAL
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 #define FACCH_TEST 0 // FACCH test enabled.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 #define ADC_TIMER_ON 0 // Timer for ADC measurements
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107 #define AFC_ON 1 // Enable of the Omega AFC module
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109 #define AUDIO_TASK 1 // Enable the L1 audio features
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114 #define TTY_SYNC_MCU 1 // TTY WORKAROUND BUG03401
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 #define TTY_SYNC_MCU_2 1 //
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 #define L1_GTT_FIFO_TEST_ATOMIC 0 //
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 #define NEW_WKA_PATCH 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 #define OPTIMISED 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120 #define L1_RECOVERY 0 // L1 recovery
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 #undef L1_GPRS
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 #undef AMR
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 #define AMR 1 // AMR version 1.0 supported
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128 #undef L1_12NEIGH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 #define L1_12NEIGH 1 // new L1-RR interface for 12 neighbour cells
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131 #undef L1_GTT
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 #define L1_GTT 1 // Enable Global Text Telephony feature for simulation
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134 #undef OP_L1_STANDALONE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135 #define OP_L1_STANDALONE 1 // Selection of code for L1 stand alone
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 #undef OP_RIV_AUDIO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140 #undef OP_WCP
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	141 #define OP_WCP 0 // No WCP integration
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	142 //---------------------------------------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	143 // Test with H/W platform.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 //---------------------------------------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145 #elif (CODE_VERSION == NOT_SIMULATION)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147 #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 // Work around about Calypso RevA: the bus is floating (Cf PB01435)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149 // (corrected with Calypso ReV B and Calypso C035)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 #if (CHIPSET == 7)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151 #define W_A_CALYPSO_BUG_01435 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 #define W_A_CALYPSO_BUG_01435 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157 // for AMR thresolds definition CQ22226
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 #define AMR_THRESHOLDS_WORKAROUND 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 #if (L1_GTT==1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161 #define TTY_SYNC_MCU 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162 #define TTY_SYNC_MCU_2 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163 #define L1_GTT_FIFO_TEST_ATOMIC 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 #define NEW_WKA_PATCH 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 #define OPTIMISED 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167 #define TTY_SYNC_MCU_2 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 #define L1_GTT_FIFO_TEST_ATOMIC 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169 #define TTY_SYNC_MCU 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170 #define NEW_WKA_PATCH 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 #define OPTIMISED 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 // Traces...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176 #define NUCLEUS_TRACE 0 // Nucleus error trace
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177 #define FLOWCHART 0 // Message sequence/flow chart trace.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 #define LOGFILE_TRACE 0 // trace in an output logfile
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 // Test Scenari...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 #define SCENARIO_FILE 0 // Test Scenario comes from input files.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183 #define SCENARIO_MEM 1 // // Test Scenario comes from RAM.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 #define L2_L3_SIMUL 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 // Control algorithms...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192 #define AFC_ALGO 1 // AFC algorithm.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 #define TOA_ALGO 1 // TOA algorithm.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 #define AGC_ALGO 1 // AGC algorithm.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196 #define TA_ALGO 1 // TA (Timing Advance) algorithm.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 #define FACCH_TEST 0 // FACCH test enabled.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200 #define ADC_TIMER_ON 0 // Timer for ADC measurements
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 #define AFC_ON 1 // Enable of the Omega AFC module
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203 #define AUDIO_TASK 1 // Enable the L1 audio features
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 #define AUDIO_SIMULATION 0 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 #define AUDIO_L1_STANDALONE 1 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 #define AUDIO_L1_STANDALONE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 #define L1_RECOVERY 1 // L1 recovery
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 #if (L1_GPRS == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 #define RLC_VERSION RLC_SCENARIO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 #if (RLC_VERSION == RLC_SCENARIO)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222 // output stat on CRC error blocks
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223 // The user must enter the cs type and
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224 // the number of frames desired.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230 #define DSP_BACKGROUND_TASKS 1 // Enable the TEST of DSP background.tasks
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231 // activated by a layer 3 message (BG_TASK_START (<task number>))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 // deactivated by a layer 3 message (BG_TASK_STOP (<task number>))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233 // Warning : Works only with DSP>=31
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235 #define DSP_BACKGROUND_TASKS 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239 #define DSP_BACKGROUND_TASKS 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244 // Audio tasks selection
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 //-----------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 #if (AUDIO_TASK == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248 #define KEYBEEP 1 // Enable keybeep feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249 #define TONE 1 // Enable tone feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250 // Temporary modification for protocol stack compatibility - GSMLITE will be removed
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252 #define GSMLITE 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254 #if ((OP_L1_STANDALONE == 1) \|\| (!GSMLITE))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 #define MELODY_E1 1 // Enable melody format E1 feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256 #define VOICE_MEMO 1 // Enable voice memorization feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258 #define FIR 1 // Enable FIR feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 #if (DSP == 33) \|\| (DSP == 34) \|\| (DSP == 35) \|\| (DSP == 36)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260 #define AUDIO_MODE 1 // Enable Audio mode feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262 #define AUDIO_MODE 0 // Disable Audio mode feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265 #define MELODY_E1 0 // Disable melody format E1 feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266 #define VOICE_MEMO 0 // Disable voice memorization feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267 #if (MELODY_E2)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 #define FIR 1 // Enable FIR feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 #define FIR 0 // Disable FIR feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273 #define AUDIO_MODE 0 // Disable Audio mode feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 // Define CPORT for ESample only
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276 #if ((CHIPSET == 12) && ((DSP == 35) \|\| (DSP == 36)))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277 #define L1_CPORT 1 // Enable cport feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279 #define L1_CPORT 0 // Disable cport feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 #define KEYBEEP 0 // Enable keybeep feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284 #define TONE 0 // Enable tone feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285 #define MELODY_E1 0 // Enable melody format E1 feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286 #define VOICE_MEMO 0 // Enable voice memorization feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288 #define FIR 0 // Enable FIR feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289 #define AUDIO_MODE 0 // Enable Audio mode feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290 #define L1_CPORT 0 // Enable cport feature
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO \| MELODY_E2) // audio background task is used by speech reco and melody_e2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294 #if (OP_RIV_AUDIO == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295 #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299 // Vocoder selections
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 //-------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 #define FR 1 // Full Rate
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303 #define FR_HR 2 // Full Rate + Half Rate
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304 #define FR_EFR 3 // Full Rate + Enhanced Full Rate
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 // Standard (frequency plan) selections
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308 //-------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 #define GSM 1 // GSM900.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 #define GSM_E 2 // GSM900 Extended.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 #define PCS1900 3 // PCS1900.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 #define DCS1800 4 // DCS1800.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 #define GSM850 7 // GSM850 Band
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317 #define DUAL_US 8 // PCS1900 + GSM850
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319 /------------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320 /* Power Management */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321 /------------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325 /---------------------------------------------------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326 /* DSP configurations */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327 /* ------------------ */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328 /* DSP \| FR\| HR\|EFR\|14.4\| SPEED \|12LA68\|12LA68 \|4L32\|AEC\| MCU/DSP */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 /* (version) \| \| \| \| \| \|POLE80\|POLE112\| \|/NS\| interface */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331 /* 0 (821) \| x \| \| \| \| 39Mhz \| x \| \| \| \| 1 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333 /* 1 (830) \| x \| \| \| \| 39Mhz \| (1) \| \| x \| \| 1 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335 /* 2 (912) \| x \| x \| \| \| 58.5Mhz \| x \| \| \| \| 2 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337 /* 3 (10xx) \| x \| \| x \| x \| 65Mhz \| x \| \| \| x \| 3 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 /* ----------+---+---+---+----+---------+------+-------+----\|---+---------- */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339 /* 4 (11xx) \| x \| x \| x \| x \| 65Mhz \| x \| x (3)\| \| x \| 3 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	340 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341 /* 5 (830) \| x \| \| \| \| 39Mhz \| x \| \| \| \| 1 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343 /* 6 (11xx) \| x \| x \| x \| x \| 65Mhz \| x \| x (3)\| \|(2)\| 3 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 /* */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346 /(1) this version can be loaded on a 12LA68/POLE80 but the RIF/DL problem is/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347 /* not corrected. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348 /* */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349 /(2) AEC is disabled at DSP level but L1 must be compiled with MCU/DSP /
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350 /* interface which support AEC, therefore AEC is defined as 1. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 /* */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352 /(3) Pole112 include RIF DL correction. No patch is needed if this one only /
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353 /* include RIF/DL problem. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 /* */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 /---------------------------------------------------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 #if (DSP == 16 \|\| DSP == 17)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358 /* #define CLKMOD1 0x414e // ...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359 #define CLKMOD2 0x414e // ...65 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 #define CLKSTART 0x29 // ...65 Mips */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 #define CLKMOD1 0x4006 // ...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363 #define CLKMOD2 0x4116 // ...65 Mips pll free
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 #define CLKSTART 0x29 // ...65 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 /* #define CLKMOD1 0x2116 //This settings force the DSP to never enteridle
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 #define CLKMOD2 0x2116 //In this case the PLL will be always on. 39 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368 #define CLKSTART 0x25 // ...39 Mips */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370 #define VOC FR_HR_EFR // FR + HR + EFR.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371 #define DATA14_4 1 // No 14.4 data allowed.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372 #define AEC 1 // AEC/NS supported.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373 #define MAP 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 #define DSP_START 0x2000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379 /* DSP debug trace configuration */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380 /-------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381 #if (MELODY_E2)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 // In case of the melody E2 the DSP trace must be disable because the
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383 // melody instrument waves are overlayed with DSP trace buffer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385 // DSP debug trace API buufer config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389 // DSP debug trace API buufer config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394 #elif (DSP == 30) // First GPRS.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395 #define CLKMOD1 0x4006 // ...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396 #define CLKMOD2 0x4116 // ...65 Mips pll free
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397 #define CLKSTART 0x29 // ...65 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399 #define VOC FR_HR_EFR // FR + HR + EFR.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400 #define DATA14_4 1 // No 14.4 data allowed.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401 #define AEC 1 // AEC/NS not supported.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402 #define MAP 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 #define DSP_START 0x1F81
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405 #define ULYSSE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 #elif (DSP == 31) // ROM Code GPRS G0.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409 #define CLKMOD1 0x4006 // ...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410 #define CLKMOD2 0x4116 // ...65 Mips pll free
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411 #define CLKSTART 0x29 // ...65 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 #define DATA14_4 1 // 14.4 data allowed.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415 #define AEC 1 // AEC/NS not supported.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416 #define MAP 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418 #define DSP_START 0x8763
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421 #define INSTALL_ADD_WITH_PATCH 0x1352 // Used to set gprs_install_address pointer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424 #define ULYSSE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427 #elif (DSP == 32) // ROM Code GPRS G1.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428 #define CLKMOD1 0x4006 // ...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429 #define CLKMOD2 0x4116 // ...65 Mips pll free
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430 #define CLKSTART 0x29 // ...65 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 #define DATA14_4 1 // 14.4 data allowed.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434 #define AEC 1 // AEC/NS not supported.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435 #define MAP 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 #define DSP_START 0x8763
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442 #define ULYSSE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 #elif (DSP == 33) // ROM Code GPRS.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446 #define CLKMOD1 0x4006 // ...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447 #define CLKMOD2 0x4116 // ...65 Mips pll free
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 #define CLKSTART 0x29 // ...65 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451 #define AEC 1 // AEC/NS not supported.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 #if (OP_RIV_AUDIO == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453 #define L1_NEW_AEC 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455 // Available but not yet tuned with Riviera AUDIO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 #define L1_NEW_AEC 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458 #if ((L1_NEW_AEC) && (!AEC))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459 // First undef the flag to avoid warnings at compilation time
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460 #undef AEC
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 #define AEC 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464 #define MAP 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466 #define DSP_START 0x7000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471 #define ULYSSE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479 // management.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481 // DSP_IDLE3 is not supported in simulation
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484 #define W_A_DSP_IDLE3 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 // DSP software work-around config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488 // bit0 - Work-around to support CRTG.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494 #define C_DSP_SW_WORK_AROUND 0x0006
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496 #elif (ANLG_FAM == 2) // IOTA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497 #define C_DSP_SW_WORK_AROUND 0x000E
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499 #elif (ANLG_FAM == 3) // SYREN
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500 #define C_DSP_SW_WORK_AROUND 0x000E
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504 /* DSP debug trace configuration */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505 /-------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506 #if (MELODY_E2)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507 // In case of the melody E2 the DSP trace must be disable because the
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508 // melody instrument waves are overlayed with DSP trace buffer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510 // DSP debug trace API buufer config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 // DSP debug trace type config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521 // Currently not supported !
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524 // DSP debug trace API buufer config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	525 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	528 // DSP debug trace type config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	531 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537 /* d_error_status */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 /-------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	539
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	542
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544 #define DSP_DEBUG_GSM_MASK 0x0000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545 #define DSP_DEBUG_GPRS_MASK 0x0f3d
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 #if DCO_ALGO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549 // DCO type of scheduling
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 #define C_CN_DCO_PARAM 0xA248
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553 #elif (DSP == 34) // ROM Code GPRS AMR.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554 #define CLKMOD1 0x4006 // ...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555 #define CLKMOD2 0x4116 // ...65 Mips pll free
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 #define CLKSTART 0x29 // ...65 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	557 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	558 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 #define AEC 1 // AEC/NS not supported.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560 #if (OP_RIV_AUDIO == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561 #define L1_NEW_AEC 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	562 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563 // Available but not yet tuned with Riviera AUDIO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	564 #define L1_NEW_AEC 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566 #if ((L1_NEW_AEC) && (!AEC))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	567 // First undef the flag to avoid warnings at compilation time
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568 #undef AEC
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	569 #define AEC 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	570 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	571 #define MAP 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	572
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	573 #define DSP_START 0x7000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	574
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	575 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	576
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	577 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	578 #define ULYSSE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	579
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	580 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	581
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	582 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	583
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	584 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	585
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	586 // management.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	587
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	588 // DSP_IDLE3 is not supported in simulation
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	589
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	590 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	591 #define W_A_DSP_IDLE3 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	592 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	593
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	594 // DSP software work-around config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	595 // bit0 - Work-around to support CRTG.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	596 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	597 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	598 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	599 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	600 #define C_DSP_SW_WORK_AROUND 0x0006
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	601
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	602 #elif (ANLG_FAM == 2) // IOTA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	603 #define C_DSP_SW_WORK_AROUND 0x000E
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	604
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	605 #elif (ANLG_FAM == 3) // SYREN
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	606 #define C_DSP_SW_WORK_AROUND 0x000E
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	607
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	608 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	609
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	610 /* DSP debug trace configuration */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	611 /-------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	612 #if (MELODY_E2)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	613 // In case of the melody E2 the DSP trace must be disable because the
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	614 // melody instrument waves are overlayed with DSP trace buffer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	615
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	616 // DSP debug trace API buufer config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	617 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	618 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	619
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	620 // DSP debug trace type config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	621 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	622 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	623 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	624
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	625 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	626 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	627 // Currently not supported !
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	628 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	629 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	630 // DSP debug trace API buufer config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	631 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	632 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	633
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	634 // DSP debug trace type config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	635 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	636 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	637 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	638
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	639 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	640 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	641 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	642
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	643 // AMR trace
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	644 #define C_AMR_TRACE_ID 55
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	645
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	646 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	647 /* d_error_status */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	648 /-------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	649
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	650 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	651 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	652
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	653 // masks to apply on d_error_status bit field
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	654 #define DSP_DEBUG_GSM_MASK 0x0000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	655 #define DSP_DEBUG_GPRS_MASK 0x0f3d
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	656 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	657
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	658 #elif (DSP == 35) // ROM Code GPRS AMR.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	659 #define CLKMOD1 0x4006 // ...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	660 #define CLKMOD2 0x4116 // ...65 Mips pll free
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	661 #define CLKSTART 0x29 // ...65 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	662 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	663 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	664 #define AEC 1 // AEC/NS not supported.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	665 #if (OP_RIV_AUDIO == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	666 #define L1_NEW_AEC 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	667 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	668 // Available but not yet tuned with Riviera AUDIO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	669 #define L1_NEW_AEC 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	670 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	671 #if ((L1_NEW_AEC) && (!AEC))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	672 // First undef the flag to avoid warnings at compilation time
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	673 #undef AEC
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	674 #define AEC 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	675 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	676 #define MAP 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	677
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	678 #define FF_L1_TCH_VOCODER_CONTROL 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	679 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	680
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	681 #define DSP_START 0x7000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	682
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	683 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	684
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	685 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	686 #define ULYSSE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	687
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	688 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	689
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	690 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	691
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	692 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	693
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	694 // management.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	695
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	696 // DSP_IDLE3 is not supported in simulation
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	697
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	698 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	699 #define W_A_DSP_IDLE3 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	700 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	701
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	702 // DSP software work-around config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	703 // bit0 - Work-around to support CRTG.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	704 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	705 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	706 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	707 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	708 #define C_DSP_SW_WORK_AROUND 0x0006
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	709
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	710 #elif (ANLG_FAM == 2) // IOTA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	711 #define C_DSP_SW_WORK_AROUND 0x000E
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	712
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	713 #elif (ANLG_FAM == 3) // SYREN
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	714 #define C_DSP_SW_WORK_AROUND 0x000E
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	715
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	716 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	717
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	718 /* DSP debug trace configuration */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	719 /-------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	720 #if (MELODY_E2)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	721 // In case of the melody E2 the DSP trace must be disable because the
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	722 // melody instrument waves are overlayed with DSP trace buffer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	723
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	724 // DSP debug trace API buufer config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	725 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	726 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	727
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	728 // DSP debug trace type config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	729 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	730 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	731 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	732
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	733 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	734 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	735 // Currently not supported !
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	736 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	737 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	738 // DSP debug trace API buufer config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	739 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	740 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	741
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	742 // DSP debug trace type config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	743 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	744 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	745 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	746
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	747 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	748 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	749 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	750
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	751 // AMR trace
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	752 #define C_AMR_TRACE_ID 55
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	753
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	754 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	755 /* d_error_status */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	756 /-------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	757
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	758 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	759 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	760
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	761 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	762 #define DSP_DEBUG_GSM_MASK 0x08BD
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	763 #define DSP_DEBUG_GPRS_MASK 0x0f3d
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	764 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	765 #elif (DSP == 36) // ROM Code GPRS AMR.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	766 #define CLKMOD1 0x4006 // ...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	767 #define CLKMOD2 0x4116 // ...65 Mips pll free
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	768 #define CLKSTART 0x29 // ...65 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	769 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	770 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	771 #define AEC 1 // AEC/NS not supported.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	772 #if (OP_RIV_AUDIO == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	773 #define L1_NEW_AEC 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	774 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	775 // Available but not yet tuned with Riviera AUDIO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	776 #define L1_NEW_AEC 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	777 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	778 #if ((L1_NEW_AEC) && (!AEC))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	779 // First undef the flag to avoid warnings at compilation time
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	780 #undef AEC
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	781 #define AEC 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	782 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	783 #define MAP 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	784 #undef L1_AMR_NSYNC
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	785 #define L1_AMR_NSYNC 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	786 #define FF_L1_TCH_VOCODER_CONTROL 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	787 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	788
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	789 #define DSP_START 0x7000
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	790
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	791 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	792
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	793 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	794 #define ULYSSE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	795
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	796 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	797
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	798 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	799
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	800 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	801
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	802 // management.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	803
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	804 // DSP_IDLE3 is not supported in simulation
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	805
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	806 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	807 #define W_A_DSP_IDLE3 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	808 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	809
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	810 // DSP software work-around config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	811 // bit0 - Work-around to support CRTG.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	812 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	813 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	814 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	815 #if (ANLG_FAM == 1) // OMEGA / NAUSICA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	816 #define C_DSP_SW_WORK_AROUND 0x0006
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	817
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	818 #elif (ANLG_FAM == 2) // IOTA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	819 #define C_DSP_SW_WORK_AROUND 0x000E
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	820
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	821 #elif (ANLG_FAM == 3) // SYREN
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	822 #define C_DSP_SW_WORK_AROUND 0x000E
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	823 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	824
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	825 // This workaround should be enabled only for H2-sample on full build config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	826 #if (OP_L1_STANDALONE==1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	827 #define RAZ_VULSWITCH_REGAUDIO 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	828 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	829
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	830 /* DSP debug trace configuration */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	831 /-------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	832 #if (MELODY_E2)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	833 // In case of the melody E2 the DSP trace must be disable because the
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	834 // melody instrument waves are overlayed with DSP trace buffer
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	835
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	836 // DSP debug trace API buufer config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	837 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	838 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	839
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	840 // DSP debug trace type config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	841 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	842 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	843 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	844
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	845 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	846 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	847 // Currently not supported !
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	848 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	849 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	850 // DSP debug trace API buufer config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	851 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	852 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	853
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	854 // DSP debug trace type config
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	855 // \|<-------------- Features -------------->\|<---------- Levels ----------->\|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	856 // [15-8:UNUSED\|7:TIMER\|6:BURST\|5:BUFFER\|4:BUFFER HEADER\|3:UNUSED\|2:KERNEL\|1:BASIC\|0:ISR]
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	857 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	858
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	859 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	860 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	861 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	862
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	863 // AMR trace
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	864 #define C_AMR_TRACE_ID 55
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	865
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	866 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	867 /* d_error_status */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	868 /-------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	869
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	870 #if ((TRACE_TYPE == 1) \|\| (TRACE_TYPE == 4))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	871 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	872
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	873 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	874 #define DSP_DEBUG_GSM_MASK 0x08BD
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	875 #define DSP_DEBUG_GPRS_MASK 0x0f3d
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	876 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	877 #endif // DSP
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	878
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	879 /------------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	880 /* Default value */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	881 /------------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	882 #ifndef W_A_DSP1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	883 #define W_A_DSP1 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	884 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	885
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	886 #ifndef DATA14_4
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	887 #define DATA14_4 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	888 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	889
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	890 #ifndef W_A_ITFORCE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	891 #define W_A_ITFORCE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	892 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	893
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	894 #ifndef W_A_DSP_IDLE3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	895 #define W_A_DSP_IDLE3 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	896 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	897
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	898 #ifndef L1_NEW_AEC
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	899 #define L1_NEW_AEC 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	900 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	901
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	902 #ifndef DSP_DEBUG_TRACE_ENABLE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	903 #define DSP_DEBUG_TRACE_ENABLE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	904 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	905
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	906 #ifndef DEBUG_DEDIC_TCH_BLOCK_STAT
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	907 #define DEBUG_DEDIC_TCH_BLOCK_STAT 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	908 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	909
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	910 #ifndef D_ERROR_STATUS_TRACE_ENABLE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	911 #define D_ERROR_STATUS_TRACE_ENABLE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	912 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	913
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	914 #ifndef L1_GTT
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	915 #define L1_GTT 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	916 #define TTY_SYNC_MCU 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	917 #define TTY_SYNC_MCU_2 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	918 #define L1_GTT_FIFO_TEST_ATOMIC 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	919 #define NEW_WKA_PATCH 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	920 #define OPTIMISED 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	921 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	922
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	923 #ifndef L1_AMR_NSYNC
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	924 #define L1_AMR_NSYNC 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	925 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	926
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	927 #ifndef FF_L1_TCH_VOCODER_CONTROL
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	928 #define FF_L1_TCH_VOCODER_CONTROL 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	929 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	930 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	931
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	932 /------------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	933 /* Download */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	934 /------------------------------------/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	935
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	936
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	937 /* Possible values for the download status */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	938
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	939 #define LEAD_READY 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	940 #define BLOCK_READY 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	941 #define PROGRAM_DONE 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	942 #define PAGE_SELECTION 4
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	943
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	944
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	945 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	946 /* Options of compilation... */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	947 /************************************/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	948
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	949 // Possible choice of hardware plateform.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	950 #define GEMINI 1 // GEMINI chip (rom dsp code)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	951 #define POLESTAR 2 // POLESTAR chip (no rom)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	952
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	953 // Possible choice for DSP software setup.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	954 #define NO_DWNLD 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	955 #define PATCH_DWNLD 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	956 #define DSP_DWNLD 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	957 #define PATCH_DSP_DWNLD 3
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	958
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	959 // MAC-S status reporting to Layer 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	960 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	961
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	962
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	963 // Possible choice for dll_dcch_downlink interface (with FN or without FN)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	964 #define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	965
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	966 //---------------------------------------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	967
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	968 // Neighbor Cell RXLEV indication
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	969 #if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	970 #define L1_MPHC_RXLEV_IND_REPORT_SORT 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	971 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	972 #define L1_MPHC_RXLEV_IND_REPORT_SORT 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	973 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	974
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	975 #endif /* __L1_CONFG_H__ */

FreeCalypso > hg > ffs-editor

annotate src/cs/layer1/include/l1_confg.h @ 27:cb3f6fe694e1 default tip