ffs-editor: src/cs/system/main/init.c annotate

annotate src/cs/system/main/init.c @ 27:cb3f6fe694e1 default tip

README: document SE K2x0 addition

author	Mychaela Falconia <falcon@freecalypso.org>
date	Thu, 21 Dec 2023 21:44:43 +0000
parents	9a8a20d45be7
children

rev	line source
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	1 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	2 * INIT.C
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	3 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	4 * This module allows to initialize the board:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	5 * - wait states,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	6 * - unmask selected interrupts,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	7 * - initialize clock,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	8 * - disable watchdog.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	9 * Dummy functions used by the EVA3 library are defined.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	10 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	11
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	12 /* Config Files */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	13
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	14 #ifndef _WINDOWS
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	15 #include "l1sw.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	16 #include "rf.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	17 #include "chipset.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	18 #include "board.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	19 #include "swconfig.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	20 #include "fc-target.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	21 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	22 #include "rv.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	23 #include "sys.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	24 #include "debug.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	25 #ifdef BLUETOOTH_INCLUDED
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	26 #include "btemobile.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	27 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	28 #ifdef BLUETOOTH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	29 #include "bluetooth.cfg"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	30 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	31 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	32
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	33 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	34 #include "rv/rv_defined_swe.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	35 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	36 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	37
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	38 /* Include Files */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	39 #include <assert.h>
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	40 #include <ctype.h>
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	41 #include <stdarg.h>
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	42 #include <stdlib.h>
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	43 #include <string.h>
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	44
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	45 #include "nucleus.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	46
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	47 #include "sys_types.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	48 #include "l1_types.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	49 #include "l1_confg.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	50 #include "l1_const.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	51
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	52 #if TESTMODE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	53 #include "l1tm_defty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	54 #endif // TESTMODE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	55
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	56 #if (AUDIO_TASK == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	57 #include "l1audio_const.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	58 #include "l1audio_cust.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	59 #include "l1audio_defty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	60 #endif // AUDIO_TASK
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	61
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	62 #if (L1_GTT == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	63 #include "l1gtt_const.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	64 #include "l1gtt_defty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	65 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	66
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	67 #if (L1_MP3 == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	68 #include "l1mp3_defty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	69 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	70
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	71 #if (L1_MIDI == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	72 #include "l1midi_defty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	73 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	74
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	75 #if (L1_AAC == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	76 #include "l1aac_defty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	77 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	78 #if (L1_DYN_DSP_DWNLD == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	79 #include "l1_dyn_dwl_defty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	80 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	81
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	82 #if (TRACE_TYPE == 4)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	83 #include "l1_defty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	84 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	85
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	86
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	87 #if ((OP_L1_STANDALONE == 1) && (CODE_VERSION != SIMULATION) && (PSP_STANDALONE == 0))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	88
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	89 #if (AUDIO_TASK == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	90 #include "l1audio_signa.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	91 #include "l1audio_msgty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	92 #endif // AUDIO_TASK
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	93
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	94 #if (L1_GTT == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	95 #include "l1gtt_signa.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	96 #include "l1gtt_msgty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	97 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	98
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	99 #include "l1_defty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	100 #include "cust_os.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	101 #include "l1_msgty.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	102 #include "nu_main.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	103 #include "l1_varex.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	104 #include "l1_proto.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	105 #include "hw_debug.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	106 #include "l1_trace.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	107
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	108 #endif /* ((OP_L1_STANDALONE == 1) && (CODE_VERSION != SIMULATION) && (PSP_STANDALONE==0)) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	109
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	110
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	111 #include "armio/armio.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	112 #include "timer/timer.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	113
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	114 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	115 #include "rvf/rvf_api.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	116 #include "rvm/rvm_api.h" /* A-M-E-N-D-E-D! */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	117 #include "sim/sim.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	118 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	119
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	120 #include "abb/abb.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	121
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	122 #include "inth/iq.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	123 #include "tpudrv.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	124 #include "memif/mem.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	125 #include "clkm/clkm.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	126 #include "inth/inth.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	127
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	128 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	129 #include "uart/serialswitch_core.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	130 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	131 #include "uart/serialswitch.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	132 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	133 #include "uart/traceswitch.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	134
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	135
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	136 #include "dma/dma.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	137 #include "rhea/rhea_arm.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	138
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	139 #include "ulpd/ulpd.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	140
17 9a8a20d45be7 Timer2 for Nucleus RTOS ticks Mychaela Falconia <falcon@freecalypso.org> parents: 13 diff changeset	141 /* FC FFS editor */
9a8a20d45be7 Timer2 for Nucleus RTOS ticks Mychaela Falconia <falcon@freecalypso.org> parents: 13 diff changeset	142 #include "timer2.h"
9a8a20d45be7 Timer2 for Nucleus RTOS ticks Mychaela Falconia <falcon@freecalypso.org> parents: 13 diff changeset	143
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	144 #if (PSP_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	145 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	146 extern void ffs_main_init(void);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	147 extern void create_tasks(void);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	148 #if TI_NUC_MONITOR == 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	149 extern void ti_nuc_monitor_tdma_action( void );
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	150 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	151
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	152 #if WCP_PROF == 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	153 #if PRF_CALIBRATION == 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	154 extern NU_HISR prf_CalibrationHISR;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	155 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	156 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	157
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	158 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	159 void l1ctl_pgm_clk32(UWORD32 nb_hf, UWORD32 nb_32khz);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	160 extern void L1_trace_string(char *s);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	161 #endif /* (OP_L1_STANDALONE) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	162 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	163
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	164 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	165 #if ((TRACE_TYPE==1) \|\| (TRACE_TYPE==2) \|\| (TRACE_TYPE==3) \|\| (TRACE_TYPE==7) \|\| TESTMODE)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	166 #include "uart/uart.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	167 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	168 * Serial Configuration set up.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	169 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	170
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	171 extern char ser_cfg_info[NUMBER_OF_TR_UART];
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	172 #include "rvt_gen.h"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	173 extern T_RVT_USER_ID trace_id;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	174 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	175 #endif /* (OP_L1_STANDALONE == 1) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	176
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	177 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	178 * Serial Configuration set up.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	179 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	180
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	181 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	182 ** One config is:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	183 ** {XXX_BT_HCI, // Bluetooth HCI
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	184 ** XXX_FAX_DATA, // Fax/Data AT-Cmd
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	185 ** XXX_TRACE, // L1/Riviera Trace Mux
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	186 ** XXX_TRACE}, // Trace PS
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	187 **
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	188 ** with XXX being DUMMY, UART_IRDA or UART_MODEM
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	189 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	190
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	191 #if ((((TRACE_TYPE==1) \|\| (TRACE_TYPE==2) \|\| (TRACE_TYPE==3) \|\| (TRACE_TYPE==7) \|\|\
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	192 (TESTMODE)) && (OP_L1_STANDALONE == 1)) \|\| (OP_L1_STANDALONE == 0))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	193 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	194 static T_AppliSerialInfo appli_ser_cfg_info =
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	195 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	196 T_AppliSerialInfo appli_ser_cfg_info =
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	197 #endif /* OP_L1_STANDALONE */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	198 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	199 #ifdef CONFIG_RVTMUX_ON_MODEM
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	200 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	201 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	202 UART_MODEM_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	203 DUMMY_TRACE}, // 0x0248
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	204 #else // RVTMUX_ON_MODEM
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	205 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	206 UART_MODEM_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	207 UART_IRDA_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	208 DUMMY_TRACE}, // default config = 0x0168
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	209 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	210 #ifdef BTEMOBILE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	211 12, // 12 serial config allowed
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	212 #else // BTEMOBILE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	213 9, // 9 serial config allowed
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	214 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	215 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	216 // Configs with Condat Panel only
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	217 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	218 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	219 DUMMY_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	220 UART_IRDA_TRACE}, // 0x1048
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	221 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	222 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	223 DUMMY_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	224 UART_MODEM_TRACE}, // 0x2048
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	225 // Configs with L1/Riviera Trace only
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	226 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	227 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	228 UART_IRDA_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	229 DUMMY_TRACE}, // 0x0148
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	230 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	231 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	232 UART_MODEM_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	233 DUMMY_TRACE}, // 0x0248
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	234 // Configs with AT-Cmd only
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	235 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	236 UART_MODEM_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	237 DUMMY_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	238 DUMMY_TRACE}, // 0x0068
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	239 // Configs with Condat Panel and L1/Riviera Trace
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	240 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	241 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	242 UART_MODEM_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	243 UART_IRDA_TRACE}, // 0x1248
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	244 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	245 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	246 UART_IRDA_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	247 UART_MODEM_TRACE}, // 0x2148
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	248 // Configs with Condat Panel and AT-Cmd
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	249 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	250 UART_MODEM_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	251 DUMMY_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	252 UART_IRDA_TRACE}, // 0x1068
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	253 #ifdef BTEMOBILE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	254 // Configs with L1/Riviera Trace and Bluetooth HCI
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	255 {UART_IRDA_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	256 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	257 UART_MODEM_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	258 DUMMY_TRACE}, // 0x0249
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	259 {UART_MODEM_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	260 DUMMY_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	261 UART_IRDA_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	262 DUMMY_TRACE}, // 0x014A
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	263 // Configs with AT-Cmd and Bluetooth HCI
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	264 {UART_IRDA_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	265 UART_MODEM_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	266 DUMMY_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	267 DUMMY_TRACE}, // 0x0069
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	268 #endif // BTEMOBILE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	269 // Configs with L1/Riviera Trace and AT-Cmd
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	270 {DUMMY_BT_HCI,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	271 UART_MODEM_FAX_DATA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	272 UART_IRDA_TRACE,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	273 DUMMY_TRACE} // 0x0168
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	274 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	275 };
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	276 #endif /* (TRACE_TYPE ...) \|\| (OP_L1_STANDALONE == 0) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	277
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	278
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	279 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	280 * Init_Target
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	281 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	282 * Performs low-level HW Initialization.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	283 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	284 void Init_Target(void)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	285 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	286 #if (BOARD == 5)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	287 #define WS_ROM (1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	288 #define WS_RAM (1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	289 #define WS_APIF (1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	290 #define WS_CS2 (7) /* LCD on EVA3. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	291 #define WS_CS0 (7) /* DUART on EVA3. UART16750 and latch on A-Sample. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	292 #define WS_CS1 (7) /* LCD on A-Sample. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	293
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	294 IQ_InitWaitState (WS_ROM, WS_RAM, WS_APIF, WS_CS2, WS_CS0, WS_CS1);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	295 IQ_InitClock (2); /* Internal clock division factor. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	296
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	297 IQ_MaskAll (); /* Mask all interrupts. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	298 IQ_SetupInterrupts (); /* IRQ priorities. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	299
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	300 TM_DisableWatchdog ();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	301
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	302 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	303 * Reset all TSP and DBG fdefault values
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	304 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	305
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	306 AI_ResetTspIO ();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	307 AI_ResetDbgReg ();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	308 AI_ResetIoConfig ();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	309
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	310 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	311 * Warning! The external reset signal is connected to the Omega and the
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	312 * external device. If the layer 1 is used its initialization removes
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	313 * the external reset. If the application does not use the layer 1
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	314 * you must remove the external reset (bit 2 of the reset control
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	315 * register 0x505808).
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	316 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	317
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	318 AI_ResetTspIO();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	319 AI_ResetDbgReg();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	320 AI_ResetIoConfig();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	321
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	322 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	323 * Configure all IOs (see RD300 specification).
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	324 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	325
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	326 AI_ConfigBitAsInput (1);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	327 AI_EnableBit (1);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	328
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	329 AI_ConfigBitAsOutput (2);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	330 AI_EnableBit (2);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	331
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	332 AI_ConfigBitAsInput (11);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	333 AI_EnableBit (11);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	334
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	335 AI_ConfigBitAsOutput (13);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	336 AI_EnableBit (13);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	337
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	338 AI_Power (1); /* Maintain power supply. */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	339
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	340 #elif (BOARD == 6) \|\| (BOARD == 7) \|\| (BOARD == 8) \|\| (BOARD == 9) \|\| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	341 (BOARD == 40) \|\| (BOARD == 41) \|\| (BOARD == 42) \|\| (BOARD == 43) \|\| (BOARD == 45) \|\| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	342 (BOARD == 35) \|\| (BOARD == 46) \|\| (BOARD == 70) \|\| (BOARD == 71)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	343
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	344 #if (PSP_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	345 // RIF/SPI rising edge clock for ULYSSE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	346 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	347 #if ((ANLG_FAM == 1) \|\| (ANLG_FAM == 2) \|\| (ANLG_FAM == 3)\|\| (ANLG_FAM == 11))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	348 #if ((CHIPSET >= 3))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	349 #if (CHIPSET == 12)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	350 F_CONF_RIF_RX_RISING_EDGE;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	351 F_CONF_SPI_RX_RISING_EDGE;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	352 #elif (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	353 //do the DRP init here for Locosto
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	354 #if (L1_DRP == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	355 // drp_power_on(); This should be done after the script is downloaded.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	356 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	357 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	358 #if (BOARD==35)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	359 ((volatile SYS_UWORD16 ) ASIC_CONF) = 0x2000;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	360 #elif defined(CONFIG_TARGET_PIRELLI)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	361 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	362 * Pirelli's version of this Init_Target() function
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	363 * in their fw sets the ASIC_CONF register to 0x6050,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	364 * which means PWL on the LT/PWL pin and LPG on the
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	365 * DSR_MODEM pin.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	366 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	367 ((volatile SYS_UWORD16 ) ASIC_CONF) = 0x6050;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	368 #elif defined(CONFIG_TARGET_GTAMODEM) \|\| defined(CONFIG_TARGET_GTM900)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	369 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	370 * The DSR_MODEM/LPG Calypso signal is unconnected on
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	371 * Openmoko's modem, so let's mux it as LPG (output)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	372 * so it doesn't float, like Foxconn seem to have done
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	373 * on the Pirelli.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	374 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	375 * On the GTM900 module this signal is explicitly defined as LPG.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	376 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	377 ((volatile SYS_UWORD16 ) ASIC_CONF) = 0x6040;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	378 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	379 ((volatile SYS_UWORD16 ) ASIC_CONF) = 0x6000;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	380 #endif /* (BOARD == 35) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	381 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	382 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	383 #endif /* ANLG(ANALOG)) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	384
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	385 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	386 #if (BOARD == 40) \|\| (BOARD == 41) \|\| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	387 (BOARD == 42) \|\| (BOARD == 43) \|\| (BOARD == 45)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	388 // enable 8 Ohm amplifier for audio on D-sample
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	389 AI_ConfigBitAsOutput (1);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	390 AI_SetBit(1);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	391 #elif (BOARD == 70) \|\| (BOARD == 71)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	392 //Locosto I-sample or UPP costo board.BOARD
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	393 // Initialize the ARMIO bits as per the I-sample spec
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	394 // FIXME
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	395 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	396 #endif /* (OP_L1_STANDALONE == 1) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	397 #endif /* PSP_STANDALONE ==0 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	398
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	399 // Watchdog
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	400 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	401 TM_DisableWatchdog(); /* Disable Watchdog */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	402 #if (CHIPSET == 12) \|\| (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	403 TM_SEC_DisableWatchdog();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	404 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	405
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	406 #if ((CHIPSET == 4) \|\| (CHIPSET == 7) \|\| (CHIPSET == 8) \|\| (CHIPSET == 10) \|\| (CHIPSET == 11) \|\| (CHIPSET == 12) \|\| (CHIPSET == 15))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	407
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	408 #if (CHIPSET == 12)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	409
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	410 #if 0 /* example of configuration for DMA debug */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	411 #if (BOARD == 6) /* debug on EVA 4 , GPO2 must not be changed */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	412
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	413 /* TPU_FRAME, NMIIT, IACKn */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	414 F_DBG_IRQ_CONFIG(C_DBG_IRQ_IRQ4\|C_DBG_IRQ_NMIIT\|C_DBG_IRQ_IACKN);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	415
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	416 /* NDMA_REQ_VIEW1, NDMA_REQ_VIEW0, DMA_V(1), DMA_S(1), DMAREQ_P1(3:0)*/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	417 F_DBG_DMA_P1_NDFLASH_CONFIG(C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_1 \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	418 C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_0 \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	419 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_3 \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	420 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_2 \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	421 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_1 \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	422 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_0 \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	423 C_DBG_DMA_P1_NDFLASH_DMA_REQ_S_1 \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	424 C_DBG_DMA_P1_NDFLASH_DMA_REQ_V1 );
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	425 /* DMA_REQ_S(2)*/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	426 F_DBG_DMA_P2_CONFIG(C_DBG_DMA_P2_DMA_REQ_S2);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	427
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	428 /* DMA_CLK_REQ, BRIDGE_CLK */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	429 F_DBG_CLK1_CONFIG(C_DBG_CLK1_DMA_CLK_REQ \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	430 C_DBG_CLK1_BRIDGE_CLK );
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	431
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	432 /* XIO_nREADY */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	433 F_DBG_IMIF_CONFIG(C_DBG_IMIF_XIO_NREADY_MEM);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	434
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	435 /* DSP_nIRQ_VIEW1, DSP_nIRQ_VIEW0, BRIDGE_EN */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	436 F_DBG_KB_USIM_SHD_CONFIG(C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_1 \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	437 C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_0 \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	438 C_DBG_KB_USIM_SHD_BRIDGE_EN );
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	439
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	440 /* RHEA_nREADY , RHEA_nSTROBE */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	441 F_DBG_USIM_CONFIG(C_DBG_USIM_RHEA_NSTROBE \|
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	442 C_DBG_USIM_RHEA_NREADY );
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	443
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	444 /* XIO_STROBE */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	445 F_DBG_MISC2_CONFIG(C_DBG_MISC2_X_IOSTRBN);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	446
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	447 /* DMA_CLK_REQ */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	448 F_DBG_CLK2_CONFIG(C_DBG_CLK2_DMA_CLK_REQ2);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	449
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	450 /* DSP_IRQ_SEL0=DMA, DSP_IRQ_SEL1=DMA, DMA_REQ_SEL0=RIF_RX, DMA_REQ_SEL1=RIF_RX */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	451 F_DBG_VIEW_CONFIG(0,0,C_DBG_DSP_INT_DMA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	452 C_DBG_DSP_INT_DMA,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	453 C_DMA_CHANNEL_RIF_RX,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	454 C_DMA_CHANNEL_RIF_RX);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	455
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	456 #endif /* (BOARD == 6) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	457 #endif /* DMA debug example */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	458 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	459 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	460 * Configure ASIC in order to output the DPLL and ARM clock
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	461 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	462 // (( volatile UWORD16 )(0xFFFEF008)) = 0x8000; // DPLL
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	463 // (( volatile UWORD16 )(0xFFFEF00E)) = 0x0004; // ARM clock
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	464 // (( volatile UWORD16 )(0xfffef004)) = 0x0600; // DSP clock + nIACK
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	465 #endif /* (CHIPSET == 12) \|\| CHIPSET == 15*/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	466
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	467
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	468 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	469 * Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	470 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	471 // IRQ, Timer and bridge may SLEEP
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	472 // In first step, same configuration as SAMSON
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	473 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	474 #if (CHIPSET == 12)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	475 CLKM_INITCNTL(CLKM_IRQ_DIS \| CLKM_TIMER_DIS \| CLKM_BRIDGE_DIS \| CLKM_DPLL_DIS);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	476 #elif (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	477 CLKM_INITCNTL(CLKM_IRQ_DIS \| CLKM_TIMER_DIS \| CLKM_CPORT_EN \| CLKM_BRIDGE_DIS \| 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	478
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	479 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	480 CLKM_INITCNTL(CLKM_IRQ_DIS \| CLKM_TIMER_DIS);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	481
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	482 // Select VTCXO input frequency
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	483 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	484 CLKM_UNUSED_VTCXO_26MHZ;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	485
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	486 // Rita RF uses 26MHz VCXO
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	487 #if (RF_FAM == 12)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	488 CLKM_USE_VTCXO_26MHZ;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	489 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	490 // Renesas RF uses 26MHz on F-sample but 13MHz on TEB
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	491 #if (RF_FAM == 43) && (BOARD == 46)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	492 CLKM_USE_VTCXO_26MHZ;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	493 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	494 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	495
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	496
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	497 // Control HOM/SAM automatic switching
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	498 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	499 ((volatile unsigned short ) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	500
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	501 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	502 * The following part has been reconstructed from disassembly.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	503 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	504 RHEA_INITRHEA(0,0,0xFF);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	505 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	506 #if (CHIPSET == 8)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	507 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	508 #elif (CHIPSET == 10) \|\| (CHIPSET == 11)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	509 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	510 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	511 #error "We only have DPLL setup for CHIPSETs 8 and 10"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	512 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	513 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	514 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	515 * FreeCalypso change: memory timings and widths are target-dependent;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	516 * please refer to the MEMIF-wait-states document in the freecalypso-docs
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	517 * repository for the full explanation.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	518 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	519 #ifdef CONFIG_TARGET_PIRELLI
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	520 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	521 * Pirelli's version of this Init_Target() function
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	522 * in their fw does the following:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	523 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	524 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	525 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	526 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	527 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	528 MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	529 #elif defined(CONFIG_TARGET_C155)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	530 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	531 * C155/156 official fw MEMIF config is almost the same as Pirelli's,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	532 * only nCS4 WS is different, but nCS4 is unused on this model...
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	533 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	534 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	535 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	536 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	537 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	538 MEM_INIT_CS4(6, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	539 #elif defined(CONFIG_TARGET_C11X) \|\| defined(CONFIG_TARGET_C139) \|\| \
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	540 defined(CONFIG_TARGET_GTAMODEM)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	541 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	542 * The original settings from Openmoko,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	543 * only nCS0 and nCS1 are actually used,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	544 * same as on Mot C1xx phones,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	545 * the nCS2/3/4 settings are dummies from TI.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	546 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	547 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	548 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	549 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	550 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	551 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	552 #elif defined(CONFIG_TARGET_J100)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	553 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	554 * Same as Mot C11x/12x/139/140 and Openmoko except for nCS2 WS:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	555 * it appears that SE J100 has its ringtone melody generator chip
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	556 * hooked up there.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	557 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	558 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	559 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	560 MEM_INIT_CS2(6, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	561 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	562 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	563 #elif (CHIPSET == 8)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	564 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	565 * Our only Calypso C05 target is Mother Mychaela's D-Sample board.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	566 * WS=3 with the ARM7 core running at 39 MHz gives us 92 ns,
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	567 * so we should be good on this board.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	568 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	569 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	570 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	571 MEM_INIT_CS2(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	572 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	573 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	574 #elif (CHIPSET == 10) \|\| (CHIPSET == 11)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	575 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	576 * Default for Calypso C035 targets in the absence of a more specific
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	577 * selection above. We put the WS=4 memory-oriented setting on all
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	578 * chip selects so we automatically cover targets with a second flash
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	579 * chip select no matter if it's nCS2, nCS3 or nCS4, as well as even
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	580 * weirder targets with XRAM somewhere other than nCS1.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	581 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	582 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	583 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	584 MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	585 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	586 MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	587 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	588 #error "Unknown MEMIF configuration"
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	589 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	590 MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	591 MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	592 RHEA_INITAPI(0,1);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	593 RHEA_INITARM(0,0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	594 DPLL_SET_PLL_ENABLE;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	595
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	596 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	597 * Disable and Clear all pending interrupts
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	598 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	599 #if (CHIPSET == 12) \|\| (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	600 F_INTH_DISABLE_ALL_IT; // MASK all it
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	601 F_INTH2_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH2 IRQ
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	602 F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	603 F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	604 F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	605 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	606 INTH_DISABLEALLIT;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	607 #if 0 /* not present in our reference binary object */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	608 INTH_RESETALLIT;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	609 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	610 INTH_CLEAR; /* reset IRQ/FIQ source */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	611 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	612
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	613 // INTH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	614 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	615 #if (CHIPSET == 12) \|\| (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	616 #if (GSM_IDLE_RAM != 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	617 f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram); // setup configuration IT handlers
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	618 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	619 f_inth_setup((T_INTH_CONFIG *)a_inth_config); // setup configuration IT handlers
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	620 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	621 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	622 IQ_SetupInterrupts();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	623 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	624
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	625
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	626 #if (CHIPSET == 12) \|\| (CHIPSET == 15)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	627 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	628
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	629 f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	630 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	631 f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	632 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	633 f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	634 f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	635 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	636
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	637 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	638 // DMA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	639 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	640 // channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	641 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	642 DMA_ALLOCDMA(1,0,1,1); // Channel 1 used by DSP with RIF RX
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	643 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	644 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	645
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	646 /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	647
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	648 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	649
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	650 // RHEA Bridge
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	651 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	652 // ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	653 RHEA_INITRHEA(0,0,0x7F);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	654
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	655 #if (CHIPSET == 6)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	656 // WS_H = 1 , WS_L = 15
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	657 RHEA_INITAPI(1,15); // should be 0x01E1 for 65 Mhz
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	658 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	659 // WS_H = 0 , WS_L = 7
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	660 RHEA_INITAPI(0,7); // should be 0x0101 for 65 Mhz
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	661 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	662
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	663 // Write_en_0 = 0 , Write_en_1 = 0
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	664 RHEA_INITARM(0,0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	665
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	666 // INTH
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	667 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	668 INTH_DISABLEALLIT; // MASK all it
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	669 INTH_CLEAR; // reset IRQ/FIQ source
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	670 IQ_SetupInterrupts();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	671
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	672 // DMA
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	673 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	674 // channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	675 DMA_ALLOCDMA(1,0,1,1); // should be 0x25 (channel 1 = lead)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	676
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	677 #if (CHIPSET == 6)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	678 // Memory WS configuration for ULYSS/G1 (26 Mhz) board
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	679 //-----------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	680 MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	681 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	682
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	683 // CLKM
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	684 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	685 CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	686
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	687 #if (CHIPSET == 6)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	688 CLKM_INITCNTL(CLKM_IRQ_DIS \| CLKM_BRIDGE_DIS \| CLKM_TIMER_DIS \| CLKM_VTCXO_26);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	689 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	690 CLKM_INITCNTL(CLKM_IRQ_DIS \| CLKM_BRIDGE_DIS \| CLKM_TIMER_DIS);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	691 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	692
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	693 #endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	694
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	695 // Freeze ULPD timer ....
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	696 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	697 ((volatile SYS_UWORD16 ) ULDP_GSM_TIMER_INIT_REG ) = 0;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	698 ((volatile SYS_UWORD16 ) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	699
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	700 // reset INC_SIXTEEN and INC_FRAC
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	701 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	702 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	703 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	704 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	705 ULDP_INCSIXTEEN_UPDATE(132); //32768.29038 =>132, 32500 => 133
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	706 // 26000 --> 166
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	707 ULDP_INCFRAC_UPDATE(15840); //32768.29038 =>15840, 32500 => 21845
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	708 // 26000 --> 43691
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	709 #endif /* OP_L1_STANDALONE */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	710
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	711 // program ULPD WAKE-UP ....
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	712 //=================================================
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	713 #if (CHIPSET == 2)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	714 ((volatile SYS_UWORD16 )ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 2 frame
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	715 ((volatile SYS_UWORD16 )ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 31 periods
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	716 ((volatile SYS_UWORD16 )ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	717 ((volatile SYS_UWORD16 )ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	718 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	719 ((volatile SYS_UWORD16 )ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	720 ((volatile SYS_UWORD16 )ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	721 ((volatile SYS_UWORD16 )ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	722 ((volatile SYS_UWORD16 )ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	723 ((volatile SYS_UWORD16 )ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	724 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	725
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	726 // Set Gauging versus HF (PLL)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	727 //=================================================
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	728 ULDP_GAUGING_SET_HF; // Enable gauging versus HF
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	729 ULDP_GAUGING_HF_PLL; // Gauging versus PLL
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	730
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	731 // current supply for quartz oscillation
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	732 //=================================================
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	733 #if (OP_L1_STANDALONE == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	734 #if ((CHIPSET != 9) && (CHIPSET != 12) && (CHIPSET !=15)) // programming model changed for Ulysse C035, stay with default value
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	735 (volatile SYS_UWORD16 )QUARTZ_REG = 0x27;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	736 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	737 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	738 #if ((BOARD == 6) \|\| (BOARD == 8) \|\| (BOARD == 9) \|\| (BOARD == 35) \|\| (BOARD == 40) \|\| (BOARD == 41))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	739 ((volatile SYS_UWORD16 )QUARTZ_REG) = 0x27;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	740 #elif (BOARD == 7)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	741 ((volatile SYS_UWORD16 )QUARTZ_REG) = 0x24;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	742 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	743 #endif /* OP_L1_STANDALONE */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	744
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	745 // stop Gauging if any (debug purpose ...)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	746 //--------------------------------------------------
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	747 if ( ((volatile SYS_UWORD16 ) ULDP_GAUGING_CTRL_REG) & ULDP_GAUGING_EN)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	748 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	749 volatile UWORD32 j;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	750 ULDP_GAUGING_STOP; /* Stop the gauging */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	751 /* wait for gauging it*/
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	752 // one 32khz period = 401 periods of 13Mhz
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	753 for (j=1; j<50; j++);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	754 while (! (* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	755 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	756
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	757 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	758 AI_ClockEnable ();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	759
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	760 #if (BOARD == 7)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	761 // IOs configuration of the B-Sample in order to optimize the power consumption
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	762 AI_InitIOConfig();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	763
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	764 // Set LPG instead of DSR_MODEM
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	765 ((volatile SYS_UWORD16 ) ASIC_CONF) \|= 0x40;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	766 // Reset the PERM_ON bit of LCR_REG
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	767 ((volatile SYS_UWORD16 ) MEM_LPG) &= ~(0x80);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	768 #elif ((BOARD == 8) \|\| (BOARD == 9))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	769 // IOs configuration of the C-Sample in order to optimize the power consumption
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	770 AI_InitIOConfig();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	771
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	772 // set the debug latch to 0x00.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	773 ((volatile SYS_UWORD8 ) 0x2800000) = 0x00;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	774 #elif ((BOARD == 35) \|\| (BOARD == 46))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	775 AI_InitIOConfig();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	776 // CSMI INTERFACE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	777 // Initialize CSMI clients for GSM control
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	778 // and Fax/Data services
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	779 CSMI_Init();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	780 GC_Initialize(); // GSM control initialization
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	781 CU_Initialize(); // Trace initialization
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	782 CF_Initialize(); // Fax/Data pre-initialization
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	783 #elif ((BOARD == 40) \|\| (BOARD == 41))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	784 // IOs configuration of the D-Sample in order to optimize the power consumption
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	785 AI_InitIOConfig();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	786
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	787 #ifdef BTEMOBILE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	788 // Reset BT chip by toggling the Island's nRESET_OUT signal
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	789 ((volatile SYS_UWORD16 ) 0xFFFFFD04) \|= 0x04;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	790 ((volatile SYS_UWORD16 ) 0xFFFFFD04) &= ~(0x4);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	791 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	792
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	793 // set the debug latch to 0x0000.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	794 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	795 * FreeCalypso change: this write is only correct when running
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	796 * on an actual D-Sample board, but not on any of the real-world
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	797 * Calypso target devices.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	798 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	799 #ifdef CONFIG_TARGET_DSAMPLE
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	800 ((volatile SYS_UWORD16 ) 0x2700000) = 0x0000;
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	801 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	802 #endif // BOARD
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	803
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	804 // Enable HW Timers 1 & 2
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	805 TM_EnableTimer (1);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	806 TM_EnableTimer (2);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	807
17 9a8a20d45be7 Timer2 for Nucleus RTOS ticks Mychaela Falconia <falcon@freecalypso.org> parents: 13 diff changeset	808 /* FC FFS editor */
9a8a20d45be7 Timer2 for Nucleus RTOS ticks Mychaela Falconia <falcon@freecalypso.org> parents: 13 diff changeset	809 Dtimer2_Init_cntl (1875, 1, 0, 1);
9a8a20d45be7 Timer2 for Nucleus RTOS ticks Mychaela Falconia <falcon@freecalypso.org> parents: 13 diff changeset	810 Dtimer2_Start (1);
9a8a20d45be7 Timer2 for Nucleus RTOS ticks Mychaela Falconia <falcon@freecalypso.org> parents: 13 diff changeset	811
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	812 #endif /* (OP_L1_STANDALONE == 0) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	813
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	814 #endif /* #if (BOARD == 5) */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	815 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	816
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	817 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	818 * Init_Drivers
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	819 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	820 * Performs Drivers Initialization.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	821 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	822 void Init_Drivers(void)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	823 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	824 #if ABB_SEMAPHORE_PROTECTION
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	825 // Create the ABB semaphore
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	826 ABB_Sem_Create();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	827 #endif // SEMAPHORE_PROTECTION
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	828
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	829 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	830 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	831 * Initialize FFS invoking restore procedure by MPU-S
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	832 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	833 #if ((BOARD == 35) \|\| (BOARD == 46))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	834 GC_FfsRestore();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	835 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	836
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	837 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	838 * FFS main initialization.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	839 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	840
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	841 ffs_main_init();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	842
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	843
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	844 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	845 * Initialize Riviera manager and create tasks thanks to it.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	846 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	847 #if (CHIPSET!=15) \|\| (REMU==0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	848 rvf_init();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	849 rvm_init(); /* A-M-E-M-D-E-D! */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	850 create_tasks();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	851 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	852 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	853 * SIM Main Initialization.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	854 */
13 c07376e250c1 src/cs/system/main modules patched for passing link Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	855 #if 0 /* FC FFS editor */
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	856 SIM_Initialize ();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	857 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	858 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	859 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	860
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	861 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	862 * Init_Serial_Flows
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	863 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	864 * Performs Serialswitch + related serial data flows initialization.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	865 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	866 void Init_Serial_Flows (void)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	867 {
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	868 #if (OP_L1_STANDALONE == 0)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	869
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	870 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	871 * Initialize Serial Switch module.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	872 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	873 #if ((BOARD==35) \|\| (BOARD == 46))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	874 SER_InitSerialConfig (GC_GetSerialConfig());
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	875 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	876 SER_InitSerialConfig (&appli_ser_cfg_info);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	877 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	878 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	879 * Then Initialize the Serial Data Flows and the associated UARTs:
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	880 * - G2-3 Trace if GSM/GPRS Protocol Stack
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	881 * - AT-Cmd/Fax & Data Flow
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	882 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	883 * Layer1/Riviera Trace Flow and Bluetooth HCI Flow are initialized
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	884 * by the appropriate SW Entities.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	885 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	886 * G2-3 Trace => No more Used
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	887 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	888 SER_tr_Init(SER_PROTOCOL_STACK, TR_BAUD_38400, NULL);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	889
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	890 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	891 * Fax & Data / AT-Command Interpreter Serial Data Flow Initialization
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	892 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	893
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	894 #if ((BOARD != 35) && (BOARD != 46))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	895 (void) SER_fd_Initialize ();
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	896 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	897 #else /* OP_L1_STANDALONE */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	898
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	899 #if (TESTMODE \|\| (TRACE_TYPE==1) \|\| (TRACE_TYPE==2) \|\| (TRACE_TYPE==3) \|\| (TRACE_TYPE==6) \|\| (TRACE_TYPE==7))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	900 #if ((BOARD == 35) \|\| (BOARD == 46))
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	901 ser_cfg_info[UA_UART_0] = '0';
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	902 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	903 ser_cfg_info[UA_UART_0] = 'G';
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	904 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	905 #if (CHIPSET !=15)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	906 ser_cfg_info[UA_UART_1] = 'R'; // Riviear Demux on UART MODEM
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	907 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	908 ser_cfg_info[UA_UART_0] = 'R'; // Riviear Demux on UART MODEM
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	909 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	910
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	911 /* init Uart Modem */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	912 SER_InitSerialConfig (&appli_ser_cfg_info);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	913
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	914 #if TESTMODE \|\| (TRACE_TYPE == 1) \|\| (TRACE_TYPE == 7)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	915 SER_tr_Init (SER_LAYER_1, TR_BAUD_115200, rvt_activate_RX_HISR);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	916
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	917 rvt_register_id("OTHER",&trace_id,(RVT_CALLBACK_FUNC)NULL);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	918 #else
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	919 SER_tr_Init (SER_LAYER_1, TR_BAUD_38400, NULL);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	920 #endif
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	921
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	922 L1_trace_string(" \n\r");
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	923
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	924 #endif /* TRACE_TYPE */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	925
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	926 #endif /* OP_L1_STANDALONE */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	927 }
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	928
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	929 /*
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	930 * Init_Unmask_IT
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	931 *
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	932 * Unmask all used interrupts.
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	933 */
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	934 void Init_Unmask_IT (void)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	935 {
13 c07376e250c1 src/cs/system/main modules patched for passing link Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	936 #if 0 /* FC FFS editor */
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	937 IQ_Unmask(IQ_FRAME);
13 c07376e250c1 src/cs/system/main modules patched for passing link Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	938 #endif
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	939 IQ_Unmask(IQ_UART_IRDA_IT);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	940 IQ_Unmask(IQ_UART_IT);
13 c07376e250c1 src/cs/system/main modules patched for passing link Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	941 #if 0 /* FC FFS editor */
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	942 IQ_Unmask(IQ_ARMIO);
13 c07376e250c1 src/cs/system/main modules patched for passing link Mychaela Falconia <falcon@freecalypso.org> parents: 0 diff changeset	943 #endif
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	944 #if (L1_DYN_DSP_DWNLD == 1)
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	945 IQ_Unmask(IQ_API);
92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	946 #endif
17 9a8a20d45be7 Timer2 for Nucleus RTOS ticks Mychaela Falconia <falcon@freecalypso.org> parents: 13 diff changeset	947 /* FC FFS editor */
9a8a20d45be7 Timer2 for Nucleus RTOS ticks Mychaela Falconia <falcon@freecalypso.org> parents: 13 diff changeset	948 IQ_Unmask(IQ_TIM2);
0 92470e5d0b9e src: partial import from FC Selenite Mychaela Falconia <falcon@freecalypso.org> parents: diff changeset	949 }

FreeCalypso > hg > ffs-editor

annotate src/cs/system/main/init.c @ 27:cb3f6fe694e1 default tip