FreeCalypso > hg > ffs-editor
annotate src/cs/system/main/int.s @ 27:cb3f6fe694e1 default tip
README: document SE K2x0 addition
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Thu, 21 Dec 2023 21:44:43 +0000 |
parents | 92470e5d0b9e |
children |
rev | line source |
---|---|
0
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1 ;****************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2 ; TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 ; Property of Texas Instruments -- For Unrestricted Internal Use Only |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 ; Unauthorized reproduction and/or distribution is strictly prohibited. This |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 ; product is protected under copyright law and trade secret law as an |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 ; unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 ; rights reserved. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 ; Filename : int.s |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 ; Description : Nucleus initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 ; Project : Drivers |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
16 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
17 ; Author : proussel@ti.com Patrick Roussel. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
18 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
19 ; Version number : 1.3 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
20 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
21 ; Date and time : 07/23/98 15:36:07 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
22 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
23 ; Previous delta : 07/23/98 15:36:06 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
24 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
25 ; SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release1.5/mod/emu/EMU_MCMP/eva3_drivers/source/SCCS/s.int.s |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
26 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
27 ; Sccs Id (SID) : '@(#) int.s 1.3 07/23/98 15:36:07 ' |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
28 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
29 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
30 ;/* Copyright (c) 1993 - 1996 Accelerated Technology, Inc. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
31 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
32 ;/* PROPRIETARY RIGHTS of Accelerated Technology are involved in the */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
33 ;/* subject matter of this material. All manufacturing, reproduction, */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
34 ;/* use, and sales rights pertaining to this subject matter are governed */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
35 ;/* by the license agreement. The recipient of this software implicitly */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
36 ;/* accepts the terms of the license. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
37 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
38 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
39 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
40 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
41 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
42 ;/* FILE NAME VERSION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
43 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
44 ;/* int.s PLUS/THUMB/T 1.3 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
45 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
46 ;/* COMPONENT */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
47 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
48 ;/* IN - Initialization */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
49 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
50 ;/* DESCRIPTION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
51 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
52 ;/* This file contains the target processor dependent initialization */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
53 ;/* routines and data. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
54 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
55 ;/* AUTHOR */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
56 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
57 ;/* Barry Sellew, Accelerated Technology, Inc. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
58 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
59 ;/* DATA STRUCTURES */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
60 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
61 ;/* INT_Vectors Interrupt vector table */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
62 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
63 ;/* FUNCTIONS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
64 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
65 ;/* INT_Initialize Target initialization */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
66 ;/* INT_Vectors_Loaded Returns a NU_TRUE if all the */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
67 ;/* default vectors are loaded */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
68 ;/* INT_Setup_Vector Sets up an actual vector */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
69 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
70 ;/* DEPENDENCIES */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
71 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
72 ;/* nucleus.h System constants */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
73 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
74 ;/* HISTORY */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
75 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
76 ;/* NAME DATE REMARKS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
77 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
78 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
79 ;/* B. Sellew 01-22-1996 Verified version 1.0 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
80 ;/* B. Sellew 03-14-1996 Modified to use the ROM */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
81 ;/* initialization method, */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
82 ;/* resulting in version 1.1 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
83 ;/* B. Sellew 03-14-1996 Verified version 1.1 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
84 ;/* B. Sellew 02-06-1997 Created version 1.3 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
85 ;/* B. Sellew 02-06-1997 Verified version 1.3 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
86 ;/* M. Manning 06-02-1997 Added support for FIQ */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
87 ;/* interrupts. Bumped to 1.4 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
88 ;/* M. Manning 06-03-1997 Verified version 1.4 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
89 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
90 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
91 ;#define NU_SOURCE_FILE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
92 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
93 ;#include "nucleus.h" /* System constants */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
94 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
95 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
96 ;/* Define constants used in low-level initialization. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
97 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
98 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
99 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
100 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
101 .if LONG_JUMP >= 3 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
102 .global IND_CALL |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
103 .global _f_load_int_mem |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
104 .global _ResetVector |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
105 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
106 ; Initialization for variable S_D_Mem |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
107 .sect ".cinit" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
108 .align 4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
109 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
110 ; S_D_Mem is a UWORD32, See mem_load.c |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
111 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
112 .field 4,32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
113 .field _S_D_Mem+0,32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
114 .field 0,32 ; _S_D_Mem @ 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
115 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
116 .sect ".text" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
117 .global _S_D_Mem |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
118 _S_D_Mem: .usect "S_D_Mem",4,4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
119 .sym _S_D_Mem,_S_D_Mem,14,2,32 ; For debug only |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
120 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
121 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
122 ; Initialization for variable E_D_Mem |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
123 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
124 .sect ".cinit" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
125 .align 4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
126 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
127 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
128 ; E_D_Mem is a UWORD32, See mem_load.c |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
129 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
130 .field 4,32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
131 .field _E_D_Mem+0,32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
132 .field 0,32 ; _E_D_Mem @ 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
133 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
134 .sect ".text" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
135 .global _E_D_Mem |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
136 _E_D_Mem: .usect "E_D_Mem",4,4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
137 .sym _E_D_Mem,_E_D_Mem,14,2,32 ; For debug only |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
138 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
139 .endif ; (LONG_JUMP >= 3) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
140 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
141 .if CHIPSET == 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
142 .global _f_load_int_mem |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
143 .global _ResetVector |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
144 .global _ResetVectorTestMode ; CALYPSO PLUS TEST MODE - TO BE ERASED |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
145 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
146 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
147 LOCKOUT .equ 00C0h ; Interrupt lockout value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
148 LOCK_MSK .equ 00C0h ; Interrupt lockout mask value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
149 MODE_MASK .equ 001Fh ; Processor Mode Mask |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
150 SUP_MODE .equ 0013h ; Supervisor Mode (SVC) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
151 IRQ_MODE .equ 0012h ; Interrupt Mode (IRQ) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
152 FIQ_MODE .equ 0011h ; Fast Interrupt Mode (FIQ) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
153 ABORT_MODE .equ 0017h ; Abort Interrupt Mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
154 UNDEF_MODE .equ 001Bh ; Undefined Interrupt Mode (should not happen) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
155 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
156 IRQ_STACK_SIZE .equ 128 ; Number of bytes in IRQ stack (must be align(8)) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
157 ; Note that the IRQ interrupt, |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
158 ; by default, is managed by |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
159 ; Nucleus PLUS. Only several |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
160 ; words are actually used. The |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
161 ; system stack is what will |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
162 ; actually be used for Nuclues |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
163 ; PLUS managed IRQ interrupts. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
164 FIQ_STACK_SIZE .equ 512 ; Number of bytes in FIQ stack. (must be align(8)) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
165 ; This value is application |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
166 ; specific. By default, Nucleus |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
167 ; does not manage FIQ interrupts |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
168 ; and furthermore, leaves them |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
169 ; enabled virtually all the time. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
170 SYSTEM_SIZE .equ 1024 ; Define the system stack size (must be align(8)) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
171 TIMER_SIZE .equ 1024 ; Define timer HISR stack size (must be align(8)) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
172 TIMER_PRIORITY .equ 2 ; Timer HISR priority (values from |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
173 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
174 .if BOARD = 34 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
175 ; Name value offset type W/E W/S D/Cycles |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
176 CS0_CONFIG .short 0x044F ; 0 Flash 32 N F 2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
177 CS1_CONFIG .short 0x02CF ; 2 RAM 32 Y F 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
178 CS2_CONFIG .short 0x02CF ; 4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
179 CS3_CONFIG .short 0x02CF ; 6 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
180 CS7_CONFIG .short 0x02C0 ; 8 Int-RAM 32 Y 0 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
181 CS5_CONFIG .short 0x02CF ; A |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
182 CS6_CONFIG .short 0x02C0 ; C Int-RAM 32 Y 0 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
183 RHEA_CONFIG .short 0x002A ; E ARM -> RHEA/API adaptation |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
184 NUM_CS_REGS .equ 8 ; number of Chip Select Config regs to program |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
185 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
186 ; 0 to 2, where 0 is highest) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
187 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
188 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
189 ;/* End of low-level initialization constants. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
190 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
191 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
192 ;/* Define the initialization flag that indicates whether or not all of the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
193 ; default vectors have been loaded during initialization. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
194 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
195 ;INT INT_Loaded_Flag; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
196 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
197 .def _INT_Loaded_Flag |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
198 .bss _INT_Loaded_Flag, 4, 4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
199 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
200 ;/* Define the vector table */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
201 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
202 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
203 .if CHIPSET = 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
204 .sect ".start" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
205 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
206 .ref _INT_Bootloader_Start |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
207 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
208 _ResetVector: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
209 B _INT_Bootloader_Start |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
210 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
211 .sect ".indint" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
212 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
213 .def _IndirectVectorTable |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
214 _IndirectVectorTable: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
215 LDR PC, [PC, #0x14] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
216 LDR PC, [PC, #0x14] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
217 LDR PC, [PC, #0x14] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
218 LDR PC, [PC, #0x14] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
219 LDR PC, [PC, #0x14] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
220 LDR PC, [PC, #0x14] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
221 LDR PC, [PC, #0x14] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
222 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
223 .word INT_Undef_Inst |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
224 .word INT_Swi |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
225 .word INT_Abort_Prefetch |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
226 .word INT_Abort_Data |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
227 .word INT_Reserved |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
228 .word INT_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
229 .word INT_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
230 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
231 ; CALYPSO PLUS TEST MODE - TO BE ERASED |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
232 .sect ".intvecs" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
233 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
234 _ResetVectorTestMode: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
235 B _INT_Bootloader_Start |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
236 B INT_Undef_Inst |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
237 B INT_Swi |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
238 B INT_Abort_Prefetch |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
239 B INT_Abort_Data |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
240 B INT_Reserved |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
241 B INT_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
242 B INT_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
243 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
244 .else ; CHIPSET = 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
245 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
246 .sect ".intvecs" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
247 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
248 .if BOARD = 34 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
249 B _INT_Initialize |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
250 .elseif BOARD = 35 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
251 B _INT_Initialize |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
252 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
253 .ref _INT_Bootloader_Start |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
254 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
255 B _INT_Bootloader_Start |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
256 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
257 B INT_Undef_Inst |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
258 B INT_Swi |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
259 B INT_Abort_Prefetch |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
260 B INT_Abort_Data |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
261 B INT_Reserved |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
262 B Vect_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
263 .if WCP_PROF = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
264 .global _PR_StoreMonteCarloSample |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
265 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
266 ; Timing profiler using FIQ - Handle FIQ directly here |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
267 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
268 STMFD sp!,{R0-R4, LR} ; Save R0-R4 and LR on FIQ stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
269 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
270 MOV R0, LR ; Retrieve link register in R0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
271 BL _PR_StoreMonteCarloSample ; Store into ring buffer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
272 BL _IQ_FIQ_isr ; Ack FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
273 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
274 LDMFD sp!,{R0-R4, LR} ; Restore R0-R4 and LR from FIQ stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
275 SUBS PC, LR, #4 ; return from FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
276 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
277 B Vect_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
278 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
279 .endif ; CHIPSET = 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
280 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
281 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
282 ; .text |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
283 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
284 ; .ref cinit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
285 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
286 .sect ".inttext" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
287 .global cinit ; Linker symbol for C variable init. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
288 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
289 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
290 ; Address definitions in the section where they are used. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
291 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
292 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
293 ;/* Define the global system stack variable. This is setup by the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
294 ; initialization routine. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
295 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
296 ;extern VOID *TCD_System_Stack; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
297 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
298 .ref _TCD_System_Stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
299 .ref _TCT_System_Limit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
300 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
301 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
302 ;/* Define the global data structures that need to be initialized by this |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
303 ; routine. These structures are used to define the system timer management |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
304 ; HISR. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
305 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
306 ;extern VOID *TMD_HISR_Stack_Ptr; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
307 ;extern UNSIGNED TMD_HISR_Stack_Size; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
308 ;extern INT TMD_HISR_Priority; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
309 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
310 .ref _TMD_HISR_Stack_Ptr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
311 .ref _TMD_HISR_Stack_Size |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
312 .ref _TMD_HISR_Priority |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
313 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
314 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
315 ;/* Define extern function references. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
316 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
317 ;VOID INC_Initialize(VOID *first_available_memory); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
318 ;VOID TCT_Interrupt_Context_Save(VOID); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
319 ;VOID TCT_Interrupt_Context_Restore(VOID); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
320 ;VOID TCC_Dispatch_LISR(INT vector_number); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
321 ;VOID TMT_Timer_Interrupt(void); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
322 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
323 .ref _INC_Initialize |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
324 .ref _TCT_Interrupt_Context_Save |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
325 .ref _TCT_Interrupt_Context_Restore |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
326 .ref _TCC_Dispatch_LISR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
327 .ref _TMT_Timer_Interrupt |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
328 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
329 ;/* Application ISR */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
330 .ref _IQ_IRQ_isr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
331 .ref _IQ_FIQ_isr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
332 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
333 ; /* Reference pointers defined by the linker */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
334 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
335 .ref .bss |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
336 .ref end |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
337 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
338 .if C155_TARGET = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
339 .def INT_C155_Boot_Entry |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
340 INT_C155_Boot_Entry |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
341 B _INT_Initialize |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
342 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
343 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
344 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
345 ;/* Define indirect branching labels for the vector table */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
346 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
347 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
348 .def INT_Undef_Inst |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
349 INT_Undef_Inst |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
350 B arm_undefined ; Undefined |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
351 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
352 .def INT_Swi |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
353 INT_Swi |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
354 B arm_swi ; Software Generated |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
355 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
356 .def INT_Abort_Prefetch |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
357 INT_Abort_Prefetch |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
358 B arm_abort_prefetch ; Abort Prefetch |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
359 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
360 .def INT_Abort_Data |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
361 INT_Abort_Data |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
362 B arm_abort_data ; Abort Data |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
363 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
364 .def INT_Reserved |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
365 INT_Reserved |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
366 B arm_reserved ; Reserved |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
367 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
368 .def Vect_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
369 Vect_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
370 .if TI_NUC_MONITOR = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
371 B _INT_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
372 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
373 B INT_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
374 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
375 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
376 .def Vect_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
377 Vect_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
378 .if TI_PROFILER = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
379 B _INT_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
380 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
381 B INT_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
382 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
383 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
384 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
385 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
386 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
387 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
388 ;/* FUNCTION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
389 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
390 ;/* INT_Initialize */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
391 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
392 ;/* DESCRIPTION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
393 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
394 ;/* This function sets up the global system stack variable and */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
395 ;/* transfers control to the target independent initialization */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
396 ;/* function INC_Initialize. Responsibilities of this function */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
397 ;/* include the following: */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
398 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
399 ;/* - Setup necessary processor/system control registers */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
400 ;/* - Initialize the vector table */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
401 ;/* - Setup the system stack pointers */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
402 ;/* - Setup the timer interrupt */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
403 ;/* - Calculate the timer HISR stack and priority */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
404 ;/* - Calculate the first available memory address */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
405 ;/* - Transfer control to INC_Initialize to initialize all of */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
406 ;/* the system components. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
407 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
408 ;/* AUTHOR */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
409 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
410 ;/* Barry Sellew, Accelerated Technology, Inc. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
411 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
412 ;/* CALLED BY */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
413 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
414 ;/* none */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
415 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
416 ;/* CALLS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
417 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
418 ;/* INC_Initialize Common initialization */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
419 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
420 ;/* INPUTS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
421 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
422 ;/* None */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
423 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
424 ;/* OUTPUTS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
425 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
426 ;/* None */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
427 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
428 ;/* HISTORY */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
429 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
430 ;/* NAME DATE REMARKS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
431 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
432 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
433 ;/* B. Sellew 01-22-1996 Verified version 1.0 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
434 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
435 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
436 ;VOID INT_Initialize(void) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
437 ;{ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
438 .def _c_int00 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
439 _c_int00 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
440 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
441 .include "init.asm" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
442 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
443 addrCS0 .word 0xfffffb00 ; CS0 address space |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
444 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
445 .if BOARD = 34 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
446 CSConfigTable .long CS0_CONFIG |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
447 CS7_SIZE .equ 0x2000 ; 8 kB |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
448 CS7_ADDR .equ 0x03800000 ; initial address before toggling nIBOOT |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
449 SRAM_ADDR .equ 0x03000000 ; Internal SRAM start address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
450 SRAM_SIZE .equ 0x00040000 ; 256kB |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
451 EXTRA_CONF .short 0x013E ; Boot configuration |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
452 DEF_EXTRA_CONF .short 0x063E ; Default configuration |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
453 addrCS7 .word 0xFFFFFB08 ; CS7 configuration |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
454 addrExtraConf .word 0xFFFFFB10 ; Extra configuration |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
455 armio_in .word 0xFFFE4800 ; ARMIO_IN register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
456 armio_out .word 0xFFFE4802 ; ARMIO_OUT register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
457 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
458 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
459 .if BOARD = 40 | 41 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
460 EX_MPU_CONF_REG .word 0xFFFEF006 ; Extended MPU configuration register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
461 EX_FLASH_VALUE .short 0x0008 ; set bit to enable A22 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
462 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
463 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
464 .if CHIPSET = 4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
465 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
466 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
467 RHEA_CNTL_REG .word 0xFFFFF900 ; RHEA control register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
468 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
469 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
470 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
471 ; Use DPLL, Divide by 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
472 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
473 RHEA_CONTROL_RST .short 0xFF22 ; Set access factor in order to access the DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
474 ; independently of the ARM clock |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
475 .elseif CHIPSET = 6 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
476 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
477 CNTLCLK_26MHZ_SELECTOR .short 0x0040 ; VTCXO_26 selector |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
478 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
479 .elseif CHIPSET = 7 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
480 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
481 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
482 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
483 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
484 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
485 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
486 ; Use DPLL, Divide by 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
487 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
488 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
489 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
490 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
491 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
492 .elseif CHIPSET = 8 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
493 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
494 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
495 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
496 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
497 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
498 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
499 ; Use DPLL, Divide by 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
500 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
501 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
502 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
503 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
504 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
505 .elseif CHIPSET = 10 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
506 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
507 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
508 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
509 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
510 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
511 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
512 ; Use DPLL, Divide by 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
513 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
514 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
515 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
516 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
517 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
518 .elseif CHIPSET = 11 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
519 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
520 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
521 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
522 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
523 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
524 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
525 ; Use DPLL, Divide by 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
526 DPLL_CONTROL_RST .short 0x2002 ; Configure DPLL in default state |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
527 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
528 ENABLE_DU_MASK .short 0xF7FF ; Mask to Enable the DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
529 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
530 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
531 .elseif CHIPSET = 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
532 DBG_DMA_P2 .word 0xFFFEF02C ; DBG_DMA_P2 register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
533 CNTL_ARM_CLK_REG .word 0xFFFFFD00 ; CNTL_ARM_CLK register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
534 DPLL_CNTRL_REG .word 0xFFFF9800 ; DPLL control register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
535 EXTRA_CONTROL_REG .word 0xFFFFFB10 ; Extra Control register CONF address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
536 MPU_CTL_REG .word 0xFFFFFF08 ; MPU_CTL register address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
537 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
538 CNTL_ARM_CLK_RST .short 0x1081 ; Initialization of CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
539 ; Use DPLL, Divide by 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
540 DPLL_CONTROL_RST .short 0x2006 ; Configure DPLL in default state |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
541 DISABLE_DU_MASK .short 0x0800 ; Mask to Disable the DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
542 MPU_CTL_RST .short 0x0000 ; Reset value of MPU_CTL register - All protections disabled |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
543 DBG_DMA_P2_RST .short 0x0002 ; DBG_DMA_P2 register reset value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
544 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
545 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
546 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
547 c_cinit .long cinit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
548 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
549 .def _INT_Initialize |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
550 _INT_Initialize |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
551 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
552 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
553 ; Configuration of ARM clock and DPLL frequency |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
554 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
555 .if CHIPSET = 4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
556 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
557 ; Configure RHEA access factor in order to allow the access of DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
558 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
559 ldr r1,RHEA_CNTL_REG ; Load address of RHEA control register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
560 ldrh r2,RHEA_CONTROL_RST ; Load RHEA configuration value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
561 strh r2,[r1] ; Store DPLL reset value in RHEA control register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
562 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
563 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
564 ; Configure DPLL register with reset value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
565 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
566 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
567 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
568 strh r2,[r1] ; Store DPLL reset value in DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
569 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
570 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
571 ; Wait that DPLL goes in BYPASS mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
572 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
573 Wait_DPLL_Bypass |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
574 ldr r2,[r1] ; Load DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
575 and r2,r2,#1 ; Perform a mask on bit 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
576 cmp r2,#1 ; Compare DPLL lock bit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
577 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0') |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
578 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
579 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
580 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
581 ; generate ARM clock with division factor of 1. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
582 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
583 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
584 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
585 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
586 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
587 .elseif CHIPSET = 6 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
588 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
589 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
590 ; Set VTCXO_26MHZ bit to '1' in case of the VTCXO clock is 26MHz instead |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
591 ; of 13MHz. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
592 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
593 ldr r1, CNTL_ARM_CLK_REG ; Load CLKM base register address in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
594 ldrh r2, [r1,#2] ; Load contents of CNTL_CLK register in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
595 ldr r0, CNTLCLK_26MHZ_SELECTOR ; Load configuration of 26MHz selector |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
596 orr r0, r0, r2; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
597 strh r0, [r1,#2]; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
598 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
599 ; Wait a while until clock is stable (required for AvengerII) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
600 mov r0,#0x100 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
601 WaitAWhile1: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
602 sub r0, r0, #1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
603 cmp r0, #0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
604 bne WaitAWhile1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
605 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
606 .elseif CHIPSET = 7 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
607 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
608 ; Configure DPLL register with reset value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
609 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
610 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
611 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
612 strh r2,[r1] ; Store DPLL reset value in DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
613 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
614 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
615 ; Wait that DPLL goes in BYPASS mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
616 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
617 Wait_DPLL_Bypass |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
618 ldr r2,[r1] ; Load DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
619 and r2,r2,#1 ; Perform a mask on bit 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
620 cmp r2,#1 ; Compare DPLL lock bit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
621 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0') |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
622 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
623 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
624 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
625 ; generate ARM clock with division factor of 1. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
626 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
627 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
628 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
629 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
630 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
631 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
632 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0' |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
633 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
634 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
635 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
636 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
637 ldrh r0,[r1] ; Load Extra Control register CONF in r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
638 ;orr r0,r0,r2 ; Disable DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
639 and r0,r0,r2 ; Enable DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
640 strh r0,[r1] ; Store configuration in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
641 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
642 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
643 ; Disable all MPU protections |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
644 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
645 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
646 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
647 strh r2,[r1] ; Store reset value of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
648 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
649 .elseif CHIPSET = 8 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
650 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
651 ; Configure DPLL register with reset value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
652 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
653 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
654 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
655 strh r2,[r1] ; Store DPLL reset value in DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
656 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
657 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
658 ; Wait that DPLL goes in BYPASS mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
659 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
660 Wait_DPLL_Bypass |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
661 ldr r2,[r1] ; Load DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
662 and r2,r2,#1 ; Perform a mask on bit 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
663 cmp r2,#1 ; Compare DPLL lock bit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
664 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0') |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
665 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
666 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
667 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
668 ; generate ARM clock with division factor of 1. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
669 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
670 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
671 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
672 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
673 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
674 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
675 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0' |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
676 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
677 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
678 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
679 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
680 ldrh r0,[r1] ; Load Extra Control register CONF in r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
681 ;orr r0,r0,r2 ; Disable DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
682 and r0,r0,r2 ; Enable DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
683 strh r0,[r1] ; Store configuration in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
684 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
685 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
686 ; Disable all MPU protections |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
687 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
688 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
689 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
690 strh r2,[r1] ; Store reset value of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
691 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
692 .elseif CHIPSET = 10 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
693 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
694 ; Configure DPLL register with reset value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
695 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
696 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
697 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
698 strh r2,[r1] ; Store DPLL reset value in DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
699 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
700 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
701 ; Wait that DPLL goes in BYPASS mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
702 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
703 Wait_DPLL_Bypass |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
704 ldr r2,[r1] ; Load DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
705 and r2,r2,#1 ; Perform a mask on bit 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
706 cmp r2,#1 ; Compare DPLL lock bit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
707 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0') |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
708 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
709 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
710 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
711 ; generate ARM clock with division factor of 1. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
712 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
713 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
714 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
715 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
716 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
717 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
718 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0' |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
719 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
720 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
721 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
722 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
723 ldrh r0,[r1] ; Load Extra Control register CONF in r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
724 ;orr r0,r0,r2 ; Disable DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
725 and r0,r0,r2 ; Enable DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
726 strh r0,[r1] ; Store configuration in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
727 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
728 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
729 ; Disable all MPU protections |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
730 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
731 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
732 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
733 strh r2,[r1] ; Store reset value of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
734 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
735 .elseif CHIPSET = 11 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
736 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
737 ; Configure DPLL register with reset value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
738 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
739 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
740 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
741 strh r2,[r1] ; Store DPLL reset value in DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
742 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
743 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
744 ; Wait that DPLL goes in BYPASS mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
745 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
746 Wait_DPLL_Bypass |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
747 ldr r2,[r1] ; Load DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
748 and r2,r2,#1 ; Perform a mask on bit 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
749 cmp r2,#1 ; Compare DPLL lock bit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
750 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0') |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
751 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
752 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
753 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
754 ; generate ARM clock with division factor of 1. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
755 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
756 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
757 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
758 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
759 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
760 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
761 ; Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0' |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
762 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
763 ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
764 ;ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
765 ldrh r2,ENABLE_DU_MASK ; Load mask to write in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
766 ldrh r0,[r1] ; Load Extra Control register CONF in r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
767 ;orr r0,r0,r2 ; Disable DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
768 and r0,r0,r2 ; Enable DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
769 strh r0,[r1] ; Store configuration in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
770 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
771 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
772 ; Disable all MPU protections |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
773 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
774 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
775 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
776 strh r2,[r1] ; Store reset value of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
777 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
778 .elseif CHIPSET = 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
779 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
780 .if BOARD = 6 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
781 ; Configure DBG_DMA_P2 reg => GPO_2 output pin for EVA4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
782 ldr r1,DBG_DMA_P2 ; Load address of DBG_DMA_P2 register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
783 ldrh r2,DBG_DMA_P2_RST ; Load DBG_DMA_P2 reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
784 strh r2,[r1] ; Store reset value in register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
785 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
786 .endif ; BOARD = 6 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
787 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
788 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
789 ; Configure DPLL register with reset value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
790 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
791 ldr r1,DPLL_CNTRL_REG ; Load address of DPLL register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
792 ldrh r2,DPLL_CONTROL_RST ; Load DPLL reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
793 strh r2,[r1] ; Store DPLL reset value in DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
794 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
795 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
796 ; Wait that DPLL goes in BYPASS mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
797 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
798 Wait_DPLL_Bypass |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
799 ldr r2,[r1] ; Load DPLL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
800 and r2,r2,#1 ; Perform a mask on bit 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
801 cmp r2,#1 ; Compare DPLL lock bit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
802 beq Wait_DPLL_Bypass ; Wait Bypass mode (i.e. bit[0]='0') |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
803 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
804 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
805 ; Configure CNTL_ARM_CLK register with reset value: DPLL is used to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
806 ; generate ARM clock with division factor of 1. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
807 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
808 ldr r1,CNTL_ARM_CLK_REG ; Load address of CNTL_ARM_CLK register in R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
809 ldrh r2,CNTL_ARM_CLK_RST ; Load CNTL_ARM_CLK reset value in R2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
810 strh r2,[r1] ; Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
811 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
812 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
813 ; Disable the DU module by setting bit 11 to '1' |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
814 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
815 ; ldr r1,EXTRA_CONTROL_REG ; Load address of Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
816 ; ldrh r2,DISABLE_DU_MASK ; Load mask to write in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
817 ; ldrh r0,[r1] ; Load Extra Control register CONF in r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
818 ; orr r0,r0,r2 ; Disable DU module |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
819 ; strh r0,[r1] ; Store configuration in Extra Control register CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
820 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
821 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
822 ; Disable all MPU protections |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
823 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
824 ldr r1,MPU_CTL_REG ; Load address of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
825 ldrh r2,MPU_CTL_RST ; Load reset value of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
826 strh r2,[r1] ; Store reset value of MPU_CTL register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
827 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
828 .endif ; CHIPSET = 4 or 6 or 7 or 8 or 10 or 11 or 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
829 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
830 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
831 ; Wait-state configuration of external and internal memories |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
832 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
833 .if BOARD = 34 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
834 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
835 ; Wait states for Perseus - see IQ_InitWaitStates for details |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
836 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
837 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
838 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
839 mov r0, #NUM_CS_REGS ; number of chip selects to configure |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
840 ldr r1, addrCS0 ; first CS register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
841 ldr r2, CSConfigTable ; table of values to program |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
842 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
843 ConfigCS: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
844 ldrh r3,[r2] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
845 strh r3,[r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
846 add r1, r1, #2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
847 add r2, r2, #2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
848 sub r0, r0, #1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
849 cmp r0, #0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
850 bne ConfigCS |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
851 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
852 bl Ensure_external_access |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
853 bl Copy_code_into_CS7 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
854 bl Toggle_nIBoot |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
855 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
856 ; Wait a while - not quite sure why, but it is required for Avenger II |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
857 mov r0,#0x100 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
858 WaitAWhile2: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
859 sub r0, r0, #1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
860 cmp r0, #0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
861 bne WaitAWhile2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
862 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
863 bl Clear_Internal_SRAM ; This is required if the BSS is not in SRAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
864 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
865 .elseif BOARD = 35 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
866 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
867 ldr r1,addrCS0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
868 ldrh r2,CS0_MEM_REG ; CS0 initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
869 strh r2,[r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
870 ldrh r2,CS1_MEM_REG ; CS1 initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
871 strh r2,[r1,#0x2] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
872 ldrh r2,CS2_MEM_REG ; CS2 initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
873 strh r2,[r1,#0x4] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
874 ldrh r2,CS7_MEM_REG ; CS7 initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
875 strh r2,[r1,#0x8] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
876 ldrh r2,CS6_MEM_REG ; CS6 initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
877 strh r2,[r1,#0xC] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
878 mov r2,#API_ADAPT ; API-RHEA configuration |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
879 strh r2,[r1,#0xE] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
880 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
881 bl Ensure_external_access |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
882 bl Copy_code_into_CS7 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
883 bl Toggle_nIBoot |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
884 bl Clear_Internal_SRAM ; This is required if the BSS is not in SRAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
885 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
886 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
887 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
888 ldr r1,addrCS0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
889 .if CHIPSET != 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
890 ldrh r2,CS0_MEM_REG ; ROM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
891 strh r2,[r1] ; CS0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
892 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
893 ldrh r2,CS1_MEM_REG ; RAM Initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
894 strh r2,[r1,#2] ; CS1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
895 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
896 ldrh r2,CS2_MEM_REG ; RAM Initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
897 strh r2,[r1,#4] ; CS2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
898 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
899 ldrh r2,CS3_MEM_REG ; Parallel I/O on B-Sample |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
900 strh r2,[r1,#6] ; CS3 (unused on EVA4?) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
901 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
902 ldrh r2,CS4_MEM_REG ; Latch on B-Sample |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
903 strh r2,[r1,#0xa] ; CS4 (unused on EVA4) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
904 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
905 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
906 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
907 ldrh r2,CS0_MEM_REG ; CALYPSO PLUS TEST MODE - TO BE ERASED - FLASH Initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
908 strh r2,[r1,#0x0] ; CS0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
909 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
910 ldrh r2,CS5_MEM_REG ; FLASH Initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
911 strh r2,[r1,#0xA] ; CS5 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
912 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
913 ldrh r2,CS4_MEM_REG ; RAM Initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
914 strh r2,[r1,#0x8] ; CS4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
915 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
916 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
917 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
918 .if CHIPSET = 3 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
919 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
920 strh r2,[r1,#0xc] ; CS6 Internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
921 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
922 .elseif CHIPSET = 4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
923 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
924 strh r2,[r1,#0xc] ; CS6 Internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
925 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
926 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
927 strh r2,[r1,#0x8] ; CS7 Internal Boot RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
928 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
929 .elseif CHIPSET = 5 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
930 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
931 strh r2,[r1,#0xc] ; CS6 Internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
932 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
933 .elseif CHIPSET = 6 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
934 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
935 strh r2,[r1,#0xc] ; CS6 Internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
936 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
937 .elseif CHIPSET = 7 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
938 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
939 strh r2,[r1,#0xc] ; CS6 Internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
940 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
941 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
942 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
943 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
944 .elseif CHIPSET = 8 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
945 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
946 strh r2,[r1,#0xc] ; CS6 Internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
947 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
948 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
949 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
950 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
951 .elseif CHIPSET = 10 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
952 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
953 strh r2,[r1,#0xc] ; CS6 Internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
954 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
955 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
956 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
957 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
958 .elseif CHIPSET = 11 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
959 ldrh r2,CS6_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
960 strh r2,[r1,#0xc] ; CS6 Internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
961 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
962 ldrh r2,CS7_MEM_REG ; Internal SRAM initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
963 strh r2,[r1,#0x8] ; CS7 Internal Boot ROM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
964 .endif ; CHIPSET = 3 or 4 or 5 or 6 or 7 or 8 or 10 or 11 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
965 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
966 ldrh r2,CTL_MEM_REG ; API-RHEA configuration |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
967 strh r2,[r1,#0xe] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
968 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
969 .endif ; BOARD = 34 | 35 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
970 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
971 .if BOARD = 40 | 41 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
972 ; /* On D-Sample Board, use A22 mode (ADD(22) instead of CS4) to be able to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
973 ; address 8 Mbytes especially with CS0 (Flash) & CS3 (External Peripherals) */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
974 ldr r1,EX_MPU_CONF_REG |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
975 ldrh r2,[r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
976 ldr r0,EX_FLASH_VALUE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
977 orr r0, r0, r2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
978 strh r0,[r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
979 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
980 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
981 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
982 ; /* Insure that the processor is in supervisor mode. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
983 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
984 MRS a1,CPSR ; Pickup current CPSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
985 BIC a1,a1,#MODE_MASK ; Clear the mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
986 ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
987 ORR a1,a1,#LOCKOUT ; Insure IRQ and FIQ interrupts are |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
988 ; locked out |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
989 MSR CPSR,a1 ; Setup the new CPSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
990 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
991 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
992 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
993 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
994 ; REWORK OF .bss INITIALIZATION - start |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
995 ; Creation of INT_memset and INT_memcpy, respectively identical to memset and |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
996 ; memcpy from the rts library of compiler V2.51/2.54. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
997 ; They are used to make the initialization of the .bss section and the load |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
998 ; of the internal ram code not dependent to the 32-bit alignment. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
999 ; The old code used for the initialization and the load used a loop with |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1000 ; 4-byte increment, assuming the 32-bit alignment of the .bss section. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1001 ; This alignment is not necessary true. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1002 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1003 ; /* Clear the un-initialized global and static C data areas. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1004 ; Initialize the system stack pointer a first time to allow use of memset function |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1005 ; which needs stack. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1006 ; The system stack pointers will be fully initialized after having cleared |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1007 ; the BSS area. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1008 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1009 LDR a1,StackSegment ; Pickup the begining address from .cmd file |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1010 ; (is aligned on 8 byte boundary) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1011 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1012 MOV a2,#SYSTEM_SIZE ; Pickup system stack size |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1013 SUB a2,a2,#4 ; Subtract one word for first addr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1014 ADD a3,a1,a2 ; Build start of system stack area |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1015 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1016 MOV sp,a3 ; Setup initial stack pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1017 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1018 STMFD sp!,{a1-a4} ; Save a1-a4 registers to stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1019 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1020 LDR a1,BSS_Start ; Pickup the start of the BSS area |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1021 LDR a3,BSS_End ; Pickup the end of the BSS area |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1022 SUB a3,a3,a1 ; Calculate size of the BSS area |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1023 MOV a2,#0 ; Clear value in a2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1024 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1025 BL _INT_memset ; Clear the BSS area using memset function |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1026 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1027 .if LONG_JUMP >= 3 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1028 LDR a1,BSS_IntMem_Start ; Pickup the start of the BSS area |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1029 LDR a3,BSS_IntMem_End ; Pickup the end of the BSS area |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1030 SUB a3,a3,a1 ; Calculate size of the BSS area |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1031 MOV a2,#0 ; Clear value in a2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1032 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1033 BL _INT_memset ; Clear the BSS area using memset function |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1034 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1035 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1036 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1037 LDMFD sp!,{a1-a4} ; Restore a1-a4 registers from stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1038 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1039 ; REWORK OF .bss INITIALIZATION - end |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1040 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1041 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1042 ; /* Setup the vectors loaded flag to indicate to other routines in the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1043 ; system whether or not all of the default vectors have been loaded. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1044 ; If INT_Loaded_Flag is 1, all of the default vectors have been loaded. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1045 ; Otherwise, if INT_Loaded_Flag is 0, registering an LISR cause the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1046 ; default vector to be loaded. In the THUMB this variable is always |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1047 ; set to 1. All vectors must be setup by this function. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1048 ; INT_Loaded_Flag = 0; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1049 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1050 MOV a1,#1 ; All vectors are assumed loaded |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1051 LDR a2,Loaded_Flag ; Build address of loaded flag |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1052 STR a1,[a2,#0] ; Initialize loaded flag |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1053 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1054 ; /* Initialize the system stack pointers. This is done after the BSS is |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1055 ; cleared because the TCD_System_Stack pointer is a BSS variable! It is |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1056 ; assumed that the .cmd file is written to direct where these stacks should |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1057 ; be allocated and to align them on double word boundaries. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1058 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1059 LDR a1,StackSegment ; Pickup the begining address from .cmd file |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1060 ; (is aligned on 8 byte boundary) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1061 MOV a2,#SYSTEM_SIZE ; Pickup system stack size |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1062 SUB a2,a2,#4 ; Subtract one word for first addr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1063 ADD a3,a1,a2 ; Build start of system stack area |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1064 MOV v7,a1 ; Setup initial stack limit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1065 LDR a4,System_Limit ; Pickup system stack limit address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1066 STR v7,[a4, #0] ; Save stack limit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1067 MOV sp,a3 ; Setup initial stack pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1068 LDR a4,System_Stack ; Pickup system stack address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1069 STR sp,[a4, #0] ; Save stack pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1070 MOV a2,#IRQ_STACK_SIZE ; Pickup IRQ stack size in bytes |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1071 ADD a3,a3,a2 ; Allocate IRQ stack area |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1072 MRS a1,CPSR ; Pickup current CPSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1073 BIC a1,a1,#MODE_MASK ; Clear the mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1074 ORR a1,a1,#IRQ_MODE ; Set the IRQ mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1075 MSR CPSR,a1 ; Move to IRQ mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1076 MOV sp,a3 ; Setup IRQ stack pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1077 MOV a2,#FIQ_STACK_SIZE ; Pickup FIQ stack size in bytes |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1078 ADD a3,a3,a2 ; Allocate FIQ stack area |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1079 MRS a1,CPSR ; Pickup current CPSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1080 BIC a1,a1,#MODE_MASK ; Clear the mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1081 ORR a1,a1,#FIQ_MODE ; Set the FIQ mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1082 MSR CPSR,a1 ; Move to the FIQ mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1083 MOV sp,a3 ; Setup FIQ stack pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1084 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1085 MRS a1,CPSR ; Pickup current CPSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1086 BIC a1,a1,#MODE_MASK ; Clear the mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1087 ORR a1,a1,#ABORT_MODE ; Set the Abort mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1088 MSR CPSR,a1 ; Move to the Abort mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1089 LDR sp,Exception_Stack ; Setup Abort stack pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1090 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1091 MRS a1,CPSR ; Pickup current CPSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1092 BIC a1,a1,#MODE_MASK ; Clear the mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1093 ORR a1,a1,#UNDEF_MODE ; Set the Undefined mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1094 MSR CPSR,a1 ; Move to the Undefined mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1095 LDR sp,Exception_Stack ; Setup Undefined stack pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1096 ; (should never be used) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1097 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1098 ; go to Supervisor Mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1099 MRS a1,CPSR ; Pickup current CPSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1100 BIC a1,a1,#MODE_MASK ; Clear mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1101 ORR a1,a1,#SUP_MODE ; Set the supervisor mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1102 MSR CPSR,a1 ; All interrupt stacks are setup, |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1103 ; return to supervisor mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1104 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1105 ; /* Define the global data structures that need to be initialized by this |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1106 ; routine. These structures are used to define the system timer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1107 ; management HISR. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1108 ; TMD_HISR_Stack_Ptr = (VOID *) a3; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1109 ; TMD_HISR_Stack_Size = TIMER_SIZE; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1110 ; TMD_HISR_Priority = TIMER_PRIORITY; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1111 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1112 ; TMD_HISR_Stack_Ptr points at the top (the lowest address) of the allocated |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1113 ; area. The Timer HISR (called "SYSTEM H") and its related stack will be created |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1114 ; in TMI_Initialize(). The current stack pointer will be set at the bottom (the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1115 ; lowest address) of the expected area. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1116 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1117 LDR a4,HISR_Stack_Ptr ; Pickup variable's address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1118 ADD a3,a3,#4 ; Increment to next available word |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1119 STR a3,[a4, #0] ; Setup timer HISR stack pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1120 MOV a2,#TIMER_SIZE ; Pickup the timer HISR stack size |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1121 BIC a2,a2,#3 ; Insure word alignment |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1122 ADD a3,a3,a2 ; Allocate the timer HISR stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1123 ; from available memory |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1124 LDR a4,HISR_Stack_Size ; Pickup variable's address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1125 STR a2,[a4, #0] ; Setup timer HISR stack size |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1126 MOV a2,#TIMER_PRIORITY ; Pickup timer HISR priority (0-2) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1127 LDR a4,HISR_Priority ; Pickup variable's address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1128 STR a2,[a4, #0] ; Setup timer HISR priority |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1129 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1130 .if CHIPSET = 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1131 ; This sequence must be always done in order to download the interrupt |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1132 ; vector remapping |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1133 MOV V1, a3 ; Save a3 register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1134 BL _f_load_int_mem ; Download FLASH to Internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1135 MOV a3, V1 ; Restore a3 register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1136 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1137 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1138 .if LONG_JUMP >= 3 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1139 MOV V1, a3 ; Save a3 register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1140 BL _f_load_int_mem ; Download FLASH to Internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1141 MOV a3, V1 ; Restore a3 register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1142 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1143 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1144 .endif ; CHIPSET != 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1145 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1146 ; We now fill up the System, IRQ, FIQ and System Timer HISR stacks with 0xFE for |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1147 ; checking the status of the stacks later. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1148 ; inputs: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1149 ; a3 still has the bottom of all four stacks and is aligned. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1150 ; algorithm: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1151 ; We start from the top of all four stacks (*System_Limit), which is |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1152 ; necessarily aligned. We store 0xFEFEFEFE until we have filled the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1153 ; bottom of the fourth stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1154 ; outputs: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1155 ; memory has 0xFE on all four stacks: System, FIQ, IRQ and System Timer HISR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1156 ; a3 still has the bottom of all four stacks |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1157 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1158 LDR a2,System_Limit ; pickup system stack limit address |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1159 LDR a1,[a2] ; a1 = StackSegment |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1160 MOV a4,#0FEh ; use this and the next 7 instructons to set a4 = 0xFEFEFEFE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1161 STRB a4,[a1, #0] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1162 STRB a4,[a1, #1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1163 STRB a4,[a1, #2] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1164 STRB a4,[a1, #3] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1165 LDR a4,[a1],#4 ; stored first word, move to second |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1166 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1167 fill_stack: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1168 STR a4,[a1],#4 ; store a word and increment by four |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1169 CMP a1,a3 ; is this the last address? |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1170 BLT fill_stack ; if not, loop back |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1171 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1172 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1173 ; Perform auto-initialization. if cinit is -1, then there is none. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1174 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1175 LDR r0, c_cinit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1176 CMN r0, #1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1177 BLNE _auto_init |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1178 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1179 ; /* Call INC_Initialize with a pointer to the first available memory |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1180 ; address after the compiler's global data. This memory may be used |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1181 ; by the application. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1182 ; INC_Initialize(first_available_memory); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1183 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1184 MOV a1,a3 ; Pass the first available memory |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1185 B _INC_Initialize ; to high-level initialization |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1186 ;} |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1187 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1188 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1189 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1190 .if BOARD=35 | BOARD=34 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1191 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1192 ;/* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1193 ; * FUNCTION |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1194 ; * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1195 ; * Ensure_external_access |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1196 ; */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1197 Ensure_external_access: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1198 ;AI_ResetBit(4); // request shared mem clock |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1199 ldr r1, armio_out |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1200 ldrh r2, [r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1201 bic r2, r2, #0x10 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1202 strh r2, [r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1203 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1204 ;while(AI_ReadBit(5)!=1); // wait for acknowledge |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1205 ack: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1206 ldr r1, armio_in |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1207 ldrh r2, [r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1208 and r2, r2, #0x20 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1209 cmp r2, #0x20 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1210 bne ack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1211 bx lr ; Return to caller |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1212 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1213 ;/* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1214 ; * FUNCTION |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1215 ; * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1216 ; * Copy_code_into_CS7 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1217 ; */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1218 Copy_code_into_CS7: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1219 ldr r1, addrExtraConf |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1220 ldr r3, DEF_EXTRA_CONF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1221 strh r3, [r1] ; ensure CS7 selects internal memory |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1222 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1223 mov r0, #CS7_SIZE ; size of CS7 memory in bytes |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1224 mov r1, #CS7_ADDR ; destination |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1225 mov r2, #0 ; source |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1226 CopyIntCode: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1227 ldr r3,[r2] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1228 str r3,[r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1229 add r1, r1, #4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1230 add r2, r2, #4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1231 sub r0, r0, #4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1232 cmp r0, #0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1233 bne CopyIntCode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1234 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1235 ldr r1, addrCS7 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1236 ldr r2, [r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1237 bic r2, r2, #0x80 ; Write Enable OFF on CS7 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1238 strh r2, [r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1239 bx lr ; Return to caller |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1240 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1241 ;/* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1242 ; * FUNCTION |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1243 ; * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1244 ; * Toggle_nIBoot |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1245 ; */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1246 Toggle_nIBoot: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1247 ldr r1, addrExtraConf ; Address of Extra Conf Register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1248 ldr r3, EXTRA_CONF ; set CS7 at address zero |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1249 strh r3, [r1] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1250 bx lr ; Return to caller |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1251 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1252 ;/* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1253 ; * FUNCTION |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1254 ; * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1255 ; * Clear_Internal_SRAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1256 ; */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1257 Clear_Internal_SRAM: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1258 mov r0, #SRAM_ADDR ; r0 points to SRAM start |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1259 mov r1, #SRAM_SIZE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1260 add r1, r0, r1 ; r1 points to SRAM end |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1261 mov r2, #0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1262 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1263 ClearSram: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1264 str r2,[r0], #4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1265 cmp r0, r1 ; done? |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1266 bne ClearSram ; no - loop |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1267 bx lr ; Return to caller |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1268 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1269 .endif ; BOARD=34 | BOARD=35 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1270 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1271 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1272 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1273 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1274 ;/* FUNCTION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1275 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1276 ;/* INT_Vectors_Loaded */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1277 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1278 ;/* DESCRIPTION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1279 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1280 ;/* This function returns the flag that indicates whether or not */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1281 ;/* all the default vectors have been loaded. If it is false, */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1282 ;/* each LISR register also loads the ISR shell into the actual */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1283 ;/* vector table. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1284 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1285 ;/* AUTHOR */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1286 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1287 ;/* Barry Sellew, Accelerated Technology, Inc. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1288 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1289 ;/* CALLED BY */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1290 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1291 ;/* TCC_Register_LISR Register LISR for vector */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1292 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1293 ;/* CALLS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1294 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1295 ;/* None */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1296 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1297 ;/* INPUTS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1298 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1299 ;/* None */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1300 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1301 ;/* OUTPUTS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1302 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1303 ;/* None */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1304 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1305 ;/* HISTORY */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1306 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1307 ;/* NAME DATE REMARKS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1308 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1309 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1310 ;/* B. Sellew 01-22-1996 Verified version 1.0 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1311 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1312 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1313 ;INT INT_Vectors_Loaded(void) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1314 ;{ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1315 .def $INT_Vectors_Loaded |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1316 $INT_Vectors_Loaded ; Dual-state interworking veneer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1317 .state16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1318 BX pc |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1319 NOP |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1320 .state32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1321 B _INT_Vectors_Loaded |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1322 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1323 .def _INT_Vectors_Loaded |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1324 _INT_Vectors_Loaded |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1325 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1326 ; /* Just return the loaded vectors flag. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1327 ; return(INT_Loaded_Flag); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1328 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1329 MOV a1,#1 ; Always return TRUE since there |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1330 ; are really only two normal |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1331 ; vectors IRQ & FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1332 BX lr ; Return to caller |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1333 ;} |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1334 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1335 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1336 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1337 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1338 ;/* FUNCTION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1339 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1340 ;/* INT_Setup_Vector */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1341 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1342 ;/* DESCRIPTION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1343 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1344 ;/* This function sets up the specified vector with the new vector */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1345 ;/* value. The previous vector value is returned to the caller. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1346 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1347 ;/* AUTHOR */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1348 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1349 ;/* Barry Sellew, Accelerated Technology, Inc. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1350 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1351 ;/* CALLED BY */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1352 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1353 ;/* Application */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1354 ;/* TCC_Register_LISR Register LISR for vector */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1355 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1356 ;/* CALLS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1357 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1358 ;/* None */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1359 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1360 ;/* INPUTS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1361 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1362 ;/* vector Vector number to setup */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1363 ;/* new Pointer to new assembly */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1364 ;/* language ISR */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1365 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1366 ;/* OUTPUTS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1367 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1368 ;/* old vector contents */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1369 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1370 ;/* HISTORY */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1371 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1372 ;/* NAME DATE REMARKS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1373 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1374 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1375 ;/* B. Sellew 01-22-1996 Verified version 1.0 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1376 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1377 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1378 ;VOID *INT_Setup_Vector(INT vector, VOID *new) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1379 ;{ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1380 .def $INT_Setup_Vector |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1381 $INT_Setup_Vector ; Dual-state interworking veneer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1382 .state16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1383 BX pc |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1384 NOP |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1385 .state32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1386 B _INT_Setup_Vector |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1387 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1388 .def _INT_Setup_Vector |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1389 _INT_Setup_Vector |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1390 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1391 ;VOID *old_vector; /* Old interrupt vector */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1392 ;VOID **vector_table; /* Pointer to vector table */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1393 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1394 ; /* Calculate the starting address of the actual vector table. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1395 ; vector_table = (VOID **) 0; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1396 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1397 ; /* Pickup the old interrupt vector. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1398 ; old_vector = vector_table[vector]; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1399 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1400 ; /* Setup the new interrupt vector. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1401 ; vector_table[vector] = new; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1402 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1403 ; /* Return the old interrupt vector. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1404 ; return(old_vector); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1405 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1406 MOV a1,#0 ; This routine is not applicable to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1407 ; THUMB, return a NULL pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1408 BX lr ; Return to caller |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1409 ;} |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1410 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1411 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1412 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1413 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1414 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1415 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1416 ;/* FUNCTIONS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1417 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1418 ;/* INT_EnableIRQ, INT_DisableIRQ */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1419 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1420 ;/* DESCRIPTION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1421 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1422 ;/* This function enable/disable IRQ/FIQ in current mode */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1423 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1424 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1425 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1426 .global $INT_EnableIRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1427 $INT_EnableIRQ: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1428 .state16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1429 BX pc |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1430 nop |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1431 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1432 .state32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1433 MRS a1, CPSR ; read current PSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1434 BIC a1,a1,#MODE_MASK ; remove all mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1435 ORR a1,a1,#IRQ_MODE ; retrieve desired mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1436 MSR CPSR,a1 ; IRQ mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1437 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1438 MRS a1, CPSR ; read current PSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1439 BIC a1,a1,#LOCKOUT ; interrupt lockout value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1440 MSR CPSR,a1 ; Lockout interrupts |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1441 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1442 BIC a1,a1,#MODE_MASK ; remove all mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1443 ORR a1,a1,#SUP_MODE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1444 MSR CPSR,a1 ; Lockout interrupts |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1445 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1446 add a1, pc, #1 ; back to Thumb mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1447 bx a1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1448 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1449 .state16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1450 BX lr ; Return to caller |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1451 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1452 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1453 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1454 .global $INT_DisableIRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1455 $INT_DisableIRQ: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1456 .state16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1457 BX pc |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1458 nop |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1459 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1460 .state32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1461 MRS a1, CPSR ; read current PSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1462 BIC a1,a1,#MODE_MASK ; remove all mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1463 ORR a1,a1,#IRQ_MODE ; retrieve desired mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1464 MSR CPSR,a1 ; IRQ mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1465 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1466 MRS a1, CPSR ; read current PSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1467 ORR a1,a1,#LOCKOUT ; Build interrupt lockout value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1468 MSR CPSR,a1 ; Lockout interrupts |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1469 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1470 BIC a1,a1,#MODE_MASK ; remove all mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1471 ORR a1,a1,#SUP_MODE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1472 MSR CPSR,a1 ; Lockout interrupts |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1473 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1474 add a1, pc, #1 ; back to Thumb mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1475 bx a1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1476 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1477 .state16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1478 BX lr ; Return to caller |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1479 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1480 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1481 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1482 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1483 ;/* FUNCTION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1484 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1485 ;/* INT_Retrieve_Shell */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1486 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1487 ;/* DESCRIPTION */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1488 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1489 ;/* This function retrieves the pointer to the shell interrupt */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1490 ;/* service routine. The shell interrupt service routine calls */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1491 ;/* the LISR dispatch routine. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1492 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1493 ;/* AUTHOR */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1494 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1495 ;/* Barry Sellew, Accelerated Technology, Inc. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1496 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1497 ;/* CALLED BY */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1498 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1499 ;/* TCC_Register_LISR Register LISR for vector */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1500 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1501 ;/* CALLS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1502 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1503 ;/* None */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1504 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1505 ;/* INPUTS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1506 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1507 ;/* vector Vector number to setup */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1508 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1509 ;/* OUTPUTS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1510 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1511 ;/* shell pointer */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1512 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1513 ;/* HISTORY */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1514 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1515 ;/* NAME DATE REMARKS */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1516 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1517 ;/* B. Sellew 01-19-1996 Created initial version 1.0 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1518 ;/* B. Sellew 01-22-1996 Verified version 1.0 */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1519 ;/* */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1520 ;/*************************************************************************/ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1521 ;VOID *INT_Retrieve_Shell(INT vector) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1522 ;{ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1523 .def $INT_Retrieve_Shell |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1524 $INT_Retrieve_Shell ; Dual-state interworking veneer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1525 .state16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1526 BX pc |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1527 NOP |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1528 .state32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1529 B _INT_Retrieve_Shell |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1530 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1531 .def _INT_Retrieve_Shell |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1532 _INT_Retrieve_Shell |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1533 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1534 ; /* Return the LISR Shell interrupt routine. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1535 ; return(INT_Vectors[vector]); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1536 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1537 MOV a1,#0 ; This routine is not applicable to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1538 ; THUMB, return a NULL pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1539 BX lr ; Return to caller |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1540 ;} |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1541 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1542 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1543 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1544 ;/* The following section contains default interrupt handlers. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1545 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1546 .if TI_NUC_MONITOR = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1547 ; define a new section to be mapped independently |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1548 .sect ".irqtext" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1549 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1550 .def _INT_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1551 .global _INT_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1552 _INT_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1553 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1554 .def INT_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1555 INT_IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1556 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1557 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1558 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1559 ; /* Call Prepare for IRQ interrupt processing by calling |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1560 ; TCT_Interrupt_Context_Save. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1561 STMDB sp!,{a1-a4} ; Save a1-a4 on temporary IRQ stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1562 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1563 ;BUG correction 1st part ------------------- |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1564 ;It looks like there is an issue with ARM7 IRQ masking in the CPSR register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1565 ;which leads to crashes in Nucleus+ scheduler. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1566 ;Basically the code below (correct as LOCKOUT = 0xC0) is used in many places by N+ but do not |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1567 ;prevent from having an interrupt after the execution of the third line (I mean execution, not |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1568 ;fetch). |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1569 ; MRS a1,CPSR ; Pickup current CPSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1570 ; ORR a1,a1,#LOCKOUT ; Build interrupt lockout value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1571 ; MSR CPSR,a1 ; Lockout interrupts |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1572 ; * IRQ INTERRUPT ! * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1573 ; Next instructions... |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1574 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1575 ;SW workaround: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1576 ;When a task is interrupted at this point an interrupted context is stored on its task and will |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1577 ;be resumed later on at the next instruction but to make a long story short it leads to some |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1578 ;problem as the OS does not expect to be interrupted there. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1579 ;Further testing tends to show that the CPSR *seems* to be loaded with the proper masking value |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1580 ;but that the IRQ is still triggered (has been hardwarewise requested during the instruction |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1581 ;exectution by the ARM7 core?) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1582 MRS a1,spsr ; check for the IRQ bug: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1583 TST a1,#080h ; if the I - flag is set, |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1584 BNE IRQBUG ; then postpone execution of this IRQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1585 ;Bug correction 1st part end --------------- |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1586 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1587 SUB a4,lr,#4 ; Save IRQ's lr (return address) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1588 BL _TCT_Interrupt_Context_Save ; Call context save routine |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1589 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1590 .if TI_NUC_MONITOR = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1591 ; Log the IRQ call entry |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1592 .global _ti_nuc_monitor_LISR_log |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1593 BL _ti_nuc_monitor_LISR_log ; Call the LISR Log function. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1594 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1595 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1596 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1597 ; /* On actuall hardware, a register must be examined to see what the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1598 ; IRQ interrupt was caused from. For default processing, the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1599 ; timer is the only IRQ interrupt source. It is assumed that further |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1600 ; timer interrupts are disabled upon this call. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1601 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1602 BL _IQ_IRQ_isr ; Call int. service routine |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1603 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1604 .if TI_NUC_MONITOR = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1605 ; Log the IRQ exit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1606 .global _ti_nuc_monitor_LISR_log_end |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1607 BL _ti_nuc_monitor_LISR_log_end ; Call the LISR end function. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1608 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1609 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1610 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1611 ; /* IRQ interrupt processing is complete. Restore context- Never |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1612 ; returns! */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1613 B _TCT_Interrupt_Context_Restore |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1614 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1615 ;BUG correction 2nd part ------------------ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1616 IRQBUG: LDMFD sp!,{a1-a4} ; return from interrupt |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1617 SUBS pc,r14,#4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1618 ;BUG correction 2nd part end -------------- |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1619 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1620 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1621 .if TI_NUC_MONITOR = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1622 .sect ".inttext" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1623 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1624 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1625 .if TI_PROFILER = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1626 ; define a new section to be mapped independently |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1627 .sect ".fiqtext" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1628 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1629 .def _INT_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1630 .global _INT_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1631 _INT_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1632 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1633 .def INT_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1634 INT_FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1635 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1636 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1637 .if TI_PROFILER = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1638 ; Warning : |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1639 ; This code has been added for profiliing purpose. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1640 ; It removes all other FIQ. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1641 .global _ti_profiler_handler |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1642 ; Timing profiler using FIQ - Handle FIQ directly here |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1643 STMFD sp!,{R0-R4, LR} ; Save R0-R4 and LR on FIQ stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1644 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1645 MOV R0, LR ; Retrieve link register in R0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1646 BL _ti_profiler_handler ; Store into buffer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1647 BL _IQ_FIQ_isr ; Call the FIQ ISR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1648 LDMFD sp!,{R0-R4, LR} ; Restore R0-R4 and LR from FIQ stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1649 SUBS PC, LR, #4 ; return from FIQ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1650 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1651 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1652 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1653 ; /* Call Prepare for FIQ interrupt processing by calling |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1654 ; TCT_Interrupt_Context_Save. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1655 STMDB sp!,{a1-a4} ; Save a1-a4 on temporary FIQ stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1656 SUB a4,lr,#4 ; Save FIQ's lr (return address) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1657 BL _TCT_Interrupt_Context_Save ; Call context save routine |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1658 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1659 ; /* On actuall hardware, a register must be examined to see what the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1660 ; FIQ interrupt was caused from. For default processing, the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1661 ; test is the only FIQ interrupt source. */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1662 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1663 ; /* Replace this with a call to your own ISR */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1664 BL _IQ_FIQ_isr ; Call the FIQ ISR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1665 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1666 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1667 ; /* FIQ interrupt processing is complete. Restore context- Never |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1668 ; returns! */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1669 B _TCT_Interrupt_Context_Restore |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1670 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1671 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1672 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1673 .if TI_PROFILER = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1674 .sect ".inttext" |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1675 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1676 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1677 ;*************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1678 ;* CONSTANT TABLE * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1679 ;*************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1680 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1681 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1682 ; /* Define all the global addresses used in this section */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1683 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1684 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1685 ; internal/external RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1686 .if CHIPSET = 3 | CHIPSET = 5 | CHIPSET = 6 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1687 RAM_SIZE .equ 0x40000 ; size (in bytes) of internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1688 RAM_LOW .equ 0x3000000 ; first address of internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1689 .elseif CHIPSET = 4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1690 RAM_SIZE .equ 0x40000 ; size (in bytes) of internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1691 RAM_LOW .equ 0x800000 ; first address of internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1692 .elseif CHIPSET = 7 | CHIPSET = 8 | CHIPSET = 10 | CHIPSET = 11 | CHIPSET = 12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1693 .if L1_GPRS = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1694 RAM_SIZE .equ 0x200000 ; size (in bytes) of external RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1695 RAM_LOW .equ 0x1000000 ; first address of external RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1696 .else ; GSM ONLY |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1697 RAM_SIZE .equ 0x80000 ; size (in bytes) of internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1698 RAM_LOW .equ 0x800000 ; first address of internal RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1699 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1700 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1701 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1702 RAM_HIGH .equ RAM_LOW + RAM_SIZE ; first address after internal/external RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1703 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1704 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1705 .global exception_stack ; top address of SVC mode stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1706 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1707 .global _xdump_buffer ; first address of state data |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1708 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1709 .global stack_segment ; address of the top of the system stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1710 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1711 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1712 ; /* Define exception functions */ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1713 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1714 .ref _dar_exception |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1715 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1716 XDUMP_STACK_SIZE .equ 20 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1717 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1718 ; layout of xdump buffer: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1719 ; struct xdump_s { |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1720 ; long registers[16] // svc mode registers |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1721 ; long cpsr // svc mode CPSR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1722 ; long exception // magic word + index of vector taken |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1723 ; long stack[20] // bottom 20 words of usr mode stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1724 ; } |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1725 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1726 arm_undefined: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1727 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1728 mov r11,#1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1729 b save_regs |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1730 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1731 arm_swi: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1732 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1733 mov r11,#2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1734 b save_regs |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1735 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1736 arm_abort_prefetch: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1737 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1738 mov r11,#3 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1739 b save_regs |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1740 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1741 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1742 arm_abort_data: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1743 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1744 mov r11,#4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1745 b save_regs |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1746 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1747 arm_reserved: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1748 ldr r13,Exception_Stack ; should never happen, but mode is unknown at this point |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1749 stmfd r13!,{r11,r12} ; store r12 for Xdump_buffer pointer, r11 for index |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1750 mov r11,#5 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1751 b save_regs |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1752 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1753 save_regs: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1754 ldr r12,Xdump_buffer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1755 str r14,[r12,#4*15] ; save r14_abt (original PC) into r15 slot |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1756 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1757 stmia r12,{r0-r10} ; save unbanked registers (except r11 and r12) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1758 ldmfd r13!,{r0,r1} ; get original r11 and r12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1759 str r0,[r12,#4*11] ; save original r11 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1760 str r1,[r12,#4*12] ; save original r12 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1761 mrs r0,spsr ; get original psr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1762 str r0,[r12,#4*16] ; save original cpsr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1763 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1764 mrs r1,cpsr ; save mode psr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1765 bic r2,r1,#0x1f ; psr with mode bits cleared |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1766 and r0,r0,#0x1f ; get original mode bits |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1767 add r0,r0,r2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1768 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1769 msr cpsr,r0 ; move to pre-exception mode |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1770 str r13,[r12,#4*13] ; save original SP |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1771 str r14,[r12,#4*14] ; save original LR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1772 msr cpsr,r1 ; restore mode psr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1773 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1774 ; r11 has original index |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1775 orr r10,r11,#0xDE<<24; r10 = 0xDEAD0000 + index of vector taken |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1776 orr r10,r10,#0xAD<<16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1777 str r10,[r12,#4*17] ; save magic + index |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1778 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1779 mov r0,r11 ; put index into 1st argument |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1780 b _dar_exception |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1781 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1782 .global $exception ; export function |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1783 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1784 $exception: ; Veneer function |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1785 .ref _exception |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1786 .state16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1787 adr r0,_exception |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1788 bx r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1789 .align |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1790 .state32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1791 .def _exception |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1792 _exception: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1793 ldr r12,Xdump_buffer ; redundant unless _exception is called |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1794 ldr r11,[r12,#4*13] ; get svc mode r13 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1795 add r12,r12,#4*18 ; base of stack buffer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1796 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1797 ; check if svc r13(sp) is within internal/external RAM. It *could* be invalid. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1798 ; we boldly assume stack is only within internal RAM except for GPRS build on |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1799 ; Calypso chipset : stack is within external RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1800 .if CHIPSET = 7 | CHIPSET = 8 | CHIPSET = 10 | CHIPSET = 11 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1801 .if L1_GPRS = 1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1802 ; if GPRS, check for internal RAM as well as 2Mbytes of external RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1803 cmp r11,#0x800000 ; INTERNAL RAM_LOW |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1804 blt nostack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1805 mov r0, #0x880000 ; INTERNAL RAM_HIGH |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1806 sub r0,r0,#XDUMP_STACK_SIZE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1807 cmp r11,r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1808 blt stack_range |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1809 ; was not less than 0x880000, so check for external RAM |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1810 cmp r11,#RAM_LOW |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1811 blt nostack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1812 mov r0,#RAM_HIGH |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1813 sub r0,r0,#XDUMP_STACK_SIZE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1814 cmp r11,r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1815 bge nostack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1816 .else ; GSM ONLY |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1817 cmp r11,#RAM_LOW |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1818 blt nostack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1819 mov r0,#RAM_HIGH |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1820 sub r0,r0,#XDUMP_STACK_SIZE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1821 cmp r11,r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1822 bge nostack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1823 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1824 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1825 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1826 stack_range: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1827 ldmfd r11!,{r0-r9} ; copy ten stack words.. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1828 stmia r12!,{r0-r9} |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1829 ldmfd r11!,{r0-r9} ; copy ten stack words.. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1830 stmia r12!,{r0-r9} |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1831 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1832 nostack: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1833 STACKS .equ SYSTEM_SIZE + IRQ_STACK_SIZE + FIQ_STACK_SIZE + TIMER_SIZE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1834 .ref _dar_reset |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1835 ; we're finished saving all state. Now execute C code for more flexibility. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1836 ; set up a stack for this C call |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1837 LDR a1,StackSegment ; Pickup the begining address from .cmd file |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1838 ; (is aligned on 8 byte boundary) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1839 MOV a2,#STACKS ; Pickup all stacks size |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1840 ADD a2,a2,#0x80 ; Add 128 to get past all used data |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1841 ADD a3,a1,a2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1842 MOV sp,a3 ; Setup exception stack pointer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1843 b _dar_reset |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1844 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1845 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1846 BSS_Start |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1847 .word .bss |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1848 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1849 BSS_End |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1850 .word end |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1851 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1852 .if LONG_JUMP >= 3 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1853 .align 4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1854 BSS_IntMem_Start: .field _S_D_Mem,32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1855 .align 4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1856 BSS_IntMem_End: .field _E_D_Mem,32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1857 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1858 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1859 StackSegment |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1860 .word stack_segment |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1861 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1862 Loaded_Flag |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1863 .word _INT_Loaded_Flag |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1864 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1865 System_Limit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1866 .word _TCT_System_Limit |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1867 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1868 System_Stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1869 .word _TCD_System_Stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1870 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1871 HISR_Stack_Ptr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1872 .word _TMD_HISR_Stack_Ptr |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1873 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1874 HISR_Stack_Size |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1875 .word _TMD_HISR_Stack_Size |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1876 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1877 HISR_Priority |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1878 .word _TMD_HISR_Priority |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1879 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1880 Exception_Stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1881 .word exception_stack |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1882 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1883 Xdump_buffer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1884 .word _xdump_buffer |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1885 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1886 ; The following code is pulled from rts.src, which is part of the |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1887 ; TI tools installation. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1888 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1889 ;*************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1890 ;* PROCESS INITIALIZATION TABLE. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1891 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1892 ;* THE TABLE CONSISTS OF A SEQUENCE OF RECORDS OF THE FOLLOWING FORMAT: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1893 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1894 ;* .word <length of data (bytes)> |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1895 ;* .word <address of variable to initialize> |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1896 ;* .word <data> |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1897 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1898 ;* THE INITIALIZATION TABLE IS TERMINATED WITH A ZERO LENGTH RECORD. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1899 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1900 ;*************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1901 ;****auto_init(register int *table) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1902 ;****{ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1903 ;**** register int length; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1904 ;**** register int *addr; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1905 ;**** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1906 ;**** while (length = *table++) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1907 ;**** { |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1908 ;**** addr = (int *)*table++; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1909 ;**** while (length) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1910 ;**** { |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1911 ;**** if (length > 3) |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1912 ;**** { |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1913 ;**** *addr++ = *table++; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1914 ;**** length -= 4; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1915 ;**** } |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1916 ;**** else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1917 ;**** { |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1918 ;**** *(char *)addr++ = *(char *)table++; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1919 ;**** length--; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1920 ;**** } |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1921 ;**** } |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1922 ;**** } |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1923 ;****} |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1924 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1925 tbl_addr: .set R0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1926 var_addr: .set R1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1927 length: .set R3 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1928 data: .set R4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1929 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1930 _auto_init: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1931 B rec_chk |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1932 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1933 record: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1934 ;*------------------------------------------------------ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1935 ;* PROCESS AN INITIALIZATION RECORD |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1936 ;*------------------------------------------------------ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1937 LDR var_addr, [tbl_addr], #4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1938 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1939 copy: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1940 ;*------------------------------------------------------ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1941 ;* COPY THE INITIALIZATION DATA |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1942 ;*------------------------------------------------------ |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1943 CMP length, #3 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1944 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1945 LDRHI data, [tbl_addr], #4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1946 STRHI data, [var_addr], #4 ; COPY A WORD OF DATA |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1947 SUBHI length, length, #4 ; OR ... |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1948 LDRLSB data, [tbl_addr], #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1949 STRLSB data, [var_addr], #1 ; COPY A BYTE OF DATA |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1950 SUBLS length, length, #1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1951 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1952 CMP length, #0 ; CONTINUE TO COPY IF |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1953 BNE copy ; LENGTH IS NONZERO |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1954 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1955 ANDS length, tbl_addr, #0x3 ; MAKE SURE THE ADDRESS |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1956 RSBNE length, length, #0x4 ; IS WORD ALIGNED |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1957 ADDNE tbl_addr, tbl_addr, length ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1958 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1959 rec_chk:LDR length, [tbl_addr], #4 ; PROCESS NEXT |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1960 CMP length, #0 ; RECORD IF LENGTH IS |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1961 BNE record ; NONZERO |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1962 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1963 MOV PC, LR |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1964 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1965 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1966 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1967 ; Creation of INT_memset and INT_memcpy, respectively identical to memset and |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1968 ; memcpy from the rts library of compiler 2.51/2.54. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1969 ; They are used to make the initialization of the .bss section and the load |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1970 ; of the internal ram code not dependent to the 32-bit alignment. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1971 ; The old code used for the initialization and the load used a loop with |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1972 ; 4-byte increment, assuming the 32-bit alignment of the .bss section. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1973 ; This alignment is not necessary true. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1974 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1975 ;****************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1976 ;* INT_memset - INITIALIZE MEMORY WITH VALUE * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1977 ;****************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1978 ;* MEMSET32.ASM - 32 BIT STATE - v2.51 * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1979 ;* Copyright (c) 1996-2003 Texas Instruments Incorporated * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1980 ;****************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1981 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1982 ;**************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1983 ;* INT_memset - INITIALIZE MEMORY WITH VALUE. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1984 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1985 ;* Same memset defined in rts.src. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1986 ;* Used in INT_Initialize to clear bss area. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1987 ;* Used in f_load_int_mem() function to clear internal memory space used |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1988 ;* for data and code. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1989 ;* The memset function defined in rts library is loaded into internal memory, |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1990 ;* then, it can not be used in either INT_Initialize, or f_load_int_mem(). |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1991 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1992 ;* C Prototype : void *INT_memset(void *s, int c, size_t n); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1993 ;* C++ Prototype : void *std::INT_memset(void *s, int c, std::size_t n); |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1994 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1995 ;**************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1996 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1997 ;* o DESTINATION LOCATION IS IN r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1998 ;* o INITIALIZATION VALUE IS IN r1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1999 ;* o NUMBER OF BYTES TO INITIALIZE IS IN r2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2000 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2001 ;* o ORIGINAL DESTINATION LOCATION RETURNED IN r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2002 ;**************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2003 .state32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2004 .def _INT_memset |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2005 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2006 _INT_memset: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2007 STMFD SP!, {R0, LR} ; save R0 also since original dst |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2008 ; address is returned. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2009 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2010 TST R0, #3 ; check for word alignment |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2011 BEQ _word_aligned |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2012 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2013 CMP R2, #0 ; set bytes until there are no more |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2014 ; to set or until address is aligned |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2015 _unaligned_loop: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2016 STRHIB R1, [R0], #1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2017 SUBHIS R2, R2, #1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2018 TSTHI R0, #3 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2019 BNE _unaligned_loop |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2020 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2021 CMP R2, #0 ; return early if no more bytes |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2022 LDMEQFD SP!, {R0, PC} ; to set. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2023 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2024 _word_aligned: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2025 AND R1, R1, #255 ; be safe since prototype has value as |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2026 ; as an int rather than unsigned char |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2027 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2028 ORR R1, R1, R1, LSL #8 ; replicate byte in 2nd byte of |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2029 ; register |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2030 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2031 CMP R2,#4 ; are at least 4 bytes being set |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2032 BCC _INT_memset3 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2033 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2034 ORR R1, R1, R1, LSL #16 ; replicate byte in upper 2 bytes |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2035 ; of register. note that each of |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2036 ; the bottom 2 bytes already contain |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2037 ; the byte value from above. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2038 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2039 CMP R2,#8 ; are at least 8 bytes being set |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2040 BCC _INT_memset7 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2041 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2042 MOV LR,R1 ; copy bits into another register so |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2043 ; 8 bytes at a time can be copied. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2044 ; use LR since it is already being |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2045 ; saved/restored. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2046 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2047 CMP R2,#16 ; are at least 16 bytes being set |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2048 BCC _INT_memset15 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2049 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2050 STMFD SP!, {R4} ; save regs needed by 16 byte copies |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2051 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2052 MOV R4, R1 ; copy bits into 2 other registers so |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2053 MOV R12, R1 ; 16 bytes at a time can be copied |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2054 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2055 SUB R3, R2, #15 ; set up loop count |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2056 AND R2, R2, #15 ; determine number of bytes to set |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2057 ; after setting 16 byte blocks |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2058 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2059 _INT_memset16_loop: ; set blocks of 16 bytes |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2060 STMIA R0!, {R1, R4, R12, LR} |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2061 SUBS R3, R3, #16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2062 BHI _INT_memset16_loop |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2063 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2064 LDMFD SP!, {R4} ; resotre regs used by 16 byte copies |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2065 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2066 _INT_memset15: ; may still be as many as 15 bytes to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2067 ; set. the address in R0 is guaranteed |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2068 ; to be word aligned here. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2069 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2070 TST R2, #8 ; are at least 8 bytes being set |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2071 STMNEIA R0!, {R1, LR} |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2072 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2073 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2074 _INT_memset7: ; may still be as many as 7 bytes to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2075 ; set. the address in R0 is guaranteed |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2076 ; to be word aligned here. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2077 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2078 TST R2, #4 ; are at least 4 bytes being set |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2079 STRNE R1, [R0], #4 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2080 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2081 _INT_memset3: ; may still be as many as 3 bytes to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2082 ; set. the address in R0 is guaranteed |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2083 ; to be word aligned here. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2084 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2085 TST R2, #2 ; are there at least 2 more bytes to |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2086 STRNEH R1, [R0], #2 ; set. the address in R0 is guaranteed |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2087 ; to be half-word aligned here. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2088 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2089 TST R2, #1 ; is there one remaining byte to set |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2090 STRNEB R1, [R0] |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2091 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2092 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2093 LDMFD SP!, {R0, PC} ; restore regs and return |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2094 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2095 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2096 ;****************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2097 ;* INT_memcpy - COPY CHARACTERS FROM SOURCE TO DEST * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2098 ;****************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2099 ;* MEMCPY32.ASM - 32 BIT STATE - v2.51 * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2100 ;* Copyright (c) 1996-2003 Texas Instruments Incorporated * |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2101 ;****************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2102 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2103 ;**************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2104 ;* INT_memcpy - COPY CHARACTERS FROM SOURCE TO DEST |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2105 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2106 ;* Same as C_MEMCPY defined in rts.src. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2107 ;* Used in INT_Initialize to download code into internal memory space. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2108 ;* The memcpy function defined in rts library is loaded into internal memory. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2109 ;* then, it can not be used in f_load_int_mem(). |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2110 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2111 ;**************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2112 ;* |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2113 ;* o DESTINATION LOCATION IS IN r0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2114 ;* o SOURCE LOCATION IS IN r1 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2115 ;* o NUMBER OF CHARACTERS TO BE COPIED IS IN r2 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2116 ;**************************************************************************** |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2117 .state32 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2118 .def _INT_memcpy |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2119 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2120 _INT_memcpy: |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2121 CMP r2, #0 ; CHECK FOR n == 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2122 BXEQ lr ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2123 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2124 STMFD sp!, {r0, lr} ; SAVE RETURN VALUE AND ADDRESS |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2125 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2126 TST r1, #0x3 ; CHECK ADDRESS ALIGNMENT |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2127 BNE _unaln ; IF NOT WORD ALIGNED, HANDLE SPECIALLY |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2128 TST r0, #0x3 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2129 BNE _saln ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2130 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2131 _aln: CMP r2, #16 ; CHECK FOR n >= 16 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2132 BCC _l16 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2133 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2134 STMFD sp!, {r4} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2135 SUB r2, r2, #16 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2136 _c16: LDMIA r1!, {r3, r4, r12, lr} ; COPY 16 BYTES |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2137 STMIA r0!, {r3, r4, r12, lr} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2138 SUBS r2, r2, #16 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2139 BCS _c16 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2140 LDMFD sp!, {r4} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2141 ADDS r2, r2, #16 ; RETURN IF DONE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2142 LDMEQFD sp!, {r0, pc} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2143 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2144 _l16: ANDS r3, r2, #0xC ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2145 BEQ _cp1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2146 BICS r2, r2, #0xC ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2147 ADR r12, _4line - 16 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2148 ADD pc, r12, r3, LSL #2 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2149 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2150 _4line: LDR r3, [r1], #4 ; COPY 4 BYTES |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2151 STR r3, [r0], #4 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2152 LDMEQFD sp!, {r0, pc} ; CHECK FOR n == 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2153 B _cp1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2154 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2155 LDMIA r1!, {r3, r12} ; COPY 8 BYTES |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2156 STMIA r0!, {r3, r12} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2157 LDMEQFD sp!, {r0, pc} ; CHECK FOR n == 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2158 B _cp1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2159 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2160 LDMIA r1!, {r3, r12, lr} ; COPY 12 BYTES |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2161 STMIA r0!, {r3, r12, lr} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2162 LDMEQFD sp!, {r0, pc} ; CHECK FOR n == 0 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2163 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2164 _cp1: SUBS r2, r2, #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2165 ADRNE r3, _1line - 4 ; SETUP TO COPY 1 - 3 BYTES... |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2166 ADDNE pc, r3, r2, LSL #4 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2167 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2168 _1line: LDRB r3, [r1], #1 ; COPY 1 BYTE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2169 STRB r3, [r0], #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2170 LDMFD sp!, {r0, pc} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2171 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2172 LDRH r3, [r1], #2 ; COPY 2 BYTES |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2173 STRH r3, [r0], #2 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2174 LDMFD sp!, {r0, pc} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2175 NOP ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2176 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2177 LDRH r3, [r1], #2 ; COPY 3 BYTES |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2178 STRH r3, [r0], #2 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2179 LDRB r3, [r1], #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2180 STRB r3, [r0], #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2181 LDMFD sp!, {r0, pc} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2182 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2183 _unaln: LDRB r3, [r1], #1 ; THE ADDRESSES ARE NOT WORD ALIGNED. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2184 STRB r3, [r0], #1 ; COPY BYTES UNTIL THE SOURCE IS |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2185 SUBS r2, r2, #1 ; WORD ALIGNED OR THE COPY SIZE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2186 LDMEQFD sp!, {r0, pc} ; BECOMES ZERO |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2187 TST r1, #0x3 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2188 BNE _unaln ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2189 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2190 _saln: TST r0, #0x1 ; IF THE ADDRESSES ARE OFF BY 1 BYTE |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2191 BNE _off1 ; JUST BYTE COPY |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2192 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2193 TST r0, #0x2 ; IF THE ADDRESSES ARE NOW WORD ALIGNED |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2194 BEQ _aln ; GO COPY. ELSE THEY ARE OFF BY 2, SO |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2195 ; GO SHORT WORD COPY |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2196 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2197 _off2: SUBS r2, r2, #4 ; COPY 2 BYTES AT A TIME... |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2198 BCC _c1h ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2199 _c2: LDR r3, [r1], #4 ; START BY COPYING CHUNKS OF 4, |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2200 .if .TMS470_BIG |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2201 STRH r3, [r0, #2] ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2202 MOV r3, r3, LSR #16 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2203 STRH r3, [r0], #4 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2204 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2205 STRH r3, [r0], #4 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2206 MOV r3, r3, LSR #16 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2207 STRH r3, [r0, #-2] ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2208 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2209 SUBS r2, r2, #4 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2210 BCS _c2 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2211 CMN r2, #4 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2212 LDMEQFD sp!, {r0, pc} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2213 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2214 _c1h: ADDS r2, r2, #2 ; THEN COPY THE ODD BYTES. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2215 LDRCSH r3, [r1], #2 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2216 STRCSH r3, [r0], #2 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2217 SUBCS r2, r2, #2 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2218 ADDS r2, r2, #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2219 LDRCSB r3, [r1], #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2220 STRCSB r3, [r0], #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2221 LDMFD sp!, {r0, pc} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2222 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2223 _off1: SUBS r2, r2, #4 ; COPY 1 BYTE AT A TIME... |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2224 BCC _c1b ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2225 _c1: LDR r3, [r1], #4 ; START BY COPYING CHUNKS OF 4, |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2226 .if .TMS470_BIG |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2227 STRB r3, [r0, #3] ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2228 MOV r3, r3, LSR #8 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2229 STRB r3, [r0, #2] ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2230 MOV r3, r3, LSR #8 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2231 STRB r3, [r0, #1] ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2232 MOV r3, r3, LSR #8 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2233 STRB r3, [r0], #4 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2234 .else |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2235 STRB r3, [r0], #4 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2236 MOV r3, r3, LSR #8 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2237 STRB r3, [r0, #-3] ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2238 MOV r3, r3, LSR #8 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2239 STRB r3, [r0, #-2] ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2240 MOV r3, r3, LSR #8 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2241 STRB r3, [r0, #-1] ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2242 .endif |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2243 SUBS r2, r2, #4 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2244 BCS _c1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2245 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2246 _c1b: ADDS r2, r2, #4 ; THEN COPY THE ODD BYTES. |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2247 LDMEQFD sp!, {r0, pc} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2248 _lp1: LDRB r3, [r1], #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2249 STRB r3, [r0], #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2250 SUBS r2, r2, #1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2251 BNE _lp1 ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2252 LDMFD sp!, {r0, pc} ; |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2253 |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2254 .end |
92470e5d0b9e
src: partial import from FC Selenite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2255 |