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comparison gcc/ld-script.src @ 8:727914266f28

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gcc: adapted from Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 03:13:51 +0000
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7:d0c841cb75c7 8:727914266f28
1 dnl This ld script source is fed through m4 in order to fill in
2 dnl those settings which depend on the configuration.
3 dnl Two include files are fed to m4 before this main body:
4 dnl the appropriate targets/*.m4 file defining the memory config
5 dnl of the hardware, and one of flash.m4 or xram.m4 to select
6 dnl the build type.
7
8 /*
9 * FreeCalypso Selenite ld script for the Buildmem build
10 */
11
12 ENTRY(_Firmware_boot_entry)
13
14 MEMORY {
15 ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1,
16 ` FLASH_OVERLAY : ORIGIN = 0, LENGTH = 0x2000')
17 ifelse(Buildmem,FLASH,
18 ` FLASH : ORIGIN = FLASHIMAGE_BASE_ADDR,
19 LENGTH = CONFIG_FWFLASH_SIZE - FLASHIMAGE_BASE_ADDR')
20 IRAM : ORIGIN = 0x00800000, LENGTH = CONFIG_IRAM_SIZE
21 XRAM : ORIGIN = 0x01000000, LENGTH = CONFIG_XRAM_SIZE
22 }
23
24 SECTIONS {
25 dnl The following sections exist only in the flashImage build,
26 dnl and only on targets that use the Calypso boot ROM.
27 ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1,
28 ` /* Part of flash overlaid by the boot ROM */
29 bootrom.overlay 0 : {
30 *(bootrom.overlay)
31 } > FLASH_OVERLAY
32
33 /* code that enables the boot ROM and jumps to it */
34 bootrom.switch : {
35 *(bootrom.switch)
36 } > IRAM AT> FLASH_OVERLAY
37 __romswitch_ram_addr = ADDR(bootrom.switch);
38 __romswitch_flash_addr = LOADADDR(bootrom.switch);
39 __romswitch_size = SIZEOF(bootrom.switch);
40 ')dnl
41
42 /* boot entry code, going into flash or XRAM emulating flash */
43 .inttext INTTEXT_BASE_ADDR : {
44 *(.inttext)
45 } > Buildmem
46
47 /* copy-to-IRAM code */
48 iram.text 0x80001C : {
49 /* the 7 exception and interrupt vectors @ 0x80001C */
50 *(.ramvecs)
51 *_ir.a:(.text*)
52 *_int.a:(.text*)
53 *_intram.a:(.text*)
54 *osx_na7_db.a:(.text*)
55 *tpudrv.a:(.text*)
56 *drivers_flash.a:niq32.o(.text*)
57 *sim_drv.a:sim32.o(.text*)
58 *libc.a:(.text*)
59 *libgcc.a:(.text*)
60 } > IRAM Put_in_flash
61 ifelse(Buildmem,FLASH,
62 ` __iramtext_ram_addr = ADDR(iram.text);
63 __iramtext_flash_addr = LOADADDR(iram.text);
64 __iramtext_size = SIZEOF(iram.text);
65 ')dnl
66
67 /* XIP code, going into flash or XRAM emulating flash */
68 xip.text : {
69 *(.text*)
70 /* let's put the ARM->Thumb veneers in the XIP section */
71 *(.glue_7)
72 } > Buildmem
73
74 /* all .rodata will stay in flash */
75 .rodata : {
76 *(.rodata*)
77 } > Buildmem
78
79 .bss_dar (NOLOAD) : {
80 *dar_gbl_var.a:(.bss* COMMON)
81 } > XRAM
82
83 /*
84 * All .data will go into XRAM.
85 * For the flash build we'll have a step that copies
86 * the .data section from flash to XRAM; for the RAM-only
87 * build it goes directly into XRAM and stays there.
88 */
89 .data : {
90 *(.data*)
91 } > XRAM Put_in_flash
92 ifelse(Buildmem,FLASH,
93 ` __initdata_ram_addr = ADDR(.data);
94 __initdata_flash_addr = LOADADDR(.data);
95 __initdata_size = SIZEOF(.data);
96 ')dnl
97
98 /* we have two kinds of BSS: internal and external */
99 int.bss (NOLOAD) : {
100 *(.l1s_global)
101 *_ir.a:(.bss* COMMON)
102 *_int.a:(.bss* COMMON)
103 *_intram.a:(.bss* COMMON)
104 *osx_na7_db.a:(.bss* COMMON)
105 *tpudrv.a:(.bss* COMMON)
106 *libc.a:(.bss* COMMON)
107 *libgcc.a:(.bss* COMMON)
108 *(.API_HISR_stack)
109 . = ALIGN(4);
110 } > IRAM
111 __intbss_start = ADDR(int.bss);
112 __intbss_size = SIZEOF(int.bss);
113
114 ext.bss (NOLOAD) : {
115 *(.bss* COMMON)
116 . = ALIGN(4);
117 } > XRAM
118 __extbss_start = ADDR(ext.bss);
119 __extbss_size = SIZEOF(ext.bss);
120
121 int.stack (NOLOAD) : ALIGN(8) {
122 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
123 _Stack_segment_start = .;
124 . += 0xB00;
125 _Stack_segment_end = .;
126
127 _iram_end = .;
128 } > IRAM
129
130 ext.stack (NOLOAD) : ALIGN(8) {
131 /* Stack for abort and/or undefined modes. */
132 . += 512;
133 _Except_Stack_SP = .;
134
135 /* Leave 38 32bit words for state saving on exceptions. */
136 xdump_buffer = .;
137 . += 38 * 4;
138
139 _xram_end = .;
140 } > XRAM
141 }