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comparison src/cs/layer1/cust0/l1_rf10.h @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
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1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename l1_rf10.h
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8
9 #ifndef __L1_RF_H__
10 #define __L1_RF_H__
11
12 // is this defined somewhere else?
13 //#define RF_HW_BAND_EGSM
14 //#define RF_HW_BAND_DCS
15
16 #define RF_HW_BAND_PCS 0x4
17 #define RF_HW_BAND_DUAL_US 0x80
18 #define RF_HW_BAND_DUAL_EXT 0x20
19
20 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS
21
22 // L1 RF SW Multiband configuration
23 //--------------------------
24
25 // RF_SW_MULTIBAND_SUPPORT values
26 #define SINGLE_BAND_900 1
27 #define SINGLE_BAND_1800 2
28 #define SINGLE_BAND_850 3
29 #define SINGLE_BAND_1900 4
30 #define DUAL_BAND_900_1800 5
31 #define DUAL_BAND_850_1900 6
32 #define TRI_BAND_900_1800_1900 7
33 #define TRI_BAND_850_1900_1800 8
34 #define QUAD_BAND 9
35
36 //IMPORTANT !: To change RF_SW_MULTIBAND_SUPPORT value, it must be synchronized with other multiband settings in the software
37 // To match the protocol stack settings( e.g EF_RFCAP ) in order to make sure that the value of STD sent in MPHC_INIT_L1_REQ is supported by L1
38 // And also match the RF HW support: RF_HW_BAND_SUPPORT
39 #define RF_SW_MULTIBAND_SUPPORT QUAD_BAND
40
41 // Generate band dependancy options
42 #define RF_SW_BAND900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
43 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND) )
44
45 #define RF_SW_BAND1800 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1800) ||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
46 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
47 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
48
49 #define RF_SW_BAND850 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_850)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
50 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
51
52 #define RF_SW_BAND1900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
53 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900)||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
54 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
55 /************************************/
56 /* SYNTHESIZER setup time... */
57 /************************************/
58
59 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1) // RX Synthesizer setup time in qbit.
60 #define TX_SYNTH_SETUP_TIME (- TRF_T1) // TX Synthesizer setup time in qbit.
61
62 /************************************/
63 /* time for TPU scenario ending... */
64 /************************************/
65
66 #define RX_TPU_SCENARIO_ENDING 0 // execution time of BDLENA down
67 // contained in serialization time
68 #define TX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 + 1 // execution time of BULON down
69 // minus serialization time + 1 TPU_MOVE
70
71 /******************************************************/
72 /* TXPWR configuration... */
73 /* Fixed TXPWR value when GSM management is disabled. */
74 /******************************************************/
75
76 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
77 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252
78 // #define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE)
79 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15
80 #endif
81
82 /************************************/
83 /*(ANALOG)delay (in qbits) */
84 /************************************/
85 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
86 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
87 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
88
89 #if (ANLG_FAM == 1)
90 #define UL_ABB_DELAY 6 // modulator input to output delay
91 #endif
92
93 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
94 #define UL_ABB_DELAY 3 // modulator input to output delay
95 #endif
96
97 /************************************/
98 /* TX Propagation delay... */
99 /************************************/
100 #if (ANLG_FAM == 1)
101 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
102 #endif
103
104 #if (ANLG_FAM == 2) || (ANLG_FAM == 3)
105 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY + 2) // = 42
106 #endif
107
108 /************************************/
109 /* Initial value for APC DELAY */
110 /************************************/
111
112 #if (ANLG_FAM == 1)
113 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
114 #define APCDEL_DOWN 2 // minimum value: 2
115 #define APCDEL_UP (6+5) // minimum value: 6
116 #endif
117
118 #if (ANLG_FAM == 2) || (ANLG_FAM == 3)
119 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
120 #define APCDEL_DOWN (2+0) // minimum value: 2
121 #define APCDEL_UP (6+8) // minimum value: 6
122 #endif
123
124 #define GUARD_BITS 8
125
126 /************************************/
127 /* Initial value for AFC... */
128 /************************************/
129
130 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
131
132 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames
133 // Clara (RF=10) LDO wakeup requires 3 frames
134
135 /************************************/
136 /* Baseband registers */
137 /************************************/
138
139 #if (ANLG_FAM == 1)
140
141 // Omega registers values will be programmed at 1st DSP communication interrupt
142
143 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
144 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
145 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
146 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
147 #define C_APCOFF ((0x07c << 6) | APCOFF | TRUE ) // value at reset-Changed from 0x0016- CR 27.12
148 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
149 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
150 #define C_DAI_ON_OFF (0x000) // value at reset
151 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
152 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
153
154 // BULRUDEL will be initialized on rach only ....
155 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
156 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
157 #endif
158
159 #if (ANLG_FAM == 2)
160
161 // IOTA registers values will be programmed at 1st DSP communication interrupt
162
163 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
164 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
165 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
166 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
167 #define C_APCOFF ((0x068 << 6) | APCOFF | TRUE ) // value at reset-Changed from 3c to 28 CR 17.11.02// x2 slope 128
168 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
169 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
170 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
171 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
172 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
173 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE ) // MICBIASEL=0, VDLHSO=0, MICAUX=0
174
175 // BULRUDEL will be initialized on rach only ....
176 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
177 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE ) //
178
179 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE ) // External RX I/Q DC offset calibration, Output common mode=1.35V
180 // Monoslot, Vpp=8/15*Vref
181 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
182 #endif
183
184 #if (ANLG_FAM == 3)
185
186 // SYREN registers values will be programmed at 1st DSP communication interrupt
187
188 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
189 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
190 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone - 17 dB, PGA_UL 3 dB
191 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
192 #define C_APCOFF ((0x07c << 6) | APCOFF | TRUE ) // value at reset-Changed from 0x0016- CR 27.12
193 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
194 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
195 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
196 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
197 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1 AUXI 28,2 dB
198 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE ) // HSMIC on, SPKG gain @ 2,5dB
199
200 // BULRUDEL will be initialized on rach only ....
201 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6)<<6) | APCDEL1)
202 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE )
203
204 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE ) // External autocalibration, Output common mode=1.35V
205 // Monoslot, Vpp=8/15*Vref
206 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
207
208 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE ) // HSOAUTO enabled only
209 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
210 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE ) // Init to zero
211 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE ) // Speech on all outputs
212 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE ) // Init to zero
213 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE ) // Init to zero
214
215 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
216
217 #define C_BBCFG 0x44 // Syren Like BDLF Filter - DC OFFSET removal OFF
218
219 #endif
220
221 /************************************/
222 /* Automatic frequency compensation */
223 /************************************/
224 /********************* C_Psi_sta definition *****************************/
225 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
226 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
227 /* regarding Vega V/N = 2.4/4096 */
228 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
229 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
230 /* = 0.000195748 */
231 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
232 /************************************************************************/
233
234 #define C_Psi_sta_inv 4174L // (1/C_Psi_sta)
235 #define C_Psi_st 13L // C_Psi_sta * 0.8 F0.16
236 #define C_Psi_st_32 823216L // F0.32
237 #define C_Psi_st_inv 5217L // (1/C_Psi_st)
238
239 #if (VCXO_ALGO == 1)
240 // Linearity parameters
241 #define C_AFC_DAC_CENTER ((111)*8)
242 #define C_AFC_DAC_MIN ((-1196)*8)
243 #define C_AFC_DAC_MAX ((1419)*8)
244
245 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10
246 #endif
247
248 typedef struct
249 {
250 WORD16 eeprom_afc;
251 UWORD32 psi_sta_inv;
252 UWORD32 psi_st;
253 UWORD32 psi_st_32;
254 UWORD32 psi_st_inv;
255
256 #if (VCXO_ALGO == 1)
257 // VCXO adjustment parameters
258 // Parameters used when assuming linearity
259 WORD16 dac_center;
260 WORD16 dac_min;
261 WORD16 dac_max;
262 WORD16 snr_thr;
263 #endif
264 }
265 T_AFC_PARAMS;
266
267 /************************************/
268 /* Swap IQ definitions... */
269 /************************************/
270 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
271
272 #define SWAP_IQ_GSM 0
273 #define SWAP_IQ_DCS 2 // was 2 for sara version 1
274 #define SWAP_IQ_PCS 2
275 #define SWAP_IQ_GSM850 0 // TBD
276
277 /************************************/
278 /************************************/
279 // typedef
280 /************************************/
281 /************************************/
282
283 /*************************************************************/
284 /* Define structure for apc of TX Power ******/
285 /*************************************************************/
286
287 typedef struct
288 { // pcm-file "rf/tx/level.gsm|dcs"
289 UWORD16 apc; // 0..31
290 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
291 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
292 }
293 T_TX_LEVEL;
294
295 /************************************/
296 /* Automatic Gain Control */
297 /************************************/
298 /* Define structure for sub-band definition of TX Power ******/
299 typedef struct
300 {
301 UWORD16 upper_bound; // highest physical arfcn of the sub-band
302 WORD16 agc_calib; // AGC for each TXPWR
303 }T_RF_AGC_BAND;
304
305 /************************************/
306 /* Ramp definitions */
307 /************************************/
308 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
309 typedef struct
310 {
311 UWORD8 ramp_up [16]; // Ramp-up profile
312 UWORD8 ramp_down [16]; // Ramp-down profile
313 }
314 T_TX_RAMP;
315 #endif
316
317
318 // RF structure definition
319 //========================
320
321 enum RfRevision {
322 RF_IGNORE = 0x0000,
323 RF_SL2 = 0x1000,
324 RF_GAIA_20X = 0x2000,
325 RF_GAIA_20A = 0x2001,
326 RF_GAIA_20B = 0x2002,
327 RF_ATLAS_20B = 0x2020,
328 RF_PASCAL_20 = 0x2030
329 };
330
331 // Number of bands supported
332 #define GSM_BANDS 2
333
334 #define MULTI_BAND1 0
335 #define MULTI_BAND2 1
336
337 // RF table sizes
338 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
339 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
340
341 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
342 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
343 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
344 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
345 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
346
347 #define AGC_TABLE_SIZE 27
348
349 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
350
351
352 // RX parameters and tables
353 //-------------------------
354
355 // AGC parameters and tables
356 typedef struct
357 {
358 UWORD16 low_agc_noise_thr;
359 UWORD16 high_agc_sat_thr;
360 UWORD16 low_agc;
361 UWORD16 high_agc;
362 UWORD8 il2agc_pwr[121];
363 UWORD8 il2agc_max[121];
364 UWORD8 il2agc_av[121];
365 }
366 T_AGC;
367
368 // Calibration parameters
369 typedef struct
370 {
371 UWORD16 g_magic;
372 UWORD16 lna_att;
373 UWORD16 lna_switch_thr_low;
374 UWORD16 lna_switch_thr_high;
375 }
376 T_RX_CAL_PARAMS;
377
378 // RX temperature compensation
379 typedef struct
380 {
381 WORD16 temperature;
382 WORD16 agc_calib;
383 }
384 T_RX_TEMP_COMP;
385
386 // RF RX structure
387 typedef struct
388 {
389 T_AGC agc;
390 }
391 T_RF_RX; //common
392
393 // RF RX structure
394 typedef struct
395 {
396 T_RX_CAL_PARAMS rx_cal_params;
397 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
398 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
399 }
400 T_RF_RX_BAND;
401
402
403 // TX parameters and tables
404 //-------------------------
405
406 // TX temperature compensation
407 typedef struct
408 {
409 WORD16 temperature;
410 #if (ORDER2_TX_TEMP_CAL==1)
411 WORD16 a;
412 WORD16 b;
413 WORD16 c;
414 #else
415 WORD16 apc_calib;
416 #endif
417 }
418 T_TX_TEMP_CAL;
419
420
421 // Ramp up and ramp down delay
422 typedef struct
423 {
424 UWORD16 up;
425 UWORD16 down;
426 }
427 T_RAMP_DELAY;
428
429 typedef struct
430 {
431 UWORD16 arfcn_limit;
432 WORD16 chan_cal;
433 }
434 T_TX_CHAN_CAL;
435
436 // RF TX structure
437 typedef struct
438 {
439 T_RAMP_DELAY ramp_delay;
440 UWORD8 guard_bits; // number of guard bits needed for ramp up
441 UWORD8 prg_tx;
442 }
443 T_RF_TX; //common
444
445 // RF TX structure
446 typedef struct
447 {
448 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
449 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
450 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
451 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
452 }
453 T_RF_TX_BAND;
454
455 // band structure
456 typedef struct
457 {
458 T_RF_RX_BAND rx;
459 T_RF_TX_BAND tx;
460 UWORD8 swap_iq;
461 }
462 T_RF_BAND;
463
464 // RF structure
465 typedef struct
466 {
467 // common for all bands
468 UWORD16 rf_revision;
469 UWORD16 radio_band_support;
470 T_RF_RX rx;
471 T_RF_TX tx;
472 T_AFC_PARAMS afc;
473 }
474 T_RF;
475
476 /************************************/
477 /* MADC definitions */
478 /************************************/
479 // Omega: 5 external channels if touch screen not used, 3 otherwise
480 enum ADC_INDEX {
481 ADC_VBAT,
482 ADC_VCHARG,
483 ADC_ICHARG,
484 ADC_VBACKUP,
485 ADC_BATTYP,
486 ADC_BATTEMP,
487 ADC_ADC3, // name of this ??
488 ADC_RFTEMP,
489 ADC_ADC4,
490 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
491 };
492
493 typedef struct
494 {
495 WORD16 converted[ADC_INDEX_END]; // converted
496 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
497 }
498 T_ADC;
499
500 /************************************/
501 /* MADC calibration */
502 /************************************/
503 typedef struct
504 {
505 UWORD16 a[ADC_INDEX_END];
506 WORD16 b[ADC_INDEX_END];
507 }
508 T_ADCCAL;
509
510 // Conversion table: ADC value -> temperature
511 typedef struct
512 {
513 UWORD16 adc; // ADC reading is 10 bits
514 WORD16 temp; // temp is in approx. range -30..+80
515 }
516 T_TEMP;
517
518 typedef struct
519 {
520 char *name;
521 void *addr;
522 int size;
523 }
524 T_CONFIG_FILE;
525
526 typedef struct
527 {
528 char *name; // name of ffs file suffix
529 T_RF_BAND *addr; // address to default flash structure
530 UWORD16 max_carrier; // max carrier
531 UWORD16 max_txpwr; // max tx power
532 }
533 T_BAND_CONFIG;
534
535 typedef struct
536 {
537 UWORD8 band[GSM_BANDS]; // index to band address
538 UWORD8 txpwr_tp; // tx power turning point
539 UWORD16 first_arfcn; // first index
540 }
541 T_STD_CONFIG;
542
543 enum GSMBAND_DEF
544 {
545 BAND_NONE,
546 BAND_EGSM900,
547 BAND_DCS1800,
548 BAND_PCS1900,
549 BAND_GSM850,
550 BAND_PCS1900_US,
551 // put new bands here
552 BAND_GSM900 // last entry
553 };
554
555 /************************************/
556 /* ABB (Omega) Initialization */
557 /************************************/
558
559 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
560 #define ABB_TABLE_SIZE 16
561 #endif
562
563 #if (ANLG_FAM == 3)
564 #define ABB_TABLE_SIZE 22
565 #endif
566
567 // Note that this translation is probably not needed at all. But until L1 is
568 // (maybe) changed to simply initialize the ABB from a table of words, we
569 // use this to make things more easy-readable.
570 #if (ANLG_FAM == 1)
571 enum ABB_REGISTERS {
572 ABB_AFCCTLADD = 0,
573 ABB_VBUCTRL,
574 ABB_VBDCTRL,
575 ABB_BBCTRL,
576 ABB_APCOFF,
577 ABB_BULIOFF,
578 ABB_BULQOFF,
579 ABB_DAI_ON_OFF,
580 ABB_AUXDAC,
581 ABB_VBCTRL,
582 ABB_APCDEL1
583 };
584 #endif
585
586 #if (ANLG_FAM == 2)
587 enum ABB_REGISTERS {
588 ABB_AFCCTLADD = 0,
589 ABB_VBUCTRL,
590 ABB_VBDCTRL,
591 ABB_BBCTRL,
592 ABB_BULGCAL,
593 ABB_APCOFF,
594 ABB_BULIOFF,
595 ABB_BULQOFF,
596 ABB_DAI_ON_OFF,
597 ABB_AUXDAC,
598 ABB_VBCTRL1,
599 ABB_VBCTRL2,
600 ABB_APCDEL1,
601 ABB_APCDEL2
602 };
603 #endif
604
605 #if (ANLG_FAM == 3)
606 enum ABB_REGISTERS {
607 ABB_AFCCTLADD = 0,
608 ABB_VBUCTRL,
609 ABB_VBDCTRL,
610 ABB_BBCTRL,
611 ABB_BULGCAL,
612 ABB_APCOFF,
613 ABB_BULIOFF,
614 ABB_BULQOFF,
615 ABB_DAI_ON_OFF,
616 ABB_AUXDAC,
617 ABB_VBCTRL1,
618 ABB_VBCTRL2,
619 ABB_APCDEL1,
620 ABB_APCDEL2,
621 ABB_VBPOP,
622 ABB_VAUDINITD,
623 ABB_VAUDCTRL,
624 ABB_VAUOCTRL,
625 ABB_VAUSCTRL,
626 ABB_VAUDPLL
627 };
628 #endif
629
630 #endif
631