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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
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1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename l1_rf12.h
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8
9 #ifndef __L1_RF_H__
10 #define __L1_RF_H__
11
12 #include "fc-target.h"
13
14 #define RF_RITA_10 0x2030 // Check with TIDK
15
16 //#define RF_HW_BAND_EGSM
17 //#define RF_HW_BAND_DCS
18 #define RF_HW_BAND_PCS 0x4
19 #define RF_HW_BAND_DUAL_US 0x80
20 #define RF_HW_BAND_DUAL_EXT 0x20
21
22 //#define RF_HW_BAND_SUPPORT (0x0020 | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS
23 // radio_band_support E-GSM/DCS + GSM850/PCS
24 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_DUAL_US)
25
26 // L1 RF SW Multiband configuration
27 //--------------------------
28
29 // RF_SW_MULTIBAND_SUPPORT values
30 #define SINGLE_BAND_900 1
31 #define SINGLE_BAND_1800 2
32 #define SINGLE_BAND_850 3
33 #define SINGLE_BAND_1900 4
34 #define DUAL_BAND_900_1800 5
35 #define DUAL_BAND_850_1900 6
36 #define TRI_BAND_900_1800_1900 7
37 #define TRI_BAND_850_1900_1800 8
38 #define QUAD_BAND 9
39
40 //IMPORTANT !: To change RF_SW_MULTIBAND_SUPPORT value, it must be synchronized with other multiband settings in the software
41 // To match the protocol stack settings( e.g EF_RFCAP ) in order to make sure that the value of STD sent in MPHC_INIT_L1_REQ is supported by L1
42 // And also match the RF HW support: RF_HW_BAND_SUPPORT
43 #define RF_SW_MULTIBAND_SUPPORT QUAD_BAND
44
45 // Generate band dependancy options
46 #define RF_SW_BAND900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
47 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND) )
48
49 #define RF_SW_BAND1800 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1800) ||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
50 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
51 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
52
53 #define RF_SW_BAND850 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_850)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
54 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
55
56 #define RF_SW_BAND1900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
57 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900)||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
58 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
59
60 /************************************/
61 /* SYNTHESIZER setup time... */
62 /************************************/
63 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit.
64 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
65
66 /************************************/
67 /* time for TPU scenario ending... */
68 /************************************/
69 //
70 // The following values are used to take into account any TPU activity AFTER
71 // BDLON (or BDLENA) down (for RX) and BULON down (for TX)
72 // - If there are no TPU commands after BDLON (or BDLENA) down and BULON down,
73 // these defines must be ZERO
74 // - If there IS some TPU command after BDLON (or BDLENA) and BULON down,
75 // these defines must be equal to the time difference (in qbits) between
76 // the BDLON (or BDLENA) or BULON time and the last TPU command on
77 // the TPU scenario
78 #define RX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BDLENA down
79 #define TX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BULON down
80
81
82 /******************************************************/
83 /* TXPWR configuration... */
84 /* Fixed TXPWR value when GSM management is disabled. */
85 /******************************************************/
86
87 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
88 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252
89 //#define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE)
90 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15
91 #endif
92
93
94 /************************************/
95 /* ANALOG delay (in qbits) */
96 /************************************/
97 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
98 #define UL_DELAY_1RF 7 // time spent in the first uplink RF block
99 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
100 #if (ANLG_FAM == 1)
101 #define UL_ABB_DELAY 3 // modulator input to output delay
102 #endif
103 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
104 #define UL_ABB_DELAY 3 // modulator input to output delay
105 #endif
106
107 /************************************/
108 /* TX Propagation delay... */
109 /************************************/
110 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
111 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
112 #endif
113
114 /************************************/
115 /* Initial value for APC DELAY */
116 /************************************/
117 #if (ANLG_FAM == 1)
118 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
119 #define APCDEL_DOWN 2 // minimum value: 2
120 #define APCDEL_UP (6+5) // minimum value: 6
121 #endif
122
123 #if (ANLG_FAM == 2) || (ANLG_FAM == 3)
124 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
125 #define APCDEL_DOWN (2+0) // minimum value: 2
126 #define APCDEL_UP (6+3+1) // minimum value: 6
127 // REMOVE // Jerome Modif for ARF7: (6+3) instead of (6+8)
128 #endif
129
130 #define GUARD_BITS 7
131
132 /************************************/
133 /* Initial value for AFC... */
134 /************************************/
135 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
136
137 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames and RF BAND GAP stable after 4 frames
138 // Rita (RF=12) LDO wakeup requires 6 frames
139
140 /************************************/
141 /* Baseband registers */
142 /************************************/
143 #if (ANLG_FAM == 1)
144 // Omega registers values will be programmed at 1st DSP communication interrupt
145 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
146 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
147 #define C_VBUCTRL ((0x106 << 6) | VBUCTRL | TRUE) // Uplink gain amp 0dB, Sidetone gain to mute
148 #define C_VBDCTRL ((0x026 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control 0 dB
149 // RITA does not need an APCOFFSET because the PACTRL is internal:
150 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // value at reset-Changed from 0x0016- CR 27.12
151 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE)
152 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
153 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
154 #define C_DAI_ON_OFF (0x000) // value at reset
155 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
156 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
157 // BULRUDEL will be initialized on rach only ....
158 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
159 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
160 #endif
161
162 #if (ANLG_FAM == 2)
163
164 // IOTA registers values will be programmed at 1st DSP communication interrupt
165
166 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
167 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
168 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3 dB, Sidetone gain to -17dB
169 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB
170 // RITA does not need an APCOFFSET because the PACTRL is internal:
171 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // x2 slope 128
172 #if (RF_PA == 0 || RF_PA == 3) || defined(CONFIG_TARGET_PIRELLI)
173 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128
174 #elif defined(CONFIG_TARGET_C1XX)
175 #define C_APCOFF ((0x060 << 6) | APCOFF | TRUE) // x2 slope 128
176 #elif defined(CONFIG_TARGET_J100)
177 #define C_APCOFF ((0x074 << 6) | APCOFF | TRUE) // x2 slope 128
178 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4)
179 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128
180 #endif
181 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
182 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
183 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset
184 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
185
186
187 // audio patch for H2-sample:
188 #if (RAZ_VULSWITCH_REGAUDIO == 1)
189 #define C_VBCTRL1 ((0x003 << 6) | VBCTRL1 | TRUE) // VBDFAUXG = 1, VULSWITCH=0, VDLAUX=1, VDLEAR=1 // jkb h2sample change
190 #else
191 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
192 #endif
193
194
195 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE) // MICBIASEL=0, VDLHSO=0, MICAUX=0
196 // BULRUDEL will be initialized on rach only ....
197 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
198 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) //
199 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V
200 // Monoslot, Vpp=8/15*Vref
201 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB
202 #endif
203
204 #if (ANLG_FAM == 3)
205
206 // SYREN registers values will be programmed at 1st DSP communication interrupt
207
208 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
209 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
210 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3dB, Sidetone gain to -17 dB
211 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB
212 #if (RF_PA == 0 || RF_PA == 3)
213 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128
214 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4)
215 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128
216 #endif
217 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
218 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
219 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset
220 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
221 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE) // VULSWITCH=1 AUXI 28,2 dB
222 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE) // HSMIC on, SPKG gain @ 2,5dB
223
224 // BULRUDEL will be initialized on rach only ....
225 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6)<<6) | APCDEL1)
226 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) //
227 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V
228 // Monoslot, Vpp=8/15*Vref
229 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB
230
231 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE) // HSOAUTO enabled only
232 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
233 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE) // Init to zero
234 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE) // Speech on all outputs
235 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE) // Init to zero
236 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE) // Init to zero
237
238 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
239
240 #define C_BBCFG (0x44) // Syren Like BDLF Filter - DC OFFSET removal OFF
241
242 #endif
243
244
245 /************************************/
246 /* Automatic frequency compensation */
247 /************************************/
248 /********************* C_Psi_sta definition *****************************/
249 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
250 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
251 /* regarding Vega V/N = 2.4/4096 */
252 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
253 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
254 /* = 0.000195748 */
255 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
256 /************************************************************************/
257
258 #ifdef CONFIG_TARGET_PIRELLI
259
260 /* matching Pirelli's fw as read out via rftr 9 */
261 #define C_Psi_sta_inv 6974L // (1/C_Psi_sta)
262 #define C_Psi_st 8L // C_Psi_sta * 0.8 F0.16
263 #define C_Psi_st_32 492713L // F0.32
264 #define C_Psi_st_inv 8717L // (1/C_Psi_st)
265
266 #elif defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_FCFAM)
267
268 /*
269 * We calibrate our VCXO per unit following OM's precedent,
270 * thus the compiled-in AFC params don't really matter on FC/OM targets,
271 * but let's put in some numbers that are representative of our VCXO,
272 * as opposed to the totally wrong numbers corresponding to the
273 * significantly different VCXO on the original Leonardo.
274 */
275
276 #define C_Psi_sta_inv 3462L // (1/C_Psi_sta)
277 #define C_Psi_st 15L // C_Psi_sta * 0.8 F0.16
278 #define C_Psi_st_32 992326L // F0.32
279 #define C_Psi_st_inv 4328L // (1/C_Psi_st)
280
281 #else
282
283 /* original TCS211 values */
284 #define C_Psi_sta_inv 5419L // (1/C_Psi_sta)
285 #define C_Psi_st 10L // C_Psi_sta * 0.8 F0.16
286 #define C_Psi_st_32 634112L // F0.32
287 #define C_Psi_st_inv 6773L // (1/C_Psi_st)
288
289 #endif
290
291 #if (VCXO_ALGO == 1)
292 // Linearity parameters
293
294 #ifdef CONFIG_TARGET_COMPAL
295 /* matching Compal's fw as read out via rftr 9 */
296 #define C_AFC_DAC_CENTER ((1000)*8)
297 #define C_AFC_DAC_MIN ((-500)*8)
298 #define C_AFC_DAC_MAX ((2500)*8)
299 #else
300 /* original TCS211 values */
301 #define C_AFC_DAC_CENTER ((111)*8)
302 #define C_AFC_DAC_MIN ((-1196)*8)
303 #define C_AFC_DAC_MAX ((1419)*8)
304 #endif
305
306 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10
307 #endif
308
309 typedef struct
310 {
311 WORD16 eeprom_afc;
312 UWORD32 psi_sta_inv;
313 UWORD32 psi_st;
314 UWORD32 psi_st_32;
315 UWORD32 psi_st_inv;
316
317 #if (VCXO_ALGO)
318 // VCXO adjustment parameters
319 // Parameters used when assuming linearity
320 WORD16 dac_center;
321 WORD16 dac_min;
322 WORD16 dac_max;
323 WORD16 snr_thr;
324 #endif
325 }
326 T_AFC_PARAMS;
327
328 /************************************/
329 /* Swap IQ definitions... */
330 /************************************/
331 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
332 #if (RF_PG == R_PG_10)
333 // PG 1.0 -> 1 (Swap RX only)
334 // GSM 850 => TX is ALWAYS swapped compared to GSM 900
335 #define SWAP_IQ_GSM 1
336 #define SWAP_IQ_DCS 1
337 #define SWAP_IQ_PCS 1
338 #define SWAP_IQ_GSM850 3 // Swap TX compared to GSM 900
339 #else
340 // All PG versions ABOVE 1.0 -> 0 (No Swap)
341 // GSM 850 => TX is ALWAYS swapped compared to GSM 900
342 #define SWAP_IQ_GSM 0
343 #define SWAP_IQ_DCS 0
344 #define SWAP_IQ_PCS 0
345 #define SWAP_IQ_GSM850 2 // Swap TX compared to GSM 900
346 #endif
347
348 /************************************/
349 /************************************/
350 // typedef
351 /************************************/
352 /************************************/
353
354 /*************************************************************/
355 /* Define structure for apc of TX Power ******/
356 /*************************************************************/
357 typedef struct
358 { // pcm-file "rf/tx/level.gsm|dcs"
359 UWORD16 apc; // 0..31
360 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
361 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
362 }
363 T_TX_LEVEL;
364
365 /************************************/
366 /* Automatic Gain Control */
367 /************************************/
368 /* Define structure for sub-band definition of TX Power ******/
369 typedef struct
370 {
371 UWORD16 upper_bound; //highest physical arfcn of the sub-band
372 WORD16 agc_calib; // AGC for each TXPWR
373 }T_RF_AGC_BAND;
374
375 /************************************/
376 /* Ramp definitions */
377 /************************************/
378 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
379 typedef struct
380 {
381 UWORD8 ramp_up [16]; // Ramp-up profile
382 UWORD8 ramp_down [16]; // Ramp-down profile
383 }
384 T_TX_RAMP;
385 #endif
386
387
388 // RF structure definition
389 //========================
390
391 // Number of bands supported
392 #define GSM_BANDS 2
393
394 #define MULTI_BAND1 0
395 #define MULTI_BAND2 1
396 // RF table sizes
397 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
398 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
399
400 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
401 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
402 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
403 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
404 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
405
406 #define AGC_TABLE_SIZE 20
407 #define MIN_AGC_INDEX 6
408
409 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
410
411
412 // RX parameters and tables
413 //-------------------------
414
415 // AGC parameters and tables
416 typedef struct
417 {
418 UWORD16 low_agc_noise_thr;
419 UWORD16 high_agc_sat_thr;
420 UWORD16 low_agc;
421 UWORD16 high_agc;
422 UWORD8 il2agc_pwr[121];
423 UWORD8 il2agc_max[121];
424 UWORD8 il2agc_av[121];
425 }
426 T_AGC;
427
428 // Calibration parameters
429 typedef struct
430 {
431 UWORD16 g_magic;
432 UWORD16 lna_att;
433 UWORD16 lna_switch_thr_low;
434 UWORD16 lna_switch_thr_high;
435 }
436 T_RX_CAL_PARAMS;
437
438 // RX temperature compensation
439 typedef struct
440 {
441 WORD16 temperature;
442 WORD16 agc_calib;
443 }
444 T_RX_TEMP_COMP;
445
446 // RF RX structure
447 typedef struct
448 {
449 T_AGC agc;
450 }
451 T_RF_RX; //common
452
453 // RF RX structure
454 typedef struct
455 {
456 T_RX_CAL_PARAMS rx_cal_params;
457 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
458 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
459 }
460 T_RF_RX_BAND;
461
462
463 // TX parameters and tables
464 //-------------------------
465
466 // TX temperature compensation
467 typedef struct
468 {
469 WORD16 temperature;
470 #if (ORDER2_TX_TEMP_CAL==1)
471 WORD16 a;
472 WORD16 b;
473 WORD16 c;
474 #else
475 WORD16 apc_calib;
476 #endif
477 }
478 T_TX_TEMP_CAL;
479
480 // Ramp up and ramp down delay
481 typedef struct
482 {
483 UWORD16 up;
484 UWORD16 down;
485 }
486 T_RAMP_DELAY;
487
488 typedef struct
489 {
490 UWORD16 arfcn_limit;
491 WORD16 chan_cal;
492 }
493 T_TX_CHAN_CAL;
494
495 // RF TX structure
496 typedef struct
497 {
498 T_RAMP_DELAY ramp_delay;
499 UWORD8 guard_bits; // number of guard bits needed for ramp up
500 UWORD8 prg_tx;
501 }
502 T_RF_TX; //common
503
504 // RF TX structure
505 typedef struct
506 {
507 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
508 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
509 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
510 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
511 }
512 T_RF_TX_BAND;
513
514 // band structure
515 typedef struct
516 {
517 T_RF_RX_BAND rx;
518 T_RF_TX_BAND tx;
519 UWORD8 swap_iq;
520 }
521 T_RF_BAND;
522
523 // RF structure
524 typedef struct
525 {
526 // common for all bands
527 UWORD16 rf_revision;
528 UWORD16 radio_band_support;
529 T_RF_RX rx;
530 T_RF_TX tx;
531 T_AFC_PARAMS afc;
532 }
533 T_RF;
534
535 /************************************/
536 /* MADC definitions */
537 /************************************/
538 // Omega: 5 external channels if touch screen not used, 3 otherwise
539 enum ADC_INDEX {
540 ADC_VBAT,
541 ADC_VCHARG,
542 ADC_ICHARG,
543 ADC_VBACKUP,
544 ADC_BATTYP,
545 ADC_BATTEMP,
546 ADC_ADC3, // name of this ??
547 ADC_RFTEMP,
548 ADC_ADC4,
549 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
550 };
551
552 typedef struct
553 {
554 WORD16 converted[ADC_INDEX_END]; // converted
555 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
556 }
557 T_ADC;
558
559 /************************************/
560 /* MADC calibration */
561 /************************************/
562 typedef struct
563 {
564 UWORD16 a[ADC_INDEX_END];
565 WORD16 b[ADC_INDEX_END];
566 }
567 T_ADCCAL;
568
569 // Conversion table: ADC value -> temperature
570 typedef struct
571 {
572 UWORD16 adc; // ADC reading is 10 bits
573 WORD16 temp; // temp is in approx. range -30..+80
574 }
575 T_TEMP;
576
577 typedef struct
578 {
579 char *name;
580 void *addr;
581 int size;
582 }
583 T_CONFIG_FILE;
584
585 typedef struct
586 {
587 char *name; // name of ffs file suffix
588 T_RF_BAND *addr; // address to default flash structure
589 UWORD16 max_carrier; // max carrier
590 UWORD16 max_txpwr; // max tx power
591 }
592 T_BAND_CONFIG;
593
594 typedef struct
595 {
596 UWORD8 band[GSM_BANDS]; // index to band address
597 UWORD8 txpwr_tp; // tx power turning point
598 UWORD16 first_arfcn; // first index
599 }
600 T_STD_CONFIG;
601 enum GSMBAND_DEF
602 {
603 BAND_NONE,
604 BAND_EGSM900,
605 BAND_DCS1800,
606 BAND_PCS1900,
607 BAND_GSM850,
608 // put new bands here
609 BAND_GSM900 //last entry
610 };
611
612 /************************************/
613 /* ABB (Omega) Initialization */
614 /************************************/
615
616 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
617 #define ABB_TABLE_SIZE 16
618 #elif (ANLG_FAM == 3)
619 #define ABB_TABLE_SIZE 22
620 #endif
621
622 // Note that this translation is probably not needed at all. But until L1 is
623 // (maybe) changed to simply initialize the ABB from a table of words, we
624 // use this to make things more easy-readable.
625
626 #if (ANLG_FAM == 1)
627 enum ABB_REGISTERS {
628 ABB_AFCCTLADD = 0,
629 ABB_VBUCTRL,
630 ABB_VBDCTRL,
631 ABB_BBCTRL,
632 ABB_APCOFF,
633 ABB_BULIOFF,
634 ABB_BULQOFF,
635 ABB_DAI_ON_OFF,
636 ABB_AUXDAC,
637 ABB_VBCTRL,
638 ABB_APCDEL1
639 };
640 #elif (ANLG_FAM == 2)
641 enum ABB_REGISTERS {
642 ABB_AFCCTLADD = 0,
643 ABB_VBUCTRL,
644 ABB_VBDCTRL,
645 ABB_BBCTRL,
646 ABB_BULGCAL,
647 ABB_APCOFF,
648 ABB_BULIOFF,
649 ABB_BULQOFF,
650 ABB_DAI_ON_OFF,
651 ABB_AUXDAC,
652 ABB_VBCTRL1,
653 ABB_VBCTRL2,
654 ABB_APCDEL1,
655 ABB_APCDEL2
656 };
657 #elif (ANLG_FAM == 3)
658 enum ABB_REGISTERS {
659 ABB_AFCCTLADD = 0,
660 ABB_VBUCTRL,
661 ABB_VBDCTRL,
662 ABB_BBCTRL,
663 ABB_BULGCAL,
664 ABB_APCOFF,
665 ABB_BULIOFF,
666 ABB_BULQOFF,
667 ABB_DAI_ON_OFF,
668 ABB_AUXDAC,
669 ABB_VBCTRL1,
670 ABB_VBCTRL2,
671 ABB_APCDEL1,
672 ABB_APCDEL2,
673 ABB_VBPOP,
674 ABB_VAUDINITD,
675 ABB_VAUDCTRL,
676 ABB_VAUOCTRL,
677 ABB_VAUSCTRL,
678 ABB_VAUDPLL
679 };
680 #endif
681 #endif