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comparison src/cs/layer1/cust0/l1_rf2.h @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
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-1:000000000000 0:92470e5d0b9e
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename l1_rf2.h
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8
9 #ifndef __L1_RF_H__
10 #define __L1_RF_H__
11
12 /************************************/
13 /************************************/
14 // # define
15 /************************************/
16 /************************************/
17 /* SYNTHESIZER setup time... */
18 /************************************/
19
20 #define RX_SYNTH_SETUP_TIME 215L // Synthesizer setup time in quarter bit.
21 #define TX_SYNTH_SETUP_TIME 270L // Synthesizer setup time in quarter bit.
22
23 /************************************/
24 /* time for TPU scenario ending... */
25 /************************************/
26
27 #define RX_TPU_SCENARIO_ENDING (4-3) // execution time of BDLENA down
28 // minus serialization time
29 #define TX_TPU_SCENARIO_ENDING (4-3) // execution time of BULON down
30 // minus serialization time
31
32 /************************************/
33 /* TXPWR configuration... */
34 /************************************/
35
36 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
37 #define FIXED_TXPWR ((0x1FF << 6) | AUXAPC | FALSE) // TXPWR=15
38 // #define FIXED_TXPWR ((0xFF << 6) | AUXAPC | FALSE)
39 #endif
40
41 /************************************/
42 /* TX Propagation delay... */
43 /************************************/
44
45 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
46 // #define PRG_TX ( 52L )
47 #define PRG_TX ( 8L)
48 #endif
49
50 /************************************/
51 /*(ANALOG)delay (in qbits) */
52 /************************************/
53
54 #define UL_ABB_DELAY 0 // modulator input to output delay
55
56 /************************************/
57 /* Initial value for AFC... */
58 /************************************/
59
60 #define EEPROM_AFC ((-952-2400)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
61
62 #define SETUP_AFC_AND_RF 2 // time to have a stable output of the AFC and RF Band Gap(in Frames)
63 // !! minimum Value : 1 Frame due to the fact there is no
64 // hisr() in the first wake-up frame !!!!
65
66 #if (ANLG_FAM == 1)
67 /************************************/
68 /* Omega power on... */
69 /************************************/
70 // Omega registers values will be programmed at 1st DSP communication interrupt
71 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
72 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
73 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Uplink gain amp 3 dB, Sidetone gain to -17 dB
74 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // Downlink gain amp 0dB, Volume control -12 dB
75 #define C_BBCTRL ((0x000 << 6) | BBCTRL | TRUE ) // value at reset
76 #define C_APCOFF ((0x000 << 6) | APCOFF | TRUE )
77 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
78 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
79 #define C_DAI_ON_OFF 0x0000 // value at reset
80 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
81 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE ) // VULSWITCH=0, VDLAUX=1, VDLEAR=1
82
83 // BULRUDEL will be initialized on rach only ....
84 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | FALSE)
85 #endif
86
87 #if (ANLG_FAM == 2)
88 /************************************/
89 /* Iota power on... */
90 /************************************/
91 // Iota registers values will be programmed at 1st DSP communication interrupt
92 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
93 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
94 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Uplink gain amp 3 dB, Sidetone gain to -17 dB
95 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // Downlink gain amp 0dB, Volume control -12 dB
96 #define C_BBCTRL ((0x000 << 6) | BBCTRL | TRUE ) // value at reset
97 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
98 #define C_APCOFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
99 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
100 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
101 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
102 #define C_DAI_ON_OFF 0x0000 // value at reset
103 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
104 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE ) // MICBIASEL=0, VDLHSO=0, MICAUX=0
105
106 // BULRUDEL will be initialized on rach only ....
107 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | TRUE )
108 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE )
109 #endif
110
111 #if (ANLG_FAM == 3)
112 // SYREN registers values will be programmed at 1st DSP communication interrupt
113 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
114 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
115 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
116 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
117 #define C_BBCTRL ((0x000 << 6) | BBCTRL | TRUE ) // Internal autocalibration, Output common mode=1.35V
118 // Monoslot, Vpp=8/15*Vref
119 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
120 #define C_APCOFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
121 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
122 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
123 #define C_DAI_ON_OFF 0x0000 // value at reset
124 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
125 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1 AUXI 28,2 dB
126 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE ) // HSMIC on, SPKG gain @ 2,5dB
127
128 // BULRUDEL will be initialized on rach only ....
129 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | TRUE )
130 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE )
131
132 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE ) // HSOAUTO enabled only
133 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
134 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE ) // Init to zero
135 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE ) // Speech on all outputs
136 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE ) // Init to zero
137 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE ) // Init to zero
138
139 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
140
141 #define C_BBCFG 0x44 // Syren Like BDLF Filter - DC OFFSET removal OFF
142
143 #endif
144
145 /************************************/
146 /* Automatic frequency compensation */
147 /************************************/
148
149 /********************* C_Psi_sta definition *****************************/
150 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
151 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
152 /* regarding Vega V/N = 2.4/4096 */
153 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
154 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
155 /* = 0.000195748 */
156 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
157 /************************************************************************/
158
159 #define C_Psi_sta_inv 9307L // (1/C_Psi_sta)
160 #define C_Psi_st 6 // C_Psi_sta * 0.8 F0.16
161 #define C_Psi_st_32 369173L // F0.32
162 #define C_Psi_st_inv 11634L // (1/C_Psi_st)
163
164 typedef struct
165 {
166 WORD16 eeprom_afc;
167 UWORD32 psi_sta_inv;
168 UWORD32 psi_st;
169 UWORD32 psi_st_32;
170 UWORD32 psi_st_inv;
171 }
172 T_AFC_PARAMS;
173
174 /************************************/
175 /* Swap IQ definitions... */
176 /************************************/
177 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
178
179 #define SWAP_IQ_GSM 0
180 #define SWAP_IQ_DCS 0
181 #define SWAP_IQ_PCS 0 // not supported by rf2
182 #define SWAP_IQ_GSM850 0 // not supported by rf2
183
184 /************************************/
185 /************************************/
186 // typedef
187 /************************************/
188 /************************************/
189
190 /*************************************************************/
191 /* Define structure for apc of TX Power ******/
192 /*************************************************************/
193 typedef struct
194 { // pcm-file "rf/tx/level.gsm|dcs"
195 UWORD16 apc; // 0..31
196 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
197 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
198 }
199 T_TX_LEVEL;
200
201 /************************************/
202 /* Automatic Gain Control */
203 /************************************/
204 /* Define structure for sub-band definition of TX Power ******/
205 typedef struct
206 {
207 UWORD16 upper_bound; // highest physical arfcn of the sub-band
208 WORD16 agc_calib; // AGC for each TXPWR
209 }T_RF_AGC_BAND;
210
211 /************************************/
212 /* Ramp definitions */
213 /************************************/
214
215 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
216 typedef struct
217 {
218 UWORD8 ramp_up [16]; // Ramp-up profile
219 UWORD8 ramp_down [16]; // Ramp-down profile
220 }
221 T_TX_RAMP;
222 #endif
223
224
225 // RF structure definition
226 //========================
227
228 enum RfRevision {
229 RF_IGNORE = 0x0000,
230 RF_SL2 = 0x1000,
231 RF_GAIA_20X = 0x2000,
232 RF_GAIA_20A = 0x2001,
233 RF_GAIA_20B = 0x2002,
234 RF_ATLAS_20B = 0x2020,
235 RF_PASCAL_20 = 0x2030
236 };
237
238 // Number of bands supported
239 #define GSM_BANDS 2
240
241 #define MULTI_BAND1 0
242 #define MULTI_BAND2 1
243 // RF table sizes
244 #define RF_RX_CAL_CHAN_SIZE 9 // number of AGC sub-bands
245 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
246
247 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
248 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
249 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
250 #define RF_TX_RAMP_SIZE 15 // number of ramp definitions
251 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
252
253 #define AGC_TABLE_SIZE 1
254
255 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
256
257
258 // RX parameters and tables
259 //-------------------------
260
261 // AGC parameters and tables
262 typedef struct
263 {
264 UWORD16 low_agc_noise_thr;
265 UWORD16 high_agc_sat_thr;
266 UWORD16 low_agc;
267 UWORD16 high_agc;
268 UWORD8 il2agc_pwr[121];
269 UWORD8 il2agc_max[121];
270 UWORD8 il2agc_av[121];
271 }
272 T_AGC;
273
274 // Calibration parameters
275 typedef struct
276 {
277 UWORD16 g_magic;
278 UWORD16 lna_att;
279 UWORD16 lna_switch_thr_low;
280 UWORD16 lna_switch_thr_high;
281 }
282 T_RX_CAL_PARAMS;
283
284 // RX temperature compensation
285 typedef struct
286 {
287 WORD16 temperature;
288 WORD16 agc_calib;
289 }
290 T_RX_TEMP_COMP;
291
292 // RF RX structure
293 typedef struct
294 {
295 T_AGC agc;
296 }
297 T_RF_RX; //common
298
299 // RF RX structure
300 typedef struct
301 {
302 T_RX_CAL_PARAMS rx_cal_params;
303 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
304 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
305 }
306 T_RF_RX_BAND;
307
308
309 // TX parameters and tables
310 //-------------------------
311
312 // TX temperature compensation
313 typedef struct
314 {
315 WORD16 temperature;
316 #if (ORDER2_TX_TEMP_CAL==1)
317 WORD16 a;
318 WORD16 b;
319 WORD16 c;
320 #else
321 WORD16 apc_calib;
322 #endif
323 }
324 T_TX_TEMP_CAL;
325
326 // Ramp up and ramp down delay
327 typedef struct
328 {
329 UWORD16 up;
330 UWORD16 down;
331 }
332 T_RAMP_DELAY;
333
334 typedef struct
335 {
336 UWORD16 arfcn_limit;
337 WORD16 chan_cal;
338 }
339 T_TX_CHAN_CAL;
340
341 // RF TX structure
342 typedef struct
343 {
344 T_RAMP_DELAY ramp_delay;
345 UWORD8 guard_bits; // number of guard bits needed for ramp up
346 UWORD8 prg_tx;
347 }
348 T_RF_TX; //common
349
350 // RF TX structure
351 typedef struct
352 {
353 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
354 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
355 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
356 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
357 }
358 T_RF_TX_BAND;
359
360 // band structure
361 typedef struct
362 {
363 T_RF_RX_BAND rx;
364 T_RF_TX_BAND tx;
365 UWORD8 swap_iq;
366 }
367 T_RF_BAND;
368
369 // RF structure
370 typedef struct
371 {
372 // common for all bands
373 UWORD16 rf_revision;
374 UWORD16 radio_band_support;
375 T_RF_RX rx;
376 T_RF_TX tx;
377 T_AFC_PARAMS afc;
378 }
379 T_RF;
380
381 /************************************/
382 /* MADC definitions */
383 /************************************/
384 // Omega: 5 external channels if touch screen not used, 3 otherwise
385 enum ADC_INDEX {
386 ADC_VBAT,
387 ADC_VCHARG,
388 ADC_ICHARG,
389 ADC_VBACKUP,
390 ADC_BATTYP,
391 ADC_BATTEMP,
392 ADC_RFTEMP,
393 ADC_ADC3,
394 ADC_ADC4,
395 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
396 };
397
398 typedef struct
399 {
400 WORD16 converted[ADC_INDEX_END]; // converted
401 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
402 }
403 T_ADC;
404
405 /************************************/
406 /* MADC calibration */
407 /************************************/
408 typedef struct
409 {
410 UWORD16 a[ADC_INDEX_END];
411 WORD16 b[ADC_INDEX_END];
412 }
413 T_ADCCAL;
414
415 // Conversion table: ADC value -> temperature
416 typedef struct
417 {
418 UWORD16 adc; // ADC reading is 10 bits
419 WORD16 temp; // temp is in approx. range -30..+80
420 }
421 T_TEMP;
422
423 typedef struct
424 {
425 char *name;
426 void *addr;
427 int size;
428 }
429 T_CONFIG_FILE;
430
431 typedef struct
432 {
433 char *name; // name of ffs file suffix
434 T_RF_BAND *addr; // address to default flash structure
435 UWORD16 max_carrier; // max carrier
436 UWORD16 max_txpwr; // max tx power
437 }
438 T_BAND_CONFIG;
439
440 typedef struct
441 {
442 UWORD8 band[GSM_BANDS]; // index to band address
443 UWORD8 txpwr_tp; // tx power turning point
444 UWORD16 first_arfcn; // first index
445 }
446 T_STD_CONFIG;
447
448 enum GSMBAND_DEF
449 {
450 BAND_NONE,
451 BAND_EGSM900,
452 BAND_DCS1800,
453 BAND_PCS1900,
454 BAND_GSM850,
455 // put new bands here
456 BAND_GSM900 //last entry
457 };
458
459
460 /************************************/
461 /* ABB (Omega) Initialization */
462 /************************************/
463 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
464 #define ABB_TABLE_SIZE 16
465 #endif
466
467 #if (ANLG_FAM == 3)
468 #define ABB_TABLE_SIZE 22
469 #endif
470
471 // Note that this translation is probably not needed at all. But until L1 is
472 // (maybe) changed to simply initialize the ABB from a table of words, we
473 // use this to make things more easy-readable.
474 #if (ANLG_FAM == 1)
475 enum ABB_REGISTERS {
476 ABB_AFCCTLADD = 0,
477 ABB_VBUCTRL,
478 ABB_VBDCTRL,
479 ABB_BBCTRL,
480 ABB_APCOFF,
481 ABB_BULIOFF,
482 ABB_BULQOFF,
483 ABB_DAI_ON_OFF,
484 ABB_AUXDAC,
485 ABB_VBCTRL,
486 ABB_APCDEL1
487 };
488 #elif (ANLG_FAM == 2)
489 enum ABB_REGISTERS {
490 ABB_AFCCTLADD = 0,
491 ABB_VBUCTRL,
492 ABB_VBDCTRL,
493 ABB_BBCTRL,
494 ABB_BULGCAL,
495 ABB_APCOFF,
496 ABB_BULIOFF,
497 ABB_BULQOFF,
498 ABB_DAI_ON_OFF,
499 ABB_AUXDAC,
500 ABB_VBCTRL1,
501 ABB_VBCTRL2,
502 ABB_APCDEL1,
503 ABB_APCDEL2
504 };
505 #elif (ANLG_FAM == 3)
506 enum ABB_REGISTERS {
507 ABB_AFCCTLADD = 0,
508 ABB_VBUCTRL,
509 ABB_VBDCTRL,
510 ABB_BBCTRL,
511 ABB_BULGCAL,
512 ABB_APCOFF,
513 ABB_BULIOFF,
514 ABB_BULQOFF,
515 ABB_DAI_ON_OFF,
516 ABB_AUXDAC,
517 ABB_VBCTRL1,
518 ABB_VBCTRL2,
519 ABB_APCDEL1,
520 ABB_APCDEL2,
521 ABB_VBPOP,
522 ABB_VAUDINITD,
523 ABB_VAUDCTRL,
524 ABB_VAUOCTRL,
525 ABB_VAUSCTRL,
526 ABB_VAUDPLL
527 };
528 #endif
529 #endif