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comparison src/cs/layer1/cust0/l1_rf8.h @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
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-1:000000000000 0:92470e5d0b9e
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename l1_rf8.h
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8
9 #ifndef __L1_RF_H__
10 #define __L1_RF_H__
11
12 /************************************/
13 /* SYNTHESIZER setup time... */
14 /************************************/
15
16 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1) //RX Synthesizer setup time in qbit.
17 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
18
19
20 /************************************/
21 /* time for TPU scenario ending... */
22 /************************************/
23
24 #define RX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 // execution time of BDLENA down
25 // minus serialization time
26 #define TX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 // execution time of BULON down
27 // minus serialization time
28
29 /******************************************************/
30 /* TXPWR configuration... */
31 /* Fixed TXPWR value when GSM management is disabled. */
32 /******************************************************/
33
34 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
35 // #define FIXED_TXPWR ((0xFC << 6) | AUXAPC | FALSE) // TXPWR=10, value=252
36 // #define FIXED_TXPWR ((0x28 << 6) | AUXAPC | FALSE)
37 #define FIXED_TXPWR ((0x68 << 6) | AUXAPC | FALSE) // TXPWR=15
38 #endif
39
40
41 /************************************/
42 /*(ANALOG)delay (in qbits) */
43 /************************************/
44
45 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
46 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
47 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
48
49 #if (ANLG_FAM == 1)
50 #define UL_ABB_DELAY 0 // modulator input to output delay, theoretical value is 6, needs to be checked
51 #endif
52
53 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
54 #define UL_ABB_DELAY 3 // modulator input to output delay
55 #endif
56
57 /************************************/
58 /* TX Propagation delay... */
59 /************************************/
60
61 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
62 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
63 #endif
64
65 /************************************/
66 /* Initial value for APC DELAY */
67 /************************************/
68
69 #if (ANLG_FAM == 1)
70 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
71 #define APCDEL_DOWN 2 // minimum value: 2
72 #define APCDEL_UP (6+5) // minimum value: 6
73 #endif
74
75 #if (ANLG_FAM == 2) || (ANLG_FAM == 3)
76 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
77 #define APCDEL_DOWN (2+0) // minimum value: 2
78 #define APCDEL_UP (6+2) // minimum value: 6
79 #endif
80
81 #define GUARD_BITS 7
82
83 /************************************/
84 /* Initial value for AFC... */
85 /************************************/
86
87 #define EEPROM_AFC ((-1180)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
88
89 #define SETUP_AFC_AND_RF 2 // time to have a stable output of the AFC and RF BAND GAP(in Frames)
90 // !! minimum Value : 1 Frame due to the fact there is no
91 // hisr() in the first wake-up frame !!!!
92
93 /************************************/
94 /* Baseband registers */
95 /************************************/
96
97 #if (ANLG_FAM == 1)
98 // Omega registers values will be programmed at 1st DSP communication interrupt
99 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
100 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
101 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
102 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
103 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE)
104 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
105 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
106 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
107 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
108 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
109
110 // BULRUDEL will be initialized on rach only ....
111 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
112 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
113 #endif
114
115 #if (ANLG_FAM == 2)
116 // IOTA registers values will be programmed at 1st DSP communication interrupt
117 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
118 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
119 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
120 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
121 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE)
122 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
123 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
124 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
125 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
126 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
127 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE ) // MICBIASEL=0, VDLHSO=0, MICAUX=0
128
129 // BULRUDEL will be initialized on rach only ....
130 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
131 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE ) //
132
133 #define C_BBCTRL ((0x0C1 << 6) | BBCTRL | TRUE ) // Internal autocalibration, Output common mode=1.35V
134 // Monoslot, Vpp=8/15*Vref
135 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
136 #endif
137
138 #if (ANLG_FAM == 3)
139 // SYREN registers values will be programmed at 1st DSP communication interrupt
140 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
141 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
142 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone - 17 dB, PGA_UL 3dB
143 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
144 #define C_APCOFF ((0x07C << 6) | APCOFF | TRUE)
145 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE ) // value at reset
146 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE ) // value at reset
147 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE ) // value at reset
148 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE ) // value at reset
149 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE ) // VULSWITCH=1 AUXI 28,2 dB
150 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE ) // HSMIC on, SPKG gain @ 2,5dB
151
152 // BULRUDEL will be initialized on rach only ....
153 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6)<<6) | APCDEL1)
154 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE )
155 #define C_BBCTRL ((0x0C1 << 6) | BBCTRL | TRUE ) // Internal autocalibration, Output common mode=1.35V
156 // Monoslot, Vpp=8/15*Vref
157 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
158
159 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE ) // HSOAUTO enabled only
160 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
161 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE ) // Init to zero
162 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE ) // Speech on all outputs
163 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE ) // Init to zero
164 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE ) // Init to zero
165
166 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
167
168 #define C_BBCFG 0x44 // Syren Like BDLF Filter - DC OFFSET removal OFF
169
170 #endif
171
172
173 /************************************/
174 /* Automatic frequency compensation */
175 /************************************/
176 /********************* C_Psi_sta definition *****************************/
177 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
178 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
179 /* regarding Vega V/N = 2.4/4096 */
180 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
181 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
182 /* = 0.000195748 */
183 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
184 /************************************************************************/
185
186 #define C_Psi_sta_inv 11677L // (1/C_Psi_sta)
187 #define C_Psi_st 4L // C_Psi_sta * 0.8 F0.16
188 #define C_Psi_st_32 294257L // F0.32
189 #define C_Psi_st_inv 14596L // (1/C_Psi_st)
190
191 typedef struct
192 {
193 WORD16 eeprom_afc;
194 UWORD32 psi_sta_inv;
195 UWORD32 psi_st;
196 UWORD32 psi_st_32;
197 UWORD32 psi_st_inv;
198 }
199 T_AFC_PARAMS;
200
201 /************************************/
202 /* Swap IQ definitions... */
203 /************************************/
204 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
205
206 #define SWAP_IQ_GSM 0
207 #define SWAP_IQ_DCS 3
208 #define SWAP_IQ_PCS 3
209 #define SWAP_IQ_GSM850 0 //TBD
210
211 /************************************/
212 /* RF bands supported */
213 /************************************/
214
215 #define RF_HW_BAND_SUPPORT (0x0020 | 0x0004) // radio_band_support E-GSM/DCS + PC
216
217 /************************************/
218 /************************************/
219 // typedef
220 /************************************/
221 /************************************/
222
223 /*************************************************************/
224 /* Define structure for apc of TX Power ******/
225 /*************************************************************/
226
227 typedef struct
228 { // pcm-file "rf/tx/level.gsm|dcs"
229 UWORD16 apc; // 0..31
230 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
231 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
232 }
233 T_TX_LEVEL;
234
235 /************************************/
236 /* Automatic Gain Control */
237 /************************************/
238 /* Define structure for sub-band definition of TX Power ******/
239
240 typedef struct
241 {
242 UWORD16 upper_bound; //highest physical arfcn of the sub-band
243 WORD16 agc_calib; // AGC for each TXPWR
244 }T_RF_AGC_BAND;
245
246 /************************************/
247 /* Ramp definitions */
248 /************************************/
249
250 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
251 typedef struct
252 {
253 UWORD8 ramp_up [16]; // Ramp-up profile
254 UWORD8 ramp_down [16]; // Ramp-down profile
255 }
256 T_TX_RAMP;
257 #endif
258
259
260 // RF structure definition
261 //========================
262
263 enum RfRevision {
264 RF_IGNORE = 0x0000,
265 RF_SL2 = 0x1000,
266 RF_GAIA_20X = 0x2000,
267 RF_GAIA_20A = 0x2001,
268 RF_GAIA_20B = 0x2002,
269 RF_ATLAS_20B = 0x2020,
270 RF_PASCAL_20 = 0x2030
271 };
272
273 // Number of bands supported
274 #define GSM_BANDS 2
275
276 #define MULTI_BAND1 0
277 #define MULTI_BAND2 1
278
279 // RF table sizes
280 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
281 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
282
283 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
284 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
285 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
286 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
287 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
288
289 #define AGC_TABLE_SIZE 36
290
291 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
292
293
294 // RX parameters and tables
295 //-------------------------
296
297 // AGC parameters and tables
298 typedef struct
299 {
300 UWORD16 low_agc_noise_thr;
301 UWORD16 high_agc_sat_thr;
302 UWORD16 low_agc;
303 UWORD16 high_agc;
304 UWORD8 il2agc_pwr[121];
305 UWORD8 il2agc_max[121];
306 UWORD8 il2agc_av[121];
307 }
308 T_AGC;
309
310 // Calibration parameters
311 typedef struct
312 {
313 UWORD16 g_magic;
314 UWORD16 lna_att;
315 UWORD16 lna_switch_thr_low;
316 UWORD16 lna_switch_thr_high;
317 }
318 T_RX_CAL_PARAMS;
319
320 // RX temperature compensation
321 typedef struct
322 {
323 WORD16 temperature;
324 WORD16 agc_calib;
325 }
326 T_RX_TEMP_COMP;
327
328 // RF RX structure
329 typedef struct
330 {
331 T_AGC agc;
332 }
333 T_RF_RX; //common
334
335 // RF RX structure
336 typedef struct
337 {
338 T_RX_CAL_PARAMS rx_cal_params;
339 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
340 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
341 }
342 T_RF_RX_BAND;
343
344
345 // TX parameters and tables
346 //-------------------------
347
348 // TX temperature compensation
349 typedef struct
350 {
351 WORD16 temperature;
352 #if (ORDER2_TX_TEMP_CAL==1)
353 WORD16 a;
354 WORD16 b;
355 WORD16 c;
356 #else
357 WORD16 apc_calib;
358 #endif
359 }
360 T_TX_TEMP_CAL;
361
362
363 // Ramp up and ramp down delay
364 typedef struct
365 {
366 UWORD16 up;
367 UWORD16 down;
368 }
369 T_RAMP_DELAY;
370
371 typedef struct
372 {
373 UWORD16 arfcn_limit;
374 WORD16 chan_cal;
375 }
376 T_TX_CHAN_CAL;
377
378 // RF TX structure
379 typedef struct
380 {
381 T_RAMP_DELAY ramp_delay;
382 UWORD8 guard_bits; // number of guard bits needed for ramp up
383 UWORD8 prg_tx;
384 }
385 T_RF_TX; //common
386
387 // RF TX structure
388 typedef struct
389 {
390 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
391 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
392 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
393 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
394 }
395 T_RF_TX_BAND;
396
397 // band structure
398 typedef struct
399 {
400 T_RF_RX_BAND rx;
401 T_RF_TX_BAND tx;
402 UWORD8 swap_iq;
403 }
404 T_RF_BAND;
405
406 // RF structure
407 typedef struct
408 {
409 // common for all bands
410 UWORD16 rf_revision;
411 UWORD16 radio_band_support;
412 T_RF_RX rx;
413 T_RF_TX tx;
414 T_AFC_PARAMS afc;
415 }
416 T_RF;
417
418 /************************************/
419 /* MADC definitions */
420 /************************************/
421 // Omega: 5 external channels if touch screen not used, 3 otherwise
422 enum ADC_INDEX {
423 ADC_VBAT,
424 ADC_VCHARG,
425 ADC_ICHARG,
426 ADC_VBACKUP,
427 ADC_BATTYP,
428 ADC_BATTEMP,
429 ADC_ADC3, // name of this ??
430 ADC_RFTEMP,
431 ADC_ADC4,
432 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
433 };
434
435 typedef struct
436 {
437 WORD16 converted[ADC_INDEX_END]; // converted
438 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
439 }
440 T_ADC;
441
442 /************************************/
443 /* MADC calibration */
444 /************************************/
445 typedef struct
446 {
447 UWORD16 a[ADC_INDEX_END];
448 WORD16 b[ADC_INDEX_END];
449 }
450 T_ADCCAL;
451
452 // Conversion table: ADC value -> temperature
453 typedef struct
454 {
455 UWORD16 adc; // ADC reading is 10 bits
456 WORD16 temp; // temp is in approx. range -30..+80
457 }
458 T_TEMP;
459
460 typedef struct
461 {
462 char *name;
463 void *addr;
464 int size;
465 }
466 T_CONFIG_FILE;
467
468 typedef struct
469 {
470 char *name; // name of ffs file suffix
471 T_RF_BAND *addr; // address to default flash structure
472 UWORD16 max_carrier; // max carrier
473 UWORD16 max_txpwr; // max tx power
474 }
475 T_BAND_CONFIG;
476
477 typedef struct
478 {
479 UWORD8 band[GSM_BANDS]; // index to band address
480 UWORD8 txpwr_tp; // tx power turning point
481 UWORD16 first_arfcn; // first index
482 }
483 T_STD_CONFIG;
484
485 enum GSMBAND_DEF
486 {
487 BAND_NONE,
488 BAND_EGSM900,
489 BAND_DCS1800,
490 BAND_PCS1900,
491 BAND_GSM850,
492 // put new bands here
493 BAND_GSM900 //last entry
494 };
495
496
497 /************************************/
498 /* ABB (Omega) Initialization */
499 /************************************/
500
501 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
502 #define ABB_TABLE_SIZE 16
503 #endif
504
505 #if (ANLG_FAM == 3)
506 #define ABB_TABLE_SIZE 22
507 #endif
508
509 // Note that this translation is probably not needed at all. But until L1 is
510 // (maybe) changed to simply initialize the ABB from a table of words, we
511 // use this to make things more easy-readable.
512
513 #if (ANLG_FAM == 1)
514 enum ABB_REGISTERS {
515 ABB_AFCCTLADD = 0,
516 ABB_VBUCTRL,
517 ABB_VBDCTRL,
518 ABB_BBCTRL,
519 ABB_APCOFF,
520 ABB_BULIOFF,
521 ABB_BULQOFF,
522 ABB_DAI_ON_OFF,
523 ABB_AUXDAC,
524 ABB_VBCTRL,
525 ABB_APCDEL1
526 };
527 #endif
528
529 #if (ANLG_FAM == 2)
530 enum ABB_REGISTERS {
531 ABB_AFCCTLADD = 0,
532 ABB_VBUCTRL,
533 ABB_VBDCTRL,
534 ABB_BBCTRL,
535 ABB_BULGCAL,
536 ABB_APCOFF,
537 ABB_BULIOFF,
538 ABB_BULQOFF,
539 ABB_DAI_ON_OFF,
540 ABB_AUXDAC,
541 ABB_VBCTRL1,
542 ABB_VBCTRL2,
543 ABB_APCDEL1,
544 ABB_APCDEL2
545 };
546 #endif
547
548 #if (ANLG_FAM == 3)
549 enum ABB_REGISTERS {
550 ABB_AFCCTLADD = 0,
551 ABB_VBUCTRL,
552 ABB_VBDCTRL,
553 ABB_BBCTRL,
554 ABB_BULGCAL,
555 ABB_APCOFF,
556 ABB_BULIOFF,
557 ABB_BULQOFF,
558 ABB_DAI_ON_OFF,
559 ABB_AUXDAC,
560 ABB_VBCTRL1,
561 ABB_VBCTRL2,
562 ABB_APCDEL1,
563 ABB_APCDEL2,
564 ABB_VBPOP,
565 ABB_VAUDINITD,
566 ABB_VAUDCTRL,
567 ABB_VAUOCTRL,
568 ABB_VAUSCTRL,
569 ABB_VAUDPLL
570 };
571 #endif
572 #endif
573