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comparison src/cs/layer1/tpu_drivers/source/tpudrv.h @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
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1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename tpudrv.h
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8
9 /*
10 * Device addresses - GCS000
11 */
12 // GSM 1.5 : TPU / TSP addresses
13 //-------------------------------------
14
15 #if ((CHIPSET ==2) || (CHIPSET == 3) || (CHIPSET == 4))
16 #define TPU_ADDR 0xFFFE0000l // Hercule / Ulysse / Samson
17
18 #define TPU_RAM (TPU_ADDR + 0x1400)
19
20 #define TPU_REG (TPU_ADDR + 0x1000)
21 #define TSP_REG (TPU_ADDR + 0x0800)
22 #define TPU_TIM (TPU_ADDR + 0x2000)
23
24 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
25 #define TPU_ADDR 0xFFFF0000l // Strobe 1 address
26
27 #define TPU_RAM 0xFFFF9000l // TPU RAM
28
29 #define TPU_REG (TPU_ADDR + 0x1000) // TPU register
30 #define TSP_REG 0xFFFE0800l // TSP register
31 #define TPU_TIM 0xFFFE2000l // ULPD register
32
33 #endif
34
35
36 /*
37 * Macros for defining TPU instructions
38 */
39 #define TPU_SLEEP 0
40 #define TPU_MOVE(addr,data) (0x8000 | ((data)<<5) | (addr))
41 #define TPU_AT(time) (0x2000 | (((time + 5000) % 5000)))
42 #define TPU_FAT(time) (0x2000 | (time)) // Fast version without modulo
43 #define TPU_SYNC(time) (0x6000 | (time))
44 #define TPU_WAIT(time) (0xA000 | (time))
45 #define TPU_OFFSET(time) (0x4000 | (time))
46 #define MOD5000(a) (((a) + 5000) % 5000)
47
48
49 /*
50 * TSP registers - defined in GCS004 - Time Serial Port
51 */
52 /*
53 * in TPU address space
54 */
55 // GSM 1.5 : TSP_TX_REG_1/2/3/4 instead of TSP_TX_U/M/L
56 // added TSP_SPI_SET1/2/3 to ctrl up to 5 periph.
57 //-----------------------------------------------------
58 #define TSP_CTRL1 0x00
59 #define TSP_CTRL2 0x01
60 #define TSP_TX_REG_1 0x04
61 #define TSP_TX_REG_2 0x03
62 #define TSP_TX_REG_3 0x02
63 #define TSP_TX_REG_4 0x05
64 #define TSP_ACT 0x06
65 #define TSP_ACTX 0x07
66 #define TSP_GAUGING_EN 0x11
67 #define TSP_SPI_SET1 0x09
68 #define TSP_SPI_SET2 0x0A
69 #define TSP_SPI_SET3 0x0B
70 #define TPU_IT_DSP_PG 0x10
71 #define TSP_GAUGING_EN 0x11
72
73 /*
74 * in ARM address space - defined in HYP004
75 */
76 #define TSP_RX_LSB (TSP_REG + 0x00)
77
78 #define TSP_RX_MSB (TSP_REG + 0x02)
79
80 #define TSP_TX_LSB (TSP_REG + 0x0c)
81
82 #define TSP_TX_MSB (TSP_REG + 0x0a)
83
84
85 /*
86 * TSP registers bit definitions
87 */
88 #define TC1_DEVICE0 0x00
89 #define TC1_DEVICE1 0x20
90 #define TC1_DEVICE2 0x40
91 #define TC1_DEVICE3 0x60
92 #define TC1_DEVICE4 0x80
93 #define TC2_RD 0x01
94 #define TC2_WR 0x02
95 #define TC2_EDGE_TRIG 0x40
96 #define TC2_RISING 0x80
97 #define TSP_CLK_RISE 0x01
98 #define TSP_ENA_POS 0x02
99 #define TSP_ENA_EDGE 0x04
100 #define GAUGING_START 0x01
101 #define GAUGING_STOP 0x00
102 #define TSP_ENA_POS_MSB 0x20
103
104
105
106 /*
107 * TPU registers - defined in HYP002
108 */
109 // GSM 1.5 : TPU reg are 16-bit access
110 //---------------------------------------
111 #define TPU_CTRL (TPU_REG + 0x00)
112 #define TPU_INT_CTRL (TPU_REG + 0x02)
113 #define TPU_INT_STAT (TPU_REG + 0x04)
114 #define TPU_OFFSET_REG (TPU_REG + 0x0C)
115 #define TPU_SYNCHRO_REG (TPU_REG + 0x0E)
116 #define TPU_DSP_PG (TPU_REG + 0x20)
117
118
119
120
121
122 /*
123 * TPU control register bits
124 */
125 // GSM 1.5 : TPU bits changed
126 //---------------------------------------
127 #define TPU_CTRL_RESET 0x0001
128 #define TSP_CTRL_RESET 0x0080
129 #define TPU_CTRL_T_PAGE 0x0002
130 #define TPU_CTRL_T_ENBL 0x0004
131 #define TPU_CTRL_D_ENBL 0x0010 // WARNING THIS BIT DOES NOT EXIST IN HYPERION
132 #define TPU_CTRL_SPI_RST 0x0080
133 #define TPU_CTRL_WAIT 0x0200
134 #define TPU_CTRL_CLK_EN 0x0400
135 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
136 #define TPU_CTRL_FULL_WRITE 0x0800
137 #endif
138
139
140
141
142 /*
143 * TPU interrupt control register bits
144 */
145
146
147 /* WARNING BUG IN HYPERION. */
148 /* READING TPU_INT_CRTL, TPU_INT_ITP_M BIT CONTENTS AFFECTS THE TPU_INT_ITD_M VALUE. */
149
150 #define TPU_INT_ITF_M 0x0001
151 #define TPU_INT_ITP_M 0x0002
152 #define TPU_INT_ITD_M 0x0004
153 #define TPU_INT_ITD_F 0x0008 // WARNING THIS BIT DOES NOT EXIST IN HYPERION
154
155 #define INT_FRAME 4 /* TPU frame interrupt */
156 #define INT_PAGE 5 /* TPU page interrupt */
157 #define INT_TSP 3 /* TSP interrupt */
158
159
160
161 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
162 // BB signals connected to serial link1
163 #define BULON 0x80 // bit6
164 #define BULCAL 0x40 // bit5
165 #define BULENA 0x20 // bit4
166 #define BDLON 0x10 // bit3
167 #define BDLCAL 0x08 // bit2
168 #define BDLENA 0x04 // bit1
169 #define STARTADC 0x02 // bit0
170 #endif
171
172
173 /*
174 * GSM RF programming times in quarter bits
175 */
176 /**************************************************************************/
177 /**************************************************************************/
178 /****************************** W A R N I N G !!! *************************/
179 /******* This values are fine tuned for LAYER 1 . DO NOT MODIFY !!! *******/
180 /****** FOR ANY MODIFICATION , PLEASE CONTACT Texas Instruments Inc. ******/
181 /**************************************************************************/
182 /**************************************************************************/
183
184
185 /**************************************/
186 /* TPU Macros: prototypes functions */
187 /**************************************/
188 // TPU macros.
189 //------------
190 void l1dmacro_reset_hw (UWORD32 servingCellOffset);
191 void l1dmacro_init_hw (void);
192 void l1dmacro_init_hw_light (void);
193 void l1dmacro_idle (void);
194 void l1dmacro_rx_synth (SYS_UWORD16 radio_freq);
195 void l1dmacro_tx_synth (SYS_UWORD16 radio_freq);
196 void l1dmacro_agc (SYS_UWORD16 radio_freq, WORD8 gain, UWORD8 lna);
197 void l1dmacro_afc (SYS_UWORD16 afc_value, UWORD8 win_id);
198 void l1dmacro_rx_ms (SYS_UWORD16 radio_freq);
199 void l1dmacro_rx_fb (SYS_UWORD16 radio_freq);
200 void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq);
201 void l1dmacro_offset (UWORD32 offset_value,
202 WORD32 relative_time);
203 void l1dmacro_synchro (UWORD32 when, UWORD32 value);
204 void l1dmacro_rx_sb (SYS_UWORD16 radio_freq);
205 void l1dmacro_rx_nb (SYS_UWORD16 radio_freq);
206 void l1dmacro_tx_nb (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
207 void l1dmacro_tx_ra (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
208 void l1dmacro_adc_read_tx (UWORD32 when);
209 void l1dmacro_adc_read_rx (void);
210 void l1dmacro_set_frame_it (void);
211
212 void l1pdmacro_it_dsp_gen(WORD16 time);
213
214 #if TESTMODE
215 void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
216 void l1dmacro_tx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
217 void l1dmacro_stop_cont (void);
218 #endif
219
220 /*
221 * TPU prototypes
222 */
223 void TP_PageIntHandler (void);
224 void TP_FrameIntHandler (void);
225 void TP_PageIntHandler (void);
226 void TP_FrameIntHandler (void);
227 void TPU_Reset(SYS_UWORD16 on);
228 void TSP_Reset(SYS_UWORD16 on);
229 void TPU_ClkEnable(SYS_UWORD16 on);
230 void TP_Reset(SYS_UWORD16 on);
231 void TP_Enable(SYS_UWORD16 on);
232 BOOL TPU_check_IT_DSP(void);
233
234
235 /*
236 * TPUDRV global variables
237 */
238 #ifdef TPUDRV_C
239 #define TP_GLOBAL
240 #else
241 #define TP_GLOBAL extern
242 #endif
243
244 TP_GLOBAL volatile UWORD32 TP_PageInt;
245 TP_GLOBAL volatile UWORD32 TP_FrameInt;
246
247