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comparison src/cs/system/main/gcc/exceptions.S @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
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-1:000000000000 0:92470e5d0b9e
1 /*
2 * This module contains ARM exception handlers which used to be
3 * in chipsetsw/system/Main/int.s in TI's original version.
4 */
5
6 .text
7 .code 32
8
9 @ layout of xdump buffer:
10 @ struct xdump_s {
11 @ long registers[16] // svc mode registers
12 @ long cpsr // svc mode CPSR
13 @ long exception // magic word + index of vector taken
14 @ long stack[20] // bottom 20 words of usr mode stack
15 @ }
16
17 .globl _arm_undefined
18 _arm_undefined:
19 @ store r12 for Xdump_buffer pointer, r11 for index
20 stmfd r13!,{r11,r12}
21 mov r11,#1
22 b save_regs
23
24 .globl _arm_swi
25 _arm_swi:
26 @ store r12 for Xdump_buffer pointer, r11 for index
27 stmfd r13!,{r11,r12}
28 mov r11,#2
29 b save_regs
30
31 .globl _arm_abort_prefetch
32 _arm_abort_prefetch:
33 @ store r12 for Xdump_buffer pointer, r11 for index
34 stmfd r13!,{r11,r12}
35 mov r11,#3
36 b save_regs
37
38 .globl _arm_abort_data
39 _arm_abort_data:
40 @ store r12 for Xdump_buffer pointer, r11 for index
41 stmfd r13!,{r11,r12}
42 mov r11,#4
43 b save_regs
44
45 .globl _arm_reserved
46 _arm_reserved:
47 ldr r13,=_Except_Stack_SP @ mode unknown
48 @ store r12 for Xdump_buffer pointer, r11 for index
49 stmfd r13!,{r11,r12}
50 mov r11,#5
51 b save_regs
52
53 save_regs:
54 ldr r12,=xdump_buffer
55 str r14,[r12,#4*15] @ save r14_abt (original PC) into r15 slot
56
57 stmia r12,{r0-r10} @ save unbanked registers (except r11 and r12)
58 ldmfd r13!,{r0,r1} @ get original r11 and r12
59 str r0,[r12,#4*11] @ save original r11
60 str r1,[r12,#4*12] @ save original r12
61 mrs r0,spsr @ get original psr
62 str r0,[r12,#4*16] @ save original cpsr
63
64 mrs r1,cpsr @ save mode psr
65 bic r2,r1,#0x1f @ psr with mode bits cleared
66 and r0,r0,#0x1f @ get original mode bits
67 add r0,r0,r2
68
69 msr cpsr,r0 @ move to pre-exception mode
70 str r13,[r12,#4*13] @ save original SP
71 str r14,[r12,#4*14] @ save original LR
72 msr cpsr,r1 @ restore mode psr
73
74 @ r11 has original index
75 orr r10,r11,#0xDE<<24 @ r10 = 0xDEAD0000 + index of vector taken
76 orr r10,r10,#0xAD<<16
77 str r10,[r12,#4*17] @ save magic + index
78
79 mov r0,r11 @ put index into 1st argument
80 b dar_exception
81
82 @ the second part
83
84 /*
85 * For the SP-in-RAM validity check, we use the following simplification:
86 * it doesn't really matter what the actual IRAM and XRAM sizes are on
87 * any given target, as the address decoder hooked up to the ARM7TDMI core
88 * always decodes the full 8 MiB address range for each, causing the
89 * actual memories to be aliased multiple times in those two ranges.
90 * Furthermore, the XRAM address range falls right after the IRAM one,
91 * thus we can get away with only a single range check.
92 */
93
94 #define RAM_LOW 0x00800000
95 #define RAM_HIGH 0x01800000
96
97 #define XDUMP_STACK_SIZE 20
98
99 .globl exception
100 exception:
101 ldr r12,=xdump_buffer
102 ldr r11,[r12,#4*13] @ get svc mode r13
103 add r12,r12,#4*18 @ base of stack buffer
104
105 @ check if svc r13(sp) is within internal/external RAM.
106 @ It *could* be invalid.
107 cmp r11,#RAM_LOW
108 blt nostack
109 mov r0,#RAM_HIGH
110 sub r0,r0,#XDUMP_STACK_SIZE
111 cmp r11,r0
112 bge nostack
113
114 stack_range:
115 ldmfd r11!,{r0-r9} @ copy ten stack words..
116 stmia r12!,{r0-r9}
117 ldmfd r11!,{r0-r9} @ copy ten stack words..
118 stmia r12!,{r0-r9}
119
120 nostack:
121 @ we're finished saving all state.
122 @ Now execute C code for more flexibility.
123 @ set up a stack for this C call
124 ldr sp,=_Stack_segment_end
125 b dar_reset