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comparison src/cs/system/main/init.c @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
parents
children c07376e250c1
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-1:000000000000 0:92470e5d0b9e
1 /*
2 * INIT.C
3 *
4 * This module allows to initialize the board:
5 * - wait states,
6 * - unmask selected interrupts,
7 * - initialize clock,
8 * - disable watchdog.
9 * Dummy functions used by the EVA3 library are defined.
10 */
11
12 /* Config Files */
13
14 #ifndef _WINDOWS
15 #include "l1sw.cfg"
16 #include "rf.cfg"
17 #include "chipset.cfg"
18 #include "board.cfg"
19 #include "swconfig.cfg"
20 #include "fc-target.h"
21 #if (OP_L1_STANDALONE == 0)
22 #include "rv.cfg"
23 #include "sys.cfg"
24 #include "debug.cfg"
25 #ifdef BLUETOOTH_INCLUDED
26 #include "btemobile.cfg"
27 #endif
28 #ifdef BLUETOOTH
29 #include "bluetooth.cfg"
30 #endif
31 #endif
32
33 #if (OP_L1_STANDALONE == 0)
34 #include "rv/rv_defined_swe.h"
35 #endif
36 #endif
37
38 /* Include Files */
39 #include <assert.h>
40 #include <ctype.h>
41 #include <stdarg.h>
42 #include <stdlib.h>
43 #include <string.h>
44
45 #include "nucleus.h"
46
47 #include "sys_types.h"
48 #include "l1_types.h"
49 #include "l1_confg.h"
50 #include "l1_const.h"
51
52 #if TESTMODE
53 #include "l1tm_defty.h"
54 #endif // TESTMODE
55
56 #if (AUDIO_TASK == 1)
57 #include "l1audio_const.h"
58 #include "l1audio_cust.h"
59 #include "l1audio_defty.h"
60 #endif // AUDIO_TASK
61
62 #if (L1_GTT == 1)
63 #include "l1gtt_const.h"
64 #include "l1gtt_defty.h"
65 #endif
66
67 #if (L1_MP3 == 1)
68 #include "l1mp3_defty.h"
69 #endif
70
71 #if (L1_MIDI == 1)
72 #include "l1midi_defty.h"
73 #endif
74
75 #if (L1_AAC == 1)
76 #include "l1aac_defty.h"
77 #endif
78 #if (L1_DYN_DSP_DWNLD == 1)
79 #include "l1_dyn_dwl_defty.h"
80 #endif
81
82 #if (TRACE_TYPE == 4)
83 #include "l1_defty.h"
84 #endif
85
86
87 #if ((OP_L1_STANDALONE == 1) && (CODE_VERSION != SIMULATION) && (PSP_STANDALONE == 0))
88
89 #if (AUDIO_TASK == 1)
90 #include "l1audio_signa.h"
91 #include "l1audio_msgty.h"
92 #endif // AUDIO_TASK
93
94 #if (L1_GTT == 1)
95 #include "l1gtt_signa.h"
96 #include "l1gtt_msgty.h"
97 #endif
98
99 #include "l1_defty.h"
100 #include "cust_os.h"
101 #include "l1_msgty.h"
102 #include "nu_main.h"
103 #include "l1_varex.h"
104 #include "l1_proto.h"
105 #include "hw_debug.h"
106 #include "l1_trace.h"
107
108 #endif /* ((OP_L1_STANDALONE == 1) && (CODE_VERSION != SIMULATION) && (PSP_STANDALONE==0)) */
109
110
111 #include "armio/armio.h"
112 #include "timer/timer.h"
113
114 #if (OP_L1_STANDALONE == 0)
115 #include "rvf/rvf_api.h"
116 #include "rvm/rvm_api.h" /* A-M-E-N-D-E-D! */
117 #include "sim/sim.h"
118 #endif
119
120 #include "abb/abb.h"
121
122 #include "inth/iq.h"
123 #include "tpudrv.h"
124 #include "memif/mem.h"
125 #include "clkm/clkm.h"
126 #include "inth/inth.h"
127
128 #if (OP_L1_STANDALONE == 1)
129 #include "uart/serialswitch_core.h"
130 #else
131 #include "uart/serialswitch.h"
132 #endif
133 #include "uart/traceswitch.h"
134
135
136 #include "dma/dma.h"
137 #include "rhea/rhea_arm.h"
138
139 #include "ulpd/ulpd.h"
140
141 #if (PSP_STANDALONE == 0)
142 #if (OP_L1_STANDALONE == 0)
143 extern void ffs_main_init(void);
144 extern void create_tasks(void);
145 #if TI_NUC_MONITOR == 1
146 extern void ti_nuc_monitor_tdma_action( void );
147 #endif
148
149 #if WCP_PROF == 1
150 #if PRF_CALIBRATION == 1
151 extern NU_HISR prf_CalibrationHISR;
152 #endif
153 #endif
154
155 #else
156 void l1ctl_pgm_clk32(UWORD32 nb_hf, UWORD32 nb_32khz);
157 extern void L1_trace_string(char *s);
158 #endif /* (OP_L1_STANDALONE) */
159 #endif
160
161 #if (OP_L1_STANDALONE == 1)
162 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) || TESTMODE)
163 #include "uart/uart.h"
164 /*
165 * Serial Configuration set up.
166 */
167
168 extern char ser_cfg_info[NUMBER_OF_TR_UART];
169 #include "rvt_gen.h"
170 extern T_RVT_USER_ID trace_id;
171 #endif
172 #endif /* (OP_L1_STANDALONE == 1) */
173
174 /*
175 * Serial Configuration set up.
176 */
177
178 /*
179 ** One config is:
180 ** {XXX_BT_HCI, // Bluetooth HCI
181 ** XXX_FAX_DATA, // Fax/Data AT-Cmd
182 ** XXX_TRACE, // L1/Riviera Trace Mux
183 ** XXX_TRACE}, // Trace PS
184 **
185 ** with XXX being DUMMY, UART_IRDA or UART_MODEM
186 */
187
188 #if ((((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) ||\
189 (TESTMODE)) && (OP_L1_STANDALONE == 1)) || (OP_L1_STANDALONE == 0))
190 #if (OP_L1_STANDALONE == 1)
191 static T_AppliSerialInfo appli_ser_cfg_info =
192 #else
193 T_AppliSerialInfo appli_ser_cfg_info =
194 #endif /* OP_L1_STANDALONE */
195 {
196 #ifdef CONFIG_RVTMUX_ON_MODEM
197 {DUMMY_BT_HCI,
198 DUMMY_FAX_DATA,
199 UART_MODEM_TRACE,
200 DUMMY_TRACE}, // 0x0248
201 #else // RVTMUX_ON_MODEM
202 {DUMMY_BT_HCI,
203 UART_MODEM_FAX_DATA,
204 UART_IRDA_TRACE,
205 DUMMY_TRACE}, // default config = 0x0168
206 #endif
207 #ifdef BTEMOBILE
208 12, // 12 serial config allowed
209 #else // BTEMOBILE
210 9, // 9 serial config allowed
211 #endif
212 {
213 // Configs with Condat Panel only
214 {DUMMY_BT_HCI,
215 DUMMY_FAX_DATA,
216 DUMMY_TRACE,
217 UART_IRDA_TRACE}, // 0x1048
218 {DUMMY_BT_HCI,
219 DUMMY_FAX_DATA,
220 DUMMY_TRACE,
221 UART_MODEM_TRACE}, // 0x2048
222 // Configs with L1/Riviera Trace only
223 {DUMMY_BT_HCI,
224 DUMMY_FAX_DATA,
225 UART_IRDA_TRACE,
226 DUMMY_TRACE}, // 0x0148
227 {DUMMY_BT_HCI,
228 DUMMY_FAX_DATA,
229 UART_MODEM_TRACE,
230 DUMMY_TRACE}, // 0x0248
231 // Configs with AT-Cmd only
232 {DUMMY_BT_HCI,
233 UART_MODEM_FAX_DATA,
234 DUMMY_TRACE,
235 DUMMY_TRACE}, // 0x0068
236 // Configs with Condat Panel and L1/Riviera Trace
237 {DUMMY_BT_HCI,
238 DUMMY_FAX_DATA,
239 UART_MODEM_TRACE,
240 UART_IRDA_TRACE}, // 0x1248
241 {DUMMY_BT_HCI,
242 DUMMY_FAX_DATA,
243 UART_IRDA_TRACE,
244 UART_MODEM_TRACE}, // 0x2148
245 // Configs with Condat Panel and AT-Cmd
246 {DUMMY_BT_HCI,
247 UART_MODEM_FAX_DATA,
248 DUMMY_TRACE,
249 UART_IRDA_TRACE}, // 0x1068
250 #ifdef BTEMOBILE
251 // Configs with L1/Riviera Trace and Bluetooth HCI
252 {UART_IRDA_BT_HCI,
253 DUMMY_FAX_DATA,
254 UART_MODEM_TRACE,
255 DUMMY_TRACE}, // 0x0249
256 {UART_MODEM_BT_HCI,
257 DUMMY_FAX_DATA,
258 UART_IRDA_TRACE,
259 DUMMY_TRACE}, // 0x014A
260 // Configs with AT-Cmd and Bluetooth HCI
261 {UART_IRDA_BT_HCI,
262 UART_MODEM_FAX_DATA,
263 DUMMY_TRACE,
264 DUMMY_TRACE}, // 0x0069
265 #endif // BTEMOBILE
266 // Configs with L1/Riviera Trace and AT-Cmd
267 {DUMMY_BT_HCI,
268 UART_MODEM_FAX_DATA,
269 UART_IRDA_TRACE,
270 DUMMY_TRACE} // 0x0168
271 }
272 };
273 #endif /* (TRACE_TYPE ...) || (OP_L1_STANDALONE == 0) */
274
275
276 /*
277 * Init_Target
278 *
279 * Performs low-level HW Initialization.
280 */
281 void Init_Target(void)
282 {
283 #if (BOARD == 5)
284 #define WS_ROM (1)
285 #define WS_RAM (1)
286 #define WS_APIF (1)
287 #define WS_CS2 (7) /* LCD on EVA3. */
288 #define WS_CS0 (7) /* DUART on EVA3. UART16750 and latch on A-Sample. */
289 #define WS_CS1 (7) /* LCD on A-Sample. */
290
291 IQ_InitWaitState (WS_ROM, WS_RAM, WS_APIF, WS_CS2, WS_CS0, WS_CS1);
292 IQ_InitClock (2); /* Internal clock division factor. */
293
294 IQ_MaskAll (); /* Mask all interrupts. */
295 IQ_SetupInterrupts (); /* IRQ priorities. */
296
297 TM_DisableWatchdog ();
298
299 /*
300 * Reset all TSP and DBG fdefault values
301 */
302
303 AI_ResetTspIO ();
304 AI_ResetDbgReg ();
305 AI_ResetIoConfig ();
306
307 /*
308 * Warning! The external reset signal is connected to the Omega and the
309 * external device. If the layer 1 is used its initialization removes
310 * the external reset. If the application does not use the layer 1
311 * you must remove the external reset (bit 2 of the reset control
312 * register 0x505808).
313 */
314
315 AI_ResetTspIO();
316 AI_ResetDbgReg();
317 AI_ResetIoConfig();
318
319 /*
320 * Configure all IOs (see RD300 specification).
321 */
322
323 AI_ConfigBitAsInput (1);
324 AI_EnableBit (1);
325
326 AI_ConfigBitAsOutput (2);
327 AI_EnableBit (2);
328
329 AI_ConfigBitAsInput (11);
330 AI_EnableBit (11);
331
332 AI_ConfigBitAsOutput (13);
333 AI_EnableBit (13);
334
335 AI_Power (1); /* Maintain power supply. */
336
337 #elif (BOARD == 6) || (BOARD == 7) || (BOARD == 8) || (BOARD == 9) || \
338 (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45) || \
339 (BOARD == 35) || (BOARD == 46) || (BOARD == 70) || (BOARD == 71)
340
341 #if (PSP_STANDALONE == 0)
342 // RIF/SPI rising edge clock for ULYSSE
343 //--------------------------------------------------
344 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)|| (ANLG_FAM == 11))
345 #if ((CHIPSET >= 3))
346 #if (CHIPSET == 12)
347 F_CONF_RIF_RX_RISING_EDGE;
348 F_CONF_SPI_RX_RISING_EDGE;
349 #elif (CHIPSET == 15)
350 //do the DRP init here for Locosto
351 #if (L1_DRP == 1)
352 // drp_power_on(); This should be done after the script is downloaded.
353 #endif
354 #else
355 #if (BOARD==35)
356 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000;
357 #elif defined(CONFIG_TARGET_PIRELLI)
358 /*
359 * Pirelli's version of this Init_Target() function
360 * in their fw sets the ASIC_CONF register to 0x6050,
361 * which means PWL on the LT/PWL pin and LPG on the
362 * DSR_MODEM pin.
363 */
364 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6050;
365 #elif defined(CONFIG_TARGET_GTAMODEM) || defined(CONFIG_TARGET_GTM900)
366 /*
367 * The DSR_MODEM/LPG Calypso signal is unconnected on
368 * Openmoko's modem, so let's mux it as LPG (output)
369 * so it doesn't float, like Foxconn seem to have done
370 * on the Pirelli.
371 *
372 * On the GTM900 module this signal is explicitly defined as LPG.
373 */
374 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6040;
375 #else
376 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000;
377 #endif /* (BOARD == 35) */
378 #endif
379 #endif
380 #endif /* ANLG(ANALOG)) */
381
382 #if (OP_L1_STANDALONE == 1)
383 #if (BOARD == 40) || (BOARD == 41) || \
384 (BOARD == 42) || (BOARD == 43) || (BOARD == 45)
385 // enable 8 Ohm amplifier for audio on D-sample
386 AI_ConfigBitAsOutput (1);
387 AI_SetBit(1);
388 #elif (BOARD == 70) || (BOARD == 71)
389 //Locosto I-sample or UPP costo board.BOARD
390 // Initialize the ARMIO bits as per the I-sample spec
391 // FIXME
392 #endif
393 #endif /* (OP_L1_STANDALONE == 1) */
394 #endif /* PSP_STANDALONE ==0 */
395
396 // Watchdog
397 //--------------------------------------------------
398 TM_DisableWatchdog(); /* Disable Watchdog */
399 #if (CHIPSET == 12) || (CHIPSET == 15)
400 TM_SEC_DisableWatchdog();
401 #endif
402
403 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
404
405 #if (CHIPSET == 12)
406
407 #if 0 /* example of configuration for DMA debug */
408 #if (BOARD == 6) /* debug on EVA 4 , GPO2 must not be changed */
409
410 /* TPU_FRAME, NMIIT, IACKn */
411 F_DBG_IRQ_CONFIG(C_DBG_IRQ_IRQ4|C_DBG_IRQ_NMIIT|C_DBG_IRQ_IACKN);
412
413 /* NDMA_REQ_VIEW1, NDMA_REQ_VIEW0, DMA_V(1), DMA_S(1), DMAREQ_P1(3:0)*/
414 F_DBG_DMA_P1_NDFLASH_CONFIG(C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_1 |
415 C_DBG_DMA_P1_NDFLASH_NDMA_REQ_VIEW_0 |
416 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_3 |
417 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_2 |
418 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_1 |
419 C_DBG_DMA_P1_NDFLASH_DMA_REQ_P1_0 |
420 C_DBG_DMA_P1_NDFLASH_DMA_REQ_S_1 |
421 C_DBG_DMA_P1_NDFLASH_DMA_REQ_V1 );
422 /* DMA_REQ_S(2)*/
423 F_DBG_DMA_P2_CONFIG(C_DBG_DMA_P2_DMA_REQ_S2);
424
425 /* DMA_CLK_REQ, BRIDGE_CLK */
426 F_DBG_CLK1_CONFIG(C_DBG_CLK1_DMA_CLK_REQ |
427 C_DBG_CLK1_BRIDGE_CLK );
428
429 /* XIO_nREADY */
430 F_DBG_IMIF_CONFIG(C_DBG_IMIF_XIO_NREADY_MEM);
431
432 /* DSP_nIRQ_VIEW1, DSP_nIRQ_VIEW0, BRIDGE_EN */
433 F_DBG_KB_USIM_SHD_CONFIG(C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_1 |
434 C_DBG_KB_USIM_SHD_DSP_NIRQ_VIEW_0 |
435 C_DBG_KB_USIM_SHD_BRIDGE_EN );
436
437 /* RHEA_nREADY , RHEA_nSTROBE */
438 F_DBG_USIM_CONFIG(C_DBG_USIM_RHEA_NSTROBE |
439 C_DBG_USIM_RHEA_NREADY );
440
441 /* XIO_STROBE */
442 F_DBG_MISC2_CONFIG(C_DBG_MISC2_X_IOSTRBN);
443
444 /* DMA_CLK_REQ */
445 F_DBG_CLK2_CONFIG(C_DBG_CLK2_DMA_CLK_REQ2);
446
447 /* DSP_IRQ_SEL0=DMA, DSP_IRQ_SEL1=DMA, DMA_REQ_SEL0=RIF_RX, DMA_REQ_SEL1=RIF_RX */
448 F_DBG_VIEW_CONFIG(0,0,C_DBG_DSP_INT_DMA,
449 C_DBG_DSP_INT_DMA,
450 C_DMA_CHANNEL_RIF_RX,
451 C_DMA_CHANNEL_RIF_RX);
452
453 #endif /* (BOARD == 6) */
454 #endif /* DMA debug example */
455 #else
456 /*
457 * Configure ASIC in order to output the DPLL and ARM clock
458 */
459 // (*( volatile UWORD16* )(0xFFFEF008)) = 0x8000; // DPLL
460 // (*( volatile UWORD16* )(0xFFFEF00E)) = 0x0004; // ARM clock
461 // (*( volatile UWORD16* )(0xfffef004)) = 0x0600; // DSP clock + nIACK
462 #endif /* (CHIPSET == 12) || CHIPSET == 15*/
463
464
465 /*
466 * Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules
467 */
468 // IRQ, Timer and bridge may SLEEP
469 // In first step, same configuration as SAMSON
470 //--------------------------------------------------
471 #if (CHIPSET == 12)
472 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_BRIDGE_DIS | CLKM_DPLL_DIS);
473 #elif (CHIPSET == 15)
474 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_CPORT_EN | CLKM_BRIDGE_DIS | 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/
475
476 #else
477 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS);
478
479 // Select VTCXO input frequency
480 //--------------------------------------------------
481 CLKM_UNUSED_VTCXO_26MHZ;
482
483 // Rita RF uses 26MHz VCXO
484 #if (RF_FAM == 12)
485 CLKM_USE_VTCXO_26MHZ;
486 #endif
487 // Renesas RF uses 26MHz on F-sample but 13MHz on TEB
488 #if (RF_FAM == 43) && (BOARD == 46)
489 CLKM_USE_VTCXO_26MHZ;
490 #endif
491 #endif
492
493
494 // Control HOM/SAM automatic switching
495 //--------------------------------------------------
496 *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG;
497
498 /*
499 * The following part has been reconstructed from disassembly.
500 */
501 RHEA_INITRHEA(0,0,0xFF);
502 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
503 #if (CHIPSET == 8)
504 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 6);
505 #elif (CHIPSET == 10) || (CHIPSET == 11)
506 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
507 #else
508 #error "We only have DPLL setup for CHIPSETs 8 and 10"
509 #endif
510 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
511 /*
512 * FreeCalypso change: memory timings and widths are target-dependent;
513 * please refer to the MEMIF-wait-states document in the freecalypso-docs
514 * repository for the full explanation.
515 */
516 #ifdef CONFIG_TARGET_PIRELLI
517 /*
518 * Pirelli's version of this Init_Target() function
519 * in their fw does the following:
520 */
521 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
522 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
523 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
524 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
525 MEM_INIT_CS4(7, MEM_DVS_16, MEM_WRITE_EN, 0);
526 #elif defined(CONFIG_TARGET_C155)
527 /*
528 * C155/156 official fw MEMIF config is almost the same as Pirelli's,
529 * only nCS4 WS is different, but nCS4 is unused on this model...
530 */
531 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
532 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
533 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
534 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
535 MEM_INIT_CS4(6, MEM_DVS_16, MEM_WRITE_EN, 0);
536 #elif defined(CONFIG_TARGET_C11X) || defined(CONFIG_TARGET_C139) || \
537 defined(CONFIG_TARGET_GTAMODEM)
538 /*
539 * The original settings from Openmoko,
540 * only nCS0 and nCS1 are actually used,
541 * same as on Mot C1xx phones,
542 * the nCS2/3/4 settings are dummies from TI.
543 */
544 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
545 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
546 MEM_INIT_CS2(5, MEM_DVS_16, MEM_WRITE_EN, 0);
547 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
548 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
549 #elif defined(CONFIG_TARGET_J100)
550 /*
551 * Same as Mot C11x/12x/139/140 and Openmoko except for nCS2 WS:
552 * it appears that SE J100 has its ringtone melody generator chip
553 * hooked up there.
554 */
555 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
556 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
557 MEM_INIT_CS2(6, MEM_DVS_16, MEM_WRITE_EN, 0);
558 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
559 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
560 #elif (CHIPSET == 8)
561 /*
562 * Our only Calypso C05 target is Mother Mychaela's D-Sample board.
563 * WS=3 with the ARM7 core running at 39 MHz gives us 92 ns,
564 * so we should be good on this board.
565 */
566 MEM_INIT_CS0(3, MEM_DVS_16, MEM_WRITE_EN, 0);
567 MEM_INIT_CS1(3, MEM_DVS_16, MEM_WRITE_EN, 0);
568 MEM_INIT_CS2(3, MEM_DVS_16, MEM_WRITE_EN, 0);
569 MEM_INIT_CS3(3, MEM_DVS_16, MEM_WRITE_EN, 0);
570 MEM_INIT_CS4(0, MEM_DVS_8, MEM_WRITE_EN, 0);
571 #elif (CHIPSET == 10) || (CHIPSET == 11)
572 /*
573 * Default for Calypso C035 targets in the absence of a more specific
574 * selection above. We put the WS=4 memory-oriented setting on all
575 * chip selects so we automatically cover targets with a second flash
576 * chip select no matter if it's nCS2, nCS3 or nCS4, as well as even
577 * weirder targets with XRAM somewhere other than nCS1.
578 */
579 MEM_INIT_CS0(4, MEM_DVS_16, MEM_WRITE_EN, 0);
580 MEM_INIT_CS1(4, MEM_DVS_16, MEM_WRITE_EN, 0);
581 MEM_INIT_CS2(4, MEM_DVS_16, MEM_WRITE_EN, 0);
582 MEM_INIT_CS3(4, MEM_DVS_16, MEM_WRITE_EN, 0);
583 MEM_INIT_CS4(4, MEM_DVS_16, MEM_WRITE_EN, 0);
584 #else
585 #error "Unknown MEMIF configuration"
586 #endif
587 MEM_INIT_CS6(0, MEM_DVS_32, MEM_WRITE_EN, 0);
588 MEM_INIT_CS7(0, MEM_DVS_32, MEM_WRITE_DIS, 0);
589 RHEA_INITAPI(0,1);
590 RHEA_INITARM(0,0);
591 DPLL_SET_PLL_ENABLE;
592
593 /*
594 * Disable and Clear all pending interrupts
595 */
596 #if (CHIPSET == 12) || (CHIPSET == 15)
597 F_INTH_DISABLE_ALL_IT; // MASK all it
598 F_INTH2_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH2 IRQ
599 F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ
600 F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ
601 F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source
602 #else
603 INTH_DISABLEALLIT;
604 #if 0 /* not present in our reference binary object */
605 INTH_RESETALLIT;
606 #endif
607 INTH_CLEAR; /* reset IRQ/FIQ source */
608 #endif
609
610 // INTH
611 //--------------------------------------------------
612 #if (CHIPSET == 12) || (CHIPSET == 15)
613 #if (GSM_IDLE_RAM != 0)
614 f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram); // setup configuration IT handlers
615 #else
616 f_inth_setup((T_INTH_CONFIG *)a_inth_config); // setup configuration IT handlers
617 #endif
618 #else
619 IQ_SetupInterrupts();
620 #endif
621
622
623 #if (CHIPSET == 12) || (CHIPSET == 15)
624 #if (OP_L1_STANDALONE == 0)
625
626 f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter);
627 #endif
628 f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP);
629 #if (OP_L1_STANDALONE == 1)
630 f_dma_global_parameter_set((T_DMA_TYPE_GLOBAL_PARAMETER *)&d_dma_global_parameter);
631 f_dma_channel_allocation_set(C_DMA_CHANNEL_0, C_DMA_CHANNEL_DSP);
632 #endif
633
634 #else
635 // DMA
636 //--------------------------------------------------
637 // channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same
638 #if (OP_L1_STANDALONE == 0)
639 DMA_ALLOCDMA(1,0,1,1); // Channel 1 used by DSP with RIF RX
640 #endif
641 #endif
642
643 /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
644
645 #else
646
647 // RHEA Bridge
648 //--------------------------------------------------
649 // ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F
650 RHEA_INITRHEA(0,0,0x7F);
651
652 #if (CHIPSET == 6)
653 // WS_H = 1 , WS_L = 15
654 RHEA_INITAPI(1,15); // should be 0x01E1 for 65 Mhz
655 #else
656 // WS_H = 0 , WS_L = 7
657 RHEA_INITAPI(0,7); // should be 0x0101 for 65 Mhz
658 #endif
659
660 // Write_en_0 = 0 , Write_en_1 = 0
661 RHEA_INITARM(0,0);
662
663 // INTH
664 //--------------------------------------------------
665 INTH_DISABLEALLIT; // MASK all it
666 INTH_CLEAR; // reset IRQ/FIQ source
667 IQ_SetupInterrupts();
668
669 // DMA
670 //--------------------------------------------------
671 // channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same
672 DMA_ALLOCDMA(1,0,1,1); // should be 0x25 (channel 1 = lead)
673
674 #if (CHIPSET == 6)
675 // Memory WS configuration for ULYSS/G1 (26 Mhz) board
676 //-----------------------------------------------------
677 MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0);
678 #endif
679
680 // CLKM
681 //--------------------------------------------------
682 CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */
683
684 #if (CHIPSET == 6)
685 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS | CLKM_VTCXO_26);
686 #else
687 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS);
688 #endif
689
690 #endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
691
692 // Freeze ULPD timer ....
693 //--------------------------------------------------
694 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_INIT_REG ) = 0;
695 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE;
696
697 // reset INC_SIXTEEN and INC_FRAC
698 //--------------------------------------------------
699 #if (OP_L1_STANDALONE == 1)
700 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE);
701 #else
702 ULDP_INCSIXTEEN_UPDATE(132); //32768.29038 =>132, 32500 => 133
703 // 26000 --> 166
704 ULDP_INCFRAC_UPDATE(15840); //32768.29038 =>15840, 32500 => 21845
705 // 26000 --> 43691
706 #endif /* OP_L1_STANDALONE */
707
708 // program ULPD WAKE-UP ....
709 //=================================================
710 #if (CHIPSET == 2)
711 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 2 frame
712 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 31 periods
713 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
714 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
715 #else
716 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames
717 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods
718 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
719 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
720 *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods
721 #endif
722
723 // Set Gauging versus HF (PLL)
724 //=================================================
725 ULDP_GAUGING_SET_HF; // Enable gauging versus HF
726 ULDP_GAUGING_HF_PLL; // Gauging versus PLL
727
728 // current supply for quartz oscillation
729 //=================================================
730 #if (OP_L1_STANDALONE == 1)
731 #if ((CHIPSET != 9) && (CHIPSET != 12) && (CHIPSET !=15)) // programming model changed for Ulysse C035, stay with default value
732 *(volatile SYS_UWORD16 *)QUARTZ_REG = 0x27;
733 #endif
734 #else
735 #if ((BOARD == 6) || (BOARD == 8) || (BOARD == 9) || (BOARD == 35) || (BOARD == 40) || (BOARD == 41))
736 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x27;
737 #elif (BOARD == 7)
738 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x24;
739 #endif
740 #endif /* OP_L1_STANDALONE */
741
742 // stop Gauging if any (debug purpose ...)
743 //--------------------------------------------------
744 if ( *((volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG) & ULDP_GAUGING_EN)
745 {
746 volatile UWORD32 j;
747 ULDP_GAUGING_STOP; /* Stop the gauging */
748 /* wait for gauging it*/
749 // one 32khz period = 401 periods of 13Mhz
750 for (j=1; j<50; j++);
751 while (! (* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING);
752 }
753
754 #if (OP_L1_STANDALONE == 0)
755 AI_ClockEnable ();
756
757 #if (BOARD == 7)
758 // IOs configuration of the B-Sample in order to optimize the power consumption
759 AI_InitIOConfig();
760
761 // Set LPG instead of DSR_MODEM
762 *((volatile SYS_UWORD16 *) ASIC_CONF) |= 0x40;
763 // Reset the PERM_ON bit of LCR_REG
764 *((volatile SYS_UWORD16 *) MEM_LPG) &= ~(0x80);
765 #elif ((BOARD == 8) || (BOARD == 9))
766 // IOs configuration of the C-Sample in order to optimize the power consumption
767 AI_InitIOConfig();
768
769 // set the debug latch to 0x00.
770 *((volatile SYS_UWORD8 *) 0x2800000) = 0x00;
771 #elif ((BOARD == 35) || (BOARD == 46))
772 AI_InitIOConfig();
773 // CSMI INTERFACE
774 // Initialize CSMI clients for GSM control
775 // and Fax/Data services
776 CSMI_Init();
777 GC_Initialize(); // GSM control initialization
778 CU_Initialize(); // Trace initialization
779 CF_Initialize(); // Fax/Data pre-initialization
780 #elif ((BOARD == 40) || (BOARD == 41))
781 // IOs configuration of the D-Sample in order to optimize the power consumption
782 AI_InitIOConfig();
783
784 #ifdef BTEMOBILE
785 // Reset BT chip by toggling the Island's nRESET_OUT signal
786 *((volatile SYS_UWORD16 *) 0xFFFFFD04) |= 0x04;
787 *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4);
788 #endif
789
790 // set the debug latch to 0x0000.
791 /*
792 * FreeCalypso change: this write is only correct when running
793 * on an actual D-Sample board, but not on any of the real-world
794 * Calypso target devices.
795 */
796 #ifdef CONFIG_TARGET_DSAMPLE
797 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
798 #endif
799 #endif // BOARD
800
801 // Enable HW Timers 1 & 2
802 TM_EnableTimer (1);
803 TM_EnableTimer (2);
804
805 #endif /* (OP_L1_STANDALONE == 0) */
806
807 #endif /* #if (BOARD == 5) */
808 }
809
810 /*
811 * Init_Drivers
812 *
813 * Performs Drivers Initialization.
814 */
815 void Set_Switch_ON_Cause(void);
816 void Init_Drivers(void)
817 {
818
819 #if (CHIPSET==15)
820 bspI2c_init();
821 bspTwl3029_init();
822
823 #if (OP_L1_STANDALONE == 0)
824 Set_Switch_ON_Cause();
825 #endif
826
827
828 /* Turn on DRP We will make VRMCC to device group Modem
829 * And Switch it on.
830 */
831 bspTwl3029_Power_setDevGrp(NULL,BSP_TWL3029_POWER_VRMMC,BSP_TWL3029_POWER_DEV_GRP_MODEM);
832 wait_ARM_cycles(convert_nanosec_to_cycles(100000*2));
833 bspTwl3029_Power_enable(NULL,BSP_TWL3029_POWER_VRMMC,BSP_TWL3029_POWER_STATE_ACTIVE);
834 #endif
835
836 #if (CHIPSET!=15)
837 #if ABB_SEMAPHORE_PROTECTION
838 // Create the ABB semaphore
839 ABB_Sem_Create();
840 #endif // SEMAPHORE_PROTECTION
841 #endif
842
843 #if (OP_L1_STANDALONE == 0)
844 /*
845 * Initialize FFS invoking restore procedure by MPU-S
846 */
847 #if ((BOARD == 35) || (BOARD == 46))
848 GC_FfsRestore();
849 #endif
850
851 /*
852 * FFS main initialization.
853 */
854
855 ffs_main_init();
856
857
858 /*
859 * Initialize Riviera manager and create tasks thanks to it.
860 */
861 #if (CHIPSET!=15) || (REMU==0)
862 rvf_init();
863 rvm_init(); /* A-M-E-M-D-E-D! */
864 create_tasks();
865 #endif
866 /*
867 * SIM Main Initialization.
868 */
869 #if (CHIPSET!=15)
870 SIM_Initialize ();
871 #else
872 bspUicc_bootInit();
873 #endif
874 #endif
875 }
876
877 /*
878 * Init_Serial_Flows
879 *
880 * Performs Serialswitch + related serial data flows initialization.
881 */
882 void Init_Serial_Flows (void)
883 {
884 #if (OP_L1_STANDALONE == 0)
885
886 /*
887 * Initialize Serial Switch module.
888 */
889 #if ((BOARD==35) || (BOARD == 46))
890 SER_InitSerialConfig (GC_GetSerialConfig());
891 #else
892 SER_InitSerialConfig (&appli_ser_cfg_info);
893 #endif
894 /*
895 * Then Initialize the Serial Data Flows and the associated UARTs:
896 * - G2-3 Trace if GSM/GPRS Protocol Stack
897 * - AT-Cmd/Fax & Data Flow
898 *
899 * Layer1/Riviera Trace Flow and Bluetooth HCI Flow are initialized
900 * by the appropriate SW Entities.
901 *
902 * G2-3 Trace => No more Used
903 */
904 SER_tr_Init(SER_PROTOCOL_STACK, TR_BAUD_38400, NULL);
905
906 /*
907 * Fax & Data / AT-Command Interpreter Serial Data Flow Initialization
908 */
909
910 #if ((BOARD != 35) && (BOARD != 46))
911 (void) SER_fd_Initialize ();
912 #endif
913 #else /* OP_L1_STANDALONE */
914
915 #if (TESTMODE || (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==6) || (TRACE_TYPE==7))
916 #if ((BOARD == 35) || (BOARD == 46))
917 ser_cfg_info[UA_UART_0] = '0';
918 #else
919 ser_cfg_info[UA_UART_0] = 'G';
920 #endif
921 #if (CHIPSET !=15)
922 ser_cfg_info[UA_UART_1] = 'R'; // Riviear Demux on UART MODEM
923 #else
924 ser_cfg_info[UA_UART_0] = 'R'; // Riviear Demux on UART MODEM
925 #endif
926
927 /* init Uart Modem */
928 SER_InitSerialConfig (&appli_ser_cfg_info);
929
930 #if TESTMODE || (TRACE_TYPE == 1) || (TRACE_TYPE == 7)
931 SER_tr_Init (SER_LAYER_1, TR_BAUD_115200, rvt_activate_RX_HISR);
932
933 rvt_register_id("OTHER",&trace_id,(RVT_CALLBACK_FUNC)NULL);
934 #else
935 SER_tr_Init (SER_LAYER_1, TR_BAUD_38400, NULL);
936 #endif
937
938 L1_trace_string(" \n\r");
939
940 #endif /* TRACE_TYPE */
941
942 #endif /* OP_L1_STANDALONE */
943 }
944
945 /*
946 * Init_Unmask_IT
947 *
948 * Unmask all used interrupts.
949 */
950 void Init_Unmask_IT (void)
951 {
952 IQ_Unmask(IQ_FRAME);
953 IQ_Unmask(IQ_UART_IRDA_IT);
954 IQ_Unmask(IQ_UART_IT);
955 IQ_Unmask(IQ_ARMIO);
956 #if (L1_DYN_DSP_DWNLD == 1)
957 IQ_Unmask(IQ_API);
958 #endif
959 }