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comparison src/cs/system/template/gsm_ds_fuj4d_lj3.template @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
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-1:000000000000 0:92470e5d0b9e
1 /*
2 * Integrated Protocol Stack Linker command file (all components)
3 *
4 * Target : ARM
5 *
6 * Copyright (c) Texas Instruments 2002, Condat 2002
7 *
8 */
9
10 -c /* Autoinitialize variables at runtime */
11
12 /*********************************/
13 /* SPECIFY THE SYSTEM MEMORY MAP */
14 /*********************************/
15
16 MEMORY
17 {
18 /* CS0: Flash 8 Mbytes ****************************************************/
19 /* Interrupt Vectors Table */
20 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
21
22 /* Boot Sector */
23 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
24
25 /* Magic Word for Calypso Boot ROM */
26 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
27
28 /* Program Memory */
29 P_MEM1 (RXI) : org = 0x00010000 len = 0x00000700
30 P_MEM2 (RXI) : org = 0x00010700 len = 0x00000004
31 P_MEM3 (RXI) : org = 0x00010704 len = 0x001ef8fc
32 P_MEM4 (RXI) : org = 0x00200000 len = 0x00120000
33
34 /* FFS Area */
35 FFS_MEM (RX) : org = 0x00320000 len = 0x000D0000
36 /**************************************************************************/
37
38 /* CS1: External SRAM 1 Mbytes ********************************************/
39 /* Data Memory */
40 D_MEM1 (RW) : org = 0x01000000 len = 0x00100000
41 /**************************************************************************/
42
43 /* CS2: External SRAM 8 Mbytes ********************************************/
44 /* Data Memory */
45 D_MEM2 (RW) : org = 0x01800000 len = 0x00800000
46 /**************************************************************************/
47
48 /* CS6: Calypso Internal SRAM 512 kbytes **********************************/
49 /* Code & Variables Memory */
50 S_MEM (RXW) : org = 0x00800000 len = 0x00080000
51 /**************************************************************************/
52 }
53
54 /***********************************************/
55 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
56 /***********************************************/
57
58 /*
59 * Since the bootloader directly calls the INT_Initialize() routine located
60 * in int.s, this int.s code must always be mapped at the same address
61 * (usually in the second flash sector). Its length is about 0x500 bytes.
62 * Then comes the code that need to be loaded into the internal RAM.
63 */
64
65 SECTIONS
66 {
67 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
68 .monitor : > B_MEM /* Monitor Constants & Code */
69 {
70 $(CONST_BOOT_LIB)
71 }
72
73 .inttext : {} > P_MEM1 /* int.s Code */
74
75 .bss_dar : > D_MEM1 /* DAR SWE Variables */
76 {
77 $(BSS_DAR_LIB)
78 }
79
80 /*
81 * The .bss section should not be split to ensure it is initialized to 0
82 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
83 * or in D_MEM2.
84 */
85
86 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
87 {
88 $(BSS_BOOT_LIB)
89 }
90
91 /*
92 * All .bss sections, which must be mapped in internal RAM must be
93 * grouped in order to initialized the corresponding memory to 0.
94 * This initialization is done in int.s file before calling the Nucleus
95 * routine.
96 */
97
98 GROUP
99 {
100 S_D_Mem /* Label of start address of .bss section in Int. RAM */
101 .DintMem
102 {
103
104 /*
105 * .bss sections of the application
106 */
107
108 $(BSS_LIBS)
109
110 }
111 E_D_Mem /* Label of end address of .bss section in Int. RAM */
112 } > S_MEM
113
114 /*
115 * .text and .const sections which must be mapped in internal RAM.
116 */
117
118 .ldfl : {} > P_MEM2 /* Used to know the start load address */
119 GROUP load = P_MEM3 | P_MEM4, run = S_MEM
120 {
121 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
122 .PIntMem
123 {
124 /*
125 * .text and .const sections of the application.
126 *
127 * The .veneer sections correspond exactly to .text:v&n sections
128 * implementing the veneer functions. The .text:v$n -> .veneer
129 * translation is performed by PTOOL software when PTOOL_OPTIONS
130 * environement variable is set to veneer_section.
131 */
132
133 $(CONST_LIBS)
134
135 }
136 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
137 }
138
139 /*
140 * The rest of the code is mapped in flash, however the trampolines
141 * load address should be consistent with .text.
142 */
143 COMMENT2START
144 `trampolines load = P_MEM3 | P_MEM4, run = S_MEM
145 COMMENT2END
146
147 .text : {} >> P_MEM3 | P_MEM4 /* Code */
148
149 /*
150 * The rest of the constants is mapped in flash.
151 * The .cinit section should not be split.
152 */
153
154 .cinit : {} > P_MEM4 /* Initialization Tables */
155 .const : {} >> P_MEM4 | P_MEM3 /* Constant Data */
156 KadaAPI : {} >> P_MEM4 | P_MEM3 /* ROMized CLDC */
157
158 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
159
160 .stackandheap : > D_MEM1 /* System Stacks, etc... */
161 {
162 /* Leave 20 32bit words for register pushes. */
163 . = align(8);
164 . += 20 * 4;
165
166 /* Stack for abort and/or undefined modes. */
167 exception_stack = .;
168
169 /* Leave 38 32bit words for state saving on exceptions. */
170 _xdump_buffer = .;
171 . += 38 * 4;
172 . = align(8);
173
174 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
175 stack_segment = .;
176 . += 0xB00;
177 }
178
179 .data : {} > D_MEM1 /* Initialized Data */
180 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
181
182 }