FreeCalypso > hg > ffs-editor
comparison src/cs/system/template/gsm_ds_motc139.template @ 0:92470e5d0b9e
src: partial import from FC Selenite
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 15 May 2020 01:28:16 +0000 |
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-1:000000000000 | 0:92470e5d0b9e |
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1 /* | |
2 * Integrated Protocol Stack Linker command file (all components) | |
3 * | |
4 * Target : ARM | |
5 * | |
6 * Copyright (c) Texas Instruments 2002, Condat 2002 | |
7 * | |
8 * This version of the linker script template has been concocted | |
9 * by Spacefalcon the Outlaw, based on gsm_ds_amd8_lj3.template, | |
10 * in order to build the GSM firmware for the memory configuration | |
11 * found in the Motorola C139. | |
12 */ | |
13 | |
14 -c /* Autoinitialize variables at runtime */ | |
15 | |
16 /*********************************/ | |
17 /* SPECIFY THE SYSTEM MEMORY MAP */ | |
18 /*********************************/ | |
19 | |
20 MEMORY | |
21 { | |
22 /* CS0: Flash 4 Mbytes ****************************************************/ | |
23 /* Interrupt Vectors Table */ | |
24 I_MEM (RXI) : org = 0x00000000 len = 0x00000100 | |
25 | |
26 /* Boot Sector */ | |
27 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00 | |
28 | |
29 /* Magic Word for Calypso Boot ROM */ | |
30 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001 | |
31 | |
32 /* Program Memory */ | |
33 P_MEM1 (RXI) : org = 0x00010000 len = 0x00000700 | |
34 P_MEM2 (RXI) : org = 0x00010700 len = 0x00000004 | |
35 P_MEM3 (RXI) : org = 0x00010704 len = 0x003af8fc | |
36 | |
37 /* FFS Area */ | |
38 FFS_MEM (RX) : org = 0x003C0000 len = 0x00030000 | |
39 /**************************************************************************/ | |
40 | |
41 /* CS1: External SRAM 1 Mbytes ********************************************/ | |
42 /* Data Memory */ | |
43 | |
44 /* | |
45 *** HACK by Spacefalcon the Outlaw *** | |
46 * | |
47 * The starting Leonardo version (gsm_ds_amd8_lj3.template) had two | |
48 * external SRAM regions: D_MEM1 and D_MEM2. When I tried removing | |
49 * D_MEM2 and keeping only D_MEM1, the linker started behaving oddly | |
50 * in that the sections were emitted in the wrong order, and the | |
51 * addresses printed in the map file were bogus. The resulting m0 | |
52 * images seemed to still work correctly, but I feel that having the | |
53 * linker act "correctly" is better. | |
54 * | |
55 * My current hack-solution is to split the 1 MiB physical XRAM | |
56 * into D_MEM1 and D_MEM2 of 512 KiB each. As it happens, the total | |
57 * XRAM usage of the current firmware is a little below 512 KiB anyway. | |
58 * | |
59 * Update for C139: we only have 512 KiB in total now, but we can still | |
60 * split the last 4 KiB off into D_MEM2. | |
61 */ | |
62 | |
63 D_MEM1 (RW) : org = 0x01000000 len = 0x0007F000 | |
64 D_MEM2 (RW) : org = 0x0107F000 len = 0x00001000 | |
65 /**************************************************************************/ | |
66 | |
67 /* CS6: Calypso Internal SRAM 256 kbytes **********************************/ | |
68 /* Code & Variables Memory */ | |
69 S_MEM (RXW) : org = 0x00800000 len = 0x00040000 | |
70 /**************************************************************************/ | |
71 } | |
72 | |
73 /***********************************************/ | |
74 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ | |
75 /***********************************************/ | |
76 | |
77 /* | |
78 * Since the bootloader directly calls the INT_Initialize() routine located | |
79 * in int.s, this int.s code must always be mapped at the same address | |
80 * (usually in the second flash sector). Its length is about 0x500 bytes. | |
81 * Then comes the code that need to be loaded into the internal RAM. | |
82 */ | |
83 | |
84 SECTIONS | |
85 { | |
86 .intvecs : {} > I_MEM /* Interrupt Vectors Table */ | |
87 .monitor : > B_MEM /* Monitor Constants & Code */ | |
88 { | |
89 $(CONST_BOOT_LIB) | |
90 } | |
91 | |
92 .inttext : {} > P_MEM1 /* int.s Code */ | |
93 | |
94 .bss_dar : > D_MEM1 /* DAR SWE Variables */ | |
95 { | |
96 $(BSS_DAR_LIB) | |
97 } | |
98 | |
99 /* | |
100 * The .bss section should not be split to ensure it is initialized to 0 | |
101 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1 | |
102 * or in D_MEM2. | |
103 * | |
104 * Falcon's note for K5A3281: see the comments above where the memory | |
105 * regions are defined. | |
106 */ | |
107 | |
108 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */ | |
109 { | |
110 $(BSS_BOOT_LIB) | |
111 } | |
112 | |
113 /* | |
114 * All .bss sections, which must be mapped in internal RAM must be | |
115 * grouped in order to initialized the corresponding memory to 0. | |
116 * This initialization is done in int.s file before calling the Nucleus | |
117 * routine. | |
118 */ | |
119 | |
120 GROUP | |
121 { | |
122 S_D_Mem /* Label of start address of .bss section in Int. RAM */ | |
123 .DintMem | |
124 { | |
125 | |
126 /* | |
127 * .bss sections of the application | |
128 */ | |
129 | |
130 $(BSS_LIBS) | |
131 | |
132 } | |
133 | |
134 API_HISR_stack : {} | |
135 | |
136 E_D_Mem /* Label of end address of .bss section in Int. RAM */ | |
137 } > S_MEM | |
138 | |
139 /* | |
140 * .text and .const sections which must be mapped in internal RAM. | |
141 */ | |
142 | |
143 .ldfl : {} > P_MEM2 /* Used to know the start load address */ | |
144 GROUP load = P_MEM3, run = S_MEM | |
145 { | |
146 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */ | |
147 .PIntMem | |
148 { | |
149 /* | |
150 * .text and .const sections of the application. | |
151 * | |
152 * The .veneer sections correspond exactly to .text:v&n sections | |
153 * implementing the veneer functions. The .text:v$n -> .veneer | |
154 * translation is performed by PTOOL software when PTOOL_OPTIONS | |
155 * environement variable is set to veneer_section. | |
156 */ | |
157 | |
158 $(CONST_LIBS) | |
159 | |
160 } | |
161 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */ | |
162 } | |
163 | |
164 /* | |
165 * The rest of the code is mapped in flash, however the trampolines | |
166 * load address should be consistent with .text. | |
167 */ | |
168 COMMENT2START | |
169 `trampolines load = P_MEM3, run = S_MEM | |
170 COMMENT2END | |
171 | |
172 .text : {} > P_MEM3 /* Code */ | |
173 | |
174 /* | |
175 * The rest of the constants is mapped in flash. | |
176 * The .cinit section should not be split. | |
177 */ | |
178 | |
179 .cinit : {} > P_MEM3 /* Initialization Tables */ | |
180 .const : {} > P_MEM3 /* Constant Data */ | |
181 KadaAPI : {} > P_MEM3 /* ROMized CLDC */ | |
182 | |
183 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */ | |
184 | |
185 .stackandheap : > D_MEM1 /* System Stacks, etc... */ | |
186 { | |
187 /* Leave 20 32bit words for register pushes. */ | |
188 . = align(8); | |
189 . += 20 * 4; | |
190 | |
191 /* Stack for abort and/or undefined modes. */ | |
192 exception_stack = .; | |
193 | |
194 /* Leave 38 32bit words for state saving on exceptions. */ | |
195 _xdump_buffer = .; | |
196 . += 38 * 4; | |
197 . = align(8); | |
198 | |
199 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */ | |
200 stack_segment = .; | |
201 . += 0xB00; | |
202 } | |
203 | |
204 .data : {} > D_MEM1 /* Initialized Data */ | |
205 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */ | |
206 | |
207 } |