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comparison src/nucleus/gcc/asm_defs.h @ 0:92470e5d0b9e

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src: partial import from FC Selenite
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 15 May 2020 01:28:16 +0000
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1 /*
2 ************************************************************************
3 *
4 * Copyright Mentor Graphics Corporation 2002
5 * All Rights Reserved.
6 *
7 * THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
8 * THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
9 * SUBJECT TO LICENSE TERMS.
10 *
11 ************************************************************************
12 ************************************************************************
13 *
14 * FILE NAME VERSION
15 *
16 * asm_defs.inc Nucleus PLUS\ARM925\Code Composer 1.14.1
17 *
18 * COMPONENT
19 *
20 * IN - Initialization
21 *
22 * DESCRIPTION
23 *
24 * This file contains the target processor dependent initialization
25 * values used in int.s, tct.s, and tmt.s
26 *
27 * HISTORY
28 *
29 * NAME DATE REMARKS
30 *
31 * B. Ronquillo 08-28-2002 Released version 1.13.1
32 *
33 ************************************************************************
34 */
35
36 /*
37 **********************************
38 * BOARD INITIALIZATION CONSTANTS *
39 **********************************
40 * Begin define constants used in low-level initialization.
41 */
42
43 /* CPSR control byte definitions */
44 #define LOCKOUT 0xC0 /* Interrupt lockout value */
45 #define LOCK_MSK 0xC0 /* Interrupt lockout mask value */
46 #define MODE_MASK 0x1F /* Processor Mode Mask */
47 #define SUP_MODE 0x13 /* Supervisor Mode (SVC) */
48 #define IRQ_MODE 0x12 /* Interrupt Mode (IRQ) */
49 #define IRQ_MODE_OR_LOCKOUT 0xD2 /* Combined IRQ_MODE OR'ed with */
50 /* LOCKOUT */
51 #define FIQ_MODE 0x11 /* Fast Interrupt Mode (FIQ) */
52 #define IRQ_BIT 0x80 /* Interrupt bit of CPSR and SPSR */
53 #define FIQ_BIT 0x40 /* Interrupt bit of CPSR and SPSR */
54 #define IRQ_BIT_OR_FIQ_BIT 0xC0 /* IRQ or FIQ interrupt bit of CPSR */
55 /* and SPSR */
56 #define ABORT_MODE 0x17
57 #define UNDEF_MODE 0x1B
58
59 /*
60 ********************************************
61 * TC_TCB and TC_HCB STRUCT OFFSET DEFINES *
62 ********************************************
63 */
64 #define TC_CREATED 0x00 /* Node for linking to created task */
65 /* list */
66 #define TC_ID 0x0C /* Internal TCB ID */
67 #define TC_NAME 0x10 /* Task name */
68 #define TC_STATUS 0x18 /* Task status */
69 #define TC_DELAYED_SUSPEND 0x19 /* Delayed task suspension */
70 #define TC_PRIORITY 0x1A /* Task priority */
71 #define TC_PREEMPTION 0x1B /* Task preemption enable */
72 #define TC_SCHEDULED 0x1C /* Task scheduled count */
73 #define TC_CUR_TIME_SLICE 0x20 /* Current time slice */
74 #define TC_STACK_START 0x24 /* Stack starting address */
75 #define TC_STACK_END 0x28 /* Stack ending address */
76 #define TC_STACK_POINTER 0x2C /* Task stack pointer */
77 #define TC_STACK_SIZE 0x30 /* Task stack's size */
78 #define TC_STACK_MINIMUM 0x34 /* Minimum stack size */
79 #define TC_CURRENT_PROTECT 0x38 /* Current protection */
80 #define TC_SAVED_STACK_PTR 0x3C /* Previous stack pointer */
81 #define TC_ACTIVE_NEXT 0x3C /* Next activated HISR */
82 #define TC_TIME_SLICE 0x40 /* Task time slice value */
83 #define TC_ACTIVATION_COUNT 0x40 /* Activation counter */
84 #define TC_HISR_ENTRY 0x44 /* HISR entry function */
85 #define TC_HISR_SU_MODE 0x58 /* Sup/User mode indicator for HISRs */
86 #define TC_HISR_MODULE 0x5C /* Module identifier for HISR's */
87 #define TC_SU_MODE 0xA8 /* Sup/User mode indicator for Tasks */
88 #define TC_MODULE 0xAC /* Module identifier for Tasks */