# HG changeset patch
# User Mychaela Falconia <falcon@freecalypso.org>
# Date 1589512431 0
# Node ID 727914266f2820b919703df640d1282af4ad2857
# Parent  d0c841cb75c7ad6601431d28b4ba2d3aead72cf2
gcc: adapted from Selenite

diff -r d0c841cb75c7 -r 727914266f28 gcc/ld-script.src
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gcc/ld-script.src	Fri May 15 03:13:51 2020 +0000
@@ -0,0 +1,141 @@
+dnl This ld script source is fed through m4 in order to fill in
+dnl those settings which depend on the configuration.
+dnl Two include files are fed to m4 before this main body:
+dnl the appropriate targets/*.m4 file defining the memory config
+dnl of the hardware, and one of flash.m4 or xram.m4 to select
+dnl the build type.
+
+/*
+ * FreeCalypso Selenite ld script for the Buildmem build
+ */
+
+ENTRY(_Firmware_boot_entry)
+
+MEMORY {
+ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1,
+`	FLASH_OVERLAY : ORIGIN = 0, LENGTH = 0x2000')
+ifelse(Buildmem,FLASH,
+`	FLASH : ORIGIN = FLASHIMAGE_BASE_ADDR,
+		LENGTH = CONFIG_FWFLASH_SIZE - FLASHIMAGE_BASE_ADDR')
+	IRAM : ORIGIN = 0x00800000, LENGTH = CONFIG_IRAM_SIZE
+	XRAM : ORIGIN = 0x01000000, LENGTH = CONFIG_XRAM_SIZE
+}
+
+SECTIONS {
+dnl The following sections exist only in the flashImage build,
+dnl and only on targets that use the Calypso boot ROM.
+ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1,
+`	/* Part of flash overlaid by the boot ROM */
+	bootrom.overlay 0 : {
+		*(bootrom.overlay)
+	} > FLASH_OVERLAY
+
+	/* code that enables the boot ROM and jumps to it */
+	bootrom.switch : {
+		*(bootrom.switch)
+	} > IRAM AT> FLASH_OVERLAY
+	__romswitch_ram_addr = ADDR(bootrom.switch);
+	__romswitch_flash_addr = LOADADDR(bootrom.switch);
+	__romswitch_size = SIZEOF(bootrom.switch);
+')dnl
+
+	/* boot entry code, going into flash or XRAM emulating flash */
+	.inttext INTTEXT_BASE_ADDR : {
+		*(.inttext)
+	} > Buildmem
+
+	/* copy-to-IRAM code */
+	iram.text 0x80001C : {
+		/* the 7 exception and interrupt vectors @ 0x80001C */
+		*(.ramvecs)
+		*_ir.a:(.text*)
+		*_int.a:(.text*)
+		*_intram.a:(.text*)
+		*osx_na7_db.a:(.text*)
+		*tpudrv.a:(.text*)
+		*drivers_flash.a:niq32.o(.text*)
+		*sim_drv.a:sim32.o(.text*)
+		*libc.a:(.text*)
+		*libgcc.a:(.text*)
+	} > IRAM Put_in_flash
+ifelse(Buildmem,FLASH,
+`	__iramtext_ram_addr = ADDR(iram.text);
+	__iramtext_flash_addr = LOADADDR(iram.text);
+	__iramtext_size = SIZEOF(iram.text);
+')dnl
+
+	/* XIP code, going into flash or XRAM emulating flash */
+	xip.text : {
+		*(.text*)
+		/* let's put the ARM->Thumb veneers in the XIP section */
+		*(.glue_7)
+	} > Buildmem
+
+	/* all .rodata will stay in flash */
+	.rodata : {
+		*(.rodata*)
+	} > Buildmem
+
+	.bss_dar (NOLOAD) : {
+		*dar_gbl_var.a:(.bss* COMMON)
+	} > XRAM
+
+	/*
+	 * All .data will go into XRAM.
+	 * For the flash build we'll have a step that copies
+	 * the .data section from flash to XRAM; for the RAM-only
+	 * build it goes directly into XRAM and stays there.
+	 */
+	.data : {
+		*(.data*)
+	} > XRAM Put_in_flash
+ifelse(Buildmem,FLASH,
+`	__initdata_ram_addr = ADDR(.data);
+	__initdata_flash_addr = LOADADDR(.data);
+	__initdata_size = SIZEOF(.data);
+')dnl
+
+	/* we have two kinds of BSS: internal and external */
+	int.bss (NOLOAD) : {
+		*(.l1s_global)
+		*_ir.a:(.bss* COMMON)
+		*_int.a:(.bss* COMMON)
+		*_intram.a:(.bss* COMMON)
+		*osx_na7_db.a:(.bss* COMMON)
+		*tpudrv.a:(.bss* COMMON)
+		*libc.a:(.bss* COMMON)
+		*libgcc.a:(.bss* COMMON)
+		*(.API_HISR_stack)
+		. = ALIGN(4);
+	} > IRAM
+	__intbss_start = ADDR(int.bss);
+	__intbss_size = SIZEOF(int.bss);
+
+	ext.bss (NOLOAD) : {
+		*(.bss* COMMON)
+		. = ALIGN(4);
+	} > XRAM
+	__extbss_start = ADDR(ext.bss);
+	__extbss_size = SIZEOF(ext.bss);
+
+	int.stack (NOLOAD) : ALIGN(8) {
+		/* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
+		_Stack_segment_start = .;
+		. += 0xB00;
+		_Stack_segment_end = .;
+
+		_iram_end = .;
+	} > IRAM
+
+	ext.stack (NOLOAD) : ALIGN(8) {
+		/* Stack for abort and/or undefined modes. */
+		. += 512;
+		_Except_Stack_SP = .;
+
+		/* Leave 38 32bit words for state saving on exceptions. */
+		xdump_buffer = .;
+		. += 38 * 4;
+
+		_xram_end = .;
+	} > XRAM
+}
diff -r d0c841cb75c7 -r 727914266f28 gcc/makefile-body
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gcc/makefile-body	Fri May 15 03:13:51 2020 +0000
@@ -0,0 +1,41 @@
+CC=	arm-elf-gcc
+LD=	arm-elf-ld
+OBJCOPY=arm-elf-objcopy
+
+CFLAGS=	-mthumb-interwork
+
+LIBC_A=		`${CC} -print-file-name=libc.a -mthumb-interwork`
+LIBGCC_A=	`${CC} -print-file-name=libgcc.a -mthumb-interwork`
+LIBM_T=		`${CC} -print-file-name=libm.a -mthumb-interwork -mthumb`
+
+all:	ramimage.srec
+
+${SUBDIR}: FRC
+	cd $@; ${MAKE} ${MFLAGS}
+
+${LIBS}:	${SUBDIR}
+	@true
+
+bootentry.o:	../src/cs/system/main/gcc/bootentry.S
+	${CC} -c -o $@ ${CFLAGS} -DXRAM -Iconfig -I../src/nucleus/gcc $<
+
+ramvecs.o:	../src/cs/system/main/gcc/ramvecs.S
+	${CC} -c ${CFLAGS} $<
+
+ramimage.ld:	../gcc/xram.m4 ../gcc/memlimits.m4 ../gcc/ld-script.src
+	m4 $^ > $@
+
+ramimage.elf:	${LIBS} bootentry.o ramvecs.o ramimage.ld
+	${LD} -N -T ramimage.ld -o $@ -Map ramimage.map bootentry.o ramvecs.o \
+		--start-group ${LIBS} --end-group \
+		${LIBM_T} ${LIBC_A} ${LIBGCC_A}
+
+ramimage.srec:	ramimage.elf
+	${OBJCOPY} -O srec --srec-forceS3 --srec-len=30 $< $@
+
+clean:	FRC
+	rm -f fwimage.* ramimage.* bootentry*.o ramvecs.o
+	rm -f build_date.* flash-script
+	for i in ${SUBDIR}; do (cd $$i; ${MAKE} ${MFLAGS} clean); done
+
+FRC:
diff -r d0c841cb75c7 -r 727914266f28 gcc/memlimits.m4
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gcc/memlimits.m4	Fri May 15 03:13:51 2020 +0000
@@ -0,0 +1,2 @@
+define(`CONFIG_IRAM_SIZE',0x40000)dnl
+define(`CONFIG_XRAM_SIZE',0x40000)dnl
diff -r d0c841cb75c7 -r 727914266f28 gcc/xram.m4
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gcc/xram.m4	Fri May 15 03:13:51 2020 +0000
@@ -0,0 +1,3 @@
+define(`Buildmem',`XRAM')dnl
+define(`Put_in_flash',`/* no AT> for RAM-only build */')dnl
+define(`INTTEXT_BASE_ADDR',`/* no fixed address */')dnl