FreeCalypso > hg > freecalypso-citrine

annotate bsp/abb+spi/abb_inline.h @ 48:4bb56b6c8645

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LICENSE: new terms
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 14 Apr 2020 21:38:35 +0000
parents 75a11d740a02
children
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1 /******************************************************************************/
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2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
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3 /* */
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4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
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5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This*/
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6 /* product is protected under copyright law and trade secret law as an*/
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7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All*/
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8 /* rights reserved. */
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9 /* */
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10 /* */
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11 /* Filename : abb_inline.h */
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12 /* */
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13 /* Description : inline functions to drive the ABB device. */
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14 /* The Serial Port Interface is used to connect the TI */
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15 /* Analog BaseBand (ABB). */
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16 /* It is assumed that the ABB is connected as the SPI */
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17 /* device 0. */
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18 /* */
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19 /* Author : Pascal PUEL */
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20 /* */
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21 /* Version number : 1.0 */
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22 /* */
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23 /* Date and time : Dec 2002 */
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24 /* */
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25 /* Previous delta : Creation */
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26 /* */
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27 /******************************************************************************/
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28
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29 #ifndef __ABB_INLINE_H__
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30 #define __ABB_INLINE_H__
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31
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32 #include "../../include/config.h"
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33 #include "../../include/sys_types.h"
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34
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35 #include "spi_drv.h"
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36
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37 // MACROS
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38 #define ABB_WRITE_REG(reg, data) { \
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39 SPI_WRITE_TX_MSB((data << 6) | reg) \
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40 SPI_START_WRITE }
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41
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42 #define ABB_READ_REG(reg) { \
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43 SPI_WRITE_TX_MSB(reg | 1) \
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44 SPI_START_READ }
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45
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46
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47 #define ABB_SET_PAGE(page) ABB_WRITE_REG(PAGEREG, page)
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48
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49 #define SEVEN_CYCLES_13M_NS 539
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50
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51 // INLINE FUNCTIONS
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52 /*-----------------------------------------------------------------------*/
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53 /* ABB_SetPage() */
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54 /* */
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55 /* This function sets the right page in the ABB register PAGEREG. */
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56 /* */
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57 /*-----------------------------------------------------------------------*/
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58 static inline void ABB_SetPage(SYS_UWORD16 page)
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59 {
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60 volatile SYS_UWORD16 status;
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61
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62 ABB_SET_PAGE(page);
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63 while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & WE_ST) == 0);
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64
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65 // if IBIC is already processing another request (from the BSP)
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66 // the USP request is delayed by 3 clock cycles
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67 // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case
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68 wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS));
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69 }
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70
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71
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72 /*-----------------------------------------------------------------------*/
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73 /* ABB_WriteRegister() */
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74 /* */
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75 /* This function writes "data" in the ABB register "abb_reg". */
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76 /* */
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77 /*-----------------------------------------------------------------------*/
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78 static inline void ABB_WriteRegister(SYS_UWORD16 abb_reg, SYS_UWORD16 data)
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79 {
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80 volatile SYS_UWORD16 status;
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81
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82 ABB_WRITE_REG(abb_reg, data);
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83 while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & WE_ST) == 0);
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84
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85 // if IBIC is already processing another request (from the BSP)
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86 // the USP request is delayed by 3 clock cycles
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87 // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case
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88 wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS));
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89
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90 }
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91
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92
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93 /*-----------------------------------------------------------------------*/
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94 /* ABB_ReadRegister() */
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95 /* */
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96 /* This function reads the ABB register "abb_reg" and returns */
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97 /* the real register value. */
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98 /* */
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99 /*-----------------------------------------------------------------------*/
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100 static inline SYS_UWORD16 ABB_ReadRegister(SYS_UWORD16 abb_reg)
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101 {
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102 volatile SYS_UWORD16 status;
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103
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104 // First part of read access to the ABB register
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105 ABB_READ_REG(abb_reg);
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106 while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & RE_ST) == 0);
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107
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108 // if IBIC is already processing another request (from the BSP)
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109 // the USP request is delayed by 3 clock cycles
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110 // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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111 wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS));
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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112
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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113 // Second part of read access to the ABB register
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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114 ABB_READ_REG(abb_reg);
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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115 while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & RE_ST) == 0);
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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116
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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117 // if IBIC is already processing another request (from the BSP)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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118 // the USP request is delayed by 3 clock cycles
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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119 // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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120 wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS));
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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121
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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122 return ((SPI_ReadRX_LSB() >> 6) & 0x3ff);
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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123 }
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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124
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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125
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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126 #endif // __ABB_INLINE_H__