FreeCalypso > hg > freecalypso-citrine
annotate L1/cust1/l1_rf61.h @ 33:6a2b09d3b1b4
disable L1_DYN_DSP_DWNLD and AMR by default
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 15 Oct 2016 04:23:58 +0000 |
parents | 75a11d740a02 |
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * |
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4 * Filename l1_rf61.h |
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5 * Version 1.0 |
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6 * Date June 16th, 2005 |
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7 * |
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8 ************* Revision Controle System Header *************/ |
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9 |
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10 #ifndef __L1_RF_H__ |
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11 #define __L1_RF_H__ |
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12 |
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13 #if (ANLG_FAM == 11) |
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14 #include "bspTwl3029_Madc.h" |
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15 #endif |
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16 |
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17 #define RF_LOCOSTO 0x2050 // Check with TIDK |
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18 |
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19 //LNA Specific BAND Index Settings |
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20 #define RF_QUADBAND 0 //Default Setting 850, EGSM,DCS,PCS |
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21 #define RF_EU_TRIBAND 1 // EGSM,DCS,PCS |
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22 #define RF_EU_DUALBAND 2 // EGSM,DCS |
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23 #define RF_US_TRIBAND 3 // 850,DCS,PCS |
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24 #define RF_US_DUALBAND 4 //850, PCS |
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25 #define RF_PCS1900_900_DUALBAND 5 // EGSM, PCS |
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26 #define RF_DCS1800_850_DUALBAND 6 //850, DCS |
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27 |
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28 #define RF_BAND_SYSTEM_INDEX RF_QUADBAND //for other PCB's Please redefine here. |
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29 #define RF_LNA_MASK 0x0003 // Reuse last 2 bits from |
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30 |
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31 //End LNA Changes |
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32 |
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33 //#define RF_HW_BAND_EGSM |
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34 //#define RF_HW_BAND_DCS |
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35 #define RF_HW_BAND_PCS 0x4 |
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36 #define RF_HW_BAND_DUAL_US 0x80 |
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37 #define RF_HW_BAND_DUAL_EXT 0x20 |
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38 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT) |
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39 |
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40 /************************************/ |
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41 /* SYNTHESIZER setup time... */ |
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42 /************************************/ |
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43 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1) //RX Synthesizer setup time in qbit. |
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44 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit. |
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45 |
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46 /************************************/ |
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47 /* Time for TPU scenario ending... */ |
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48 /************************************/ |
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49 // |
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50 // The following values are used to take into account any TPU activity AFTER |
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51 // BDLON (or BDLENA) down (for RX) and BULON down (for TX) |
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52 // - If there are no TPU commands after BDLON (or BDLENA) down and BULON down, |
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53 // these defines must be ZERO |
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54 // - If there IS some TPU command after BDLON (or BDLENA) and BULON down, |
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55 // these defines must be equal to the time difference (in qbits) between |
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56 // the BDLON (or BDLENA) or BULON time and the last TPU command on |
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57 // the TPU scenario |
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58 #define RX_TPU_SCENARIO_ENDING 6 // execution time of AFTER BDLENA down last value : 0 |
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59 #define TX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BULON down last value : 14 |
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60 |
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61 |
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62 /******************************************************/ |
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63 /* TXPWR configuration... */ |
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64 /* Fixed TXPWR value when GSM management is disabled. */ |
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65 /******************************************************/ |
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66 #if ( ANLG_FAM == 11) |
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67 #define FIXED_TXPWR 0x5C // TXPWR=500 for the moment...change later TEMP_FIX |
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68 #endif |
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69 |
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70 |
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71 /************************************/ |
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72 /* RF delay (in qbits) */ |
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73 /************************************/ |
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74 #define DL_DELAY_RF 0 // time spent in the Downlink global RF chain by the modulated signal |
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75 #define UL_DELAY_1RF 0 // time spent in the first uplink RF block |
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76 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block |
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77 |
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78 #define UL_ABB_DELAY 12 // 12 for RF output DELAY |
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79 |
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80 #define GUARD_BITS 5 |
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81 |
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82 /************************************/ |
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83 /* TX Propagation delay... */ |
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84 /************************************/ |
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85 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 50 |
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86 |
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87 /************************************/ |
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88 /* Initial value for APC DELAY */ |
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89 /************************************/ |
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90 #define APCDEL_DOWN (0) // To add this value, the setup delay minimum value: 2 last value : 0 |
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91 //SG #define APCDEL_UP (12) |
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92 #define APCDEL_UP (0) //To add this value, the setup delay minimum value: 6 |
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93 #define C_APCDEL1 (((APCDEL_DOWN & 0x1f)<<5) |(APCDEL_UP & 0x1f) ) |
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94 #define C_APCDEL2 (((APCDEL_DOWN & 0x3e0)) |((APCDEL_UP>>5) & 0x1f) ) |
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95 |
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96 |
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97 /************************************/ |
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98 /* Initial value for AFC... */ |
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99 /************************************/ |
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100 #define EEPROM_AFC ((150)*8) // F14.2 required!!!!! (default : -952*8, initial deviation of -2400 forced) |
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101 |
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102 #if(CHIPSET == 15) |
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103 #define SETUP_AFC_AND_RF 0 |
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104 #else |
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105 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames and RF BAND GAP stable after 4 frames |
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106 #endif |
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107 #define C_DRP_DCXO_XTAL_DSP_ADDRESS 0x7F80 // DRP DCXO XTAL DSP address |
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108 |
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109 /************************************/ |
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110 /* DCO Registers Initialization */ |
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111 /************************************/ |
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112 #define C_DCO_SAMPLES_PER_SYMBOL 1 |
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113 /* The basic frequency table in DSP is approximately 2.115KHz (26MHZ/(512*24)) |
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114 * The FCW value needs to intended IF Frequency / 2.115KHZ. |
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115 * Hence since IF is 100KFZ, FCW = 100 / 2.115 ~= 47 */ |
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116 #define C_DCO_FCW 47 |
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117 |
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118 /*************************************************************** |
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119 * Threshold between LIF_100 KHZ (at high power levels) and |
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120 * LIF_120KHz (at low power level) |
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121 * the threshold defintion for GSM and GPRS is as given below |
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122 * ************************************************************ */ |
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123 #define C_IF_ZERO_LOW_THRESHOLD_GSM 180 // if IL < -90dbm use Zero IF else Low IF STd L1 format |
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124 #define C_IF_ZERO_LOW_THRESHOLD_GPRS 180 // if IL < -90dbm use Zero IF else Low IF STd L1 format |
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125 |
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126 /* Since CSF filter coefficients are changed in accordance with GENIE |
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127 * algorithm, below are values programmed in DRP to select HW/SW CSF filter */ |
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128 #define CSF_CWL_HARDWARE_FILTER_64TAP 0x0100 |
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129 #define CSF_CWL_PROGRAMMABLE_FILTER_64TAP 0x0000 |
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130 |
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131 /* Below are the attenuation losses to be compensated for LIF_100KHZ and LIF_120KHZ Path |
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132 * !!!! Note: The below attenuations are applicable when ROC is enabled !!!! */ |
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133 #define SCF_ATTENUATION_LIF_100KHZ (0) /* value of 0 represents 0dB attenuation as per L1 F7.1 format */ |
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134 #define SCF_ATTENUATION_LIF_120KHZ (1) /* value of 1 represents 0.5dB attenuation */ |
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135 #define SCF_ATTENUATION_ZIF (0) /* No attenuation when ZIF mode is used */ |
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136 |
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137 |
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138 /************************************/ |
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139 /* DRP Retiming Related */ |
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140 /************************************/ |
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141 #define C_RETIMING_DISABLED 0x0 |
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142 #define C_RETIMING_ENABLED 0x1 |
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143 |
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144 #define C_RETIMING_CONFIG C_RETIMING_DISABLED |
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145 |
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146 /*************************************/ |
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147 /* DRP WRAPPER Initialization */ |
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148 /*************************************/ |
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149 #define C_APCCTRL2 0x05C8 // BGEN=1, APCOFF=64, APC_LDO_EN=0, MODE=0 |
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150 // SG #define C_APCCTRL2 0x01FC |
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151 #define DRP_DBB_RX_IRQ_COUNT 16 |
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152 |
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153 #define TTY_L1_STANDALONE 0 |
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154 |
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155 /************************************/ |
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156 /* Triton audio initialize */ |
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157 /************************************/ |
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158 #if (ANLG_FAM == 11) |
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159 #if (TTY_L1_STANDALONE == 1) |
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160 #define C_VULGAIN 0x10 // -12dB |
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161 // #define C_VULGAIN 0x09 // voice uplink gain set to 7dB |
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162 #define C_SIDETONE 0x0d // -23dB |
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163 // #define C_SIDETONE 0x0f // side tone set to MUTE |
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164 #define C_VDLGAIN 0x4c // |
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165 // #define C_VDLGAIN 0x2c // set PGA gain to 2dB |
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166 #define C_CTRL1 0x30 // MicBias = 1, DL Filter Bypass |
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167 // #define C_CTRL1 0x00 // VSYNC = 1, reset Dig Modulator, VSP, Digital filter |
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168 #define C_CTRL2 0x10 // |
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169 // #define C_CTRL2 0x00 // reset value |
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170 #define C_CTRL3 0x25 // MIC IN (diff), MICIP, MICIN. Amplifier: MIC AMP, Gain = 25.6 dB, SPKAMP = +2.5 dB |
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171 #define C_CTRL4 0x00 // reset value |
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172 #define C_CTRL5 0x28 // SAMP FREQ = 48Khz, EARAMP = 1 dB |
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173 #define C_CTRL6 0x00 // reset value |
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174 #define C_POPAUTO 0x01 // POPmode set to/Automatic mode |
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175 #define C_OUTEN1 0x12 // Audio left/Audio Mono, Audio Right/ Audio mono |
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176 #define C_OUTEN2 0x05 // EAR= voice speech, AUXO = voice speech |
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177 #define C_OUTEN3 0x01 // SPK = voice speech |
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178 #define C_AULGA 0x00 // reset value |
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179 #define C_AURGA 0x00 // reset value |
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180 #else |
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181 #define C_VULGAIN 0x09 // voice uplink gain set to 7dB |
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182 #define C_SIDETONE 0x06 // side tone set to MUTE |
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183 #define C_VDLGAIN 0x2c // set PGA gain to 2dB |
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184 #define C_CTRL1 0x00 // VSYNC = 1, reset Dig Modulator, VSP, Digital filter |
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185 #define C_CTRL2 0x00 // reset value |
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186 #define C_CTRL3 0x21 // MIC IN (diff), MICIP, MICIN. Amplifier: MIC AMP, Gain = 25.6 dB, SPKAMP = +2.5 dB |
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187 #define C_CTRL4 0x00 // reset value |
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188 #define C_CTRL5 0x28 // SAMP FREQ = 48Khz, EARAMP = 1 dB |
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189 #define C_CTRL6 0x00 // reset value |
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190 #define C_POPAUTO 0x01 // POPmode set to/Automatic mode |
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191 #define C_OUTEN1 0x24 // Audio left/Audio Mono, Audio Right/ Audio mono |
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192 #define C_OUTEN2 0x01 // EAR= voice speech, AUXO = voice speech |
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193 #define C_OUTEN3 0x01 // SPK = voice speech |
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194 #define C_AULGA 0x00 // reset value |
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195 #define C_AURGA 0x00 // reset value |
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196 #endif //(L1_GTT == 1) |
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197 #endif //(ANLG_FAM == 11) |
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198 |
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199 /************************************/ |
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200 /* Automatic frequency compensation */ |
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201 /************************************/ |
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202 /********************* C_Psi_sta definition *****************************/ |
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203 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */ |
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204 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */ |
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205 /* regarding Vega V/N = 2.4/4096 */ |
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206 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */ |
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207 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */ |
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208 /* = 0.000195748 */ |
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209 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */ |
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210 /************************************************************************/ |
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211 #define C_Psi_sta_inv 6142L // 12902L // (1/C_Psi_sta) |
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212 #define C_Psi_st 9L // 4L // C_Psi_sta * 0.8 F0.16 |
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213 #define C_Psi_st_32 559386L // 266313L // F0.32 |
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214 #define C_Psi_st_inv 7678L // 16128L // (1/C_Psi_st) |
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215 |
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216 #if (VCXO_ALGO == 1) |
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217 // Linearity parameters |
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218 #define C_AFC_DAC_CENTER ((4264)) //((-1242)*8) |
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219 #define C_AFC_DAC_MIN ((-11128)) //((-2000)*8) |
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220 #define C_AFC_DAC_MAX ((19656)) //((1419)*8) |
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221 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10 |
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222 #endif |
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223 |
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224 typedef struct |
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225 { |
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226 WORD16 eeprom_afc; |
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227 UWORD32 psi_sta_inv; |
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228 UWORD32 psi_st; |
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229 UWORD32 psi_st_32; |
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230 UWORD32 psi_st_inv; |
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231 |
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232 #if (VCXO_ALGO) |
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233 // VCXO adjustment parameters |
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234 // Parameters used when assuming linearity |
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235 WORD16 dac_center; |
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236 WORD16 dac_min; |
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237 WORD16 dac_max; |
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238 WORD16 snr_thr; |
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239 #endif |
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240 } |
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241 T_AFC_PARAMS; |
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242 |
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243 /************************************/ |
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244 /* Swap IQ definitions... */ |
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245 /************************************/ |
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246 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */ |
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247 #define SWAP_IQ_GSM 0 |
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248 #define SWAP_IQ_DCS 0 |
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249 #define SWAP_IQ_PCS 0 |
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250 #define SWAP_IQ_GSM850 0 // Swap TX compared to GSM 900 |
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251 |
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252 #define LNA_OFF (1) |
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253 #define LNA_ON (0) |
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254 /************************************/ |
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255 /************************************/ |
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256 // typedef |
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257 /************************************/ |
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258 /************************************/ |
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259 |
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260 /*************************************************************/ |
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261 /* Define structure for apc of TX Power ******/ |
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262 /*************************************************************/ |
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263 typedef struct |
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264 { // pcm-file "rf/tx/level.gsm|dcs" |
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265 UWORD16 apc; // 0..31 |
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266 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE |
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267 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE |
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268 } |
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269 T_TX_LEVEL; |
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270 |
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271 /************************************/ |
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272 /* Automatic Gain Control */ |
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273 /************************************/ |
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274 /* Define structure for sub-band definition of TX Power ******/ |
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275 typedef struct |
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276 { |
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277 UWORD16 upper_bound; //highest physical arfcn of the sub-band |
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278 WORD16 agc_calib; // AGC for each TXPWR |
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279 } T_RF_AGC_BAND; |
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280 |
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281 /************************************/ |
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282 /* Ramp definitions */ |
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283 /************************************/ |
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284 |
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285 typedef struct |
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286 { |
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287 UWORD8 ramp_up [20]; // Ramp-up profile |
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288 UWORD8 ramp_down [20]; // Ramp-down profile |
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289 } |
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290 T_TX_RAMP; |
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291 |
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292 |
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293 // RF structure definition |
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294 //======================== |
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295 #if (L1_FF_MULTIBAND == 0) |
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296 // Number of bands supported |
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297 #define GSM_BANDS 2 |
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298 |
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299 #define MULTI_BAND1 0 |
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300 #define MULTI_BAND2 1 |
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301 #else |
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302 #endif |
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303 |
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304 // RF table sizes |
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305 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands |
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306 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges |
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307 |
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308 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size |
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309 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table |
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310 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size |
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311 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions |
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312 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges |
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313 |
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314 #define AGC_TABLE_SIZE 24 |
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315 #define MIN_AGC_INDEX 0 // size step for AGC table |
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316 |
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317 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table |
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318 #if (REL99 && FF_PRF) |
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319 #define MAX_UPLINK_TIME_SLOT 4 // max number of time slot in uplink |
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320 #endif |
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321 |
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322 |
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323 // RX parameters and tables |
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324 //------------------------- |
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325 |
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326 // AGC parameters and tables |
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327 typedef struct |
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328 { |
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329 UWORD16 low_agc_noise_thr; |
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330 UWORD16 high_agc_sat_thr; |
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331 UWORD16 low_agc; |
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332 UWORD16 high_agc; |
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333 UWORD8 il2agc_pwr[121]; |
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334 UWORD8 il2agc_max[121]; |
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335 UWORD8 il2agc_av[121]; |
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336 } |
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337 T_AGC; |
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338 |
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339 // Calibration parameters |
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340 typedef struct |
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341 { |
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342 UWORD16 g_magic; |
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343 UWORD16 lna_att; |
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344 UWORD16 lna_switch_thr_low; |
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345 UWORD16 lna_switch_thr_high; |
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346 } |
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347 T_RX_CAL_PARAMS; |
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348 |
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349 // RX temperature compensation |
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350 typedef struct |
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351 { |
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352 WORD16 temperature; |
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353 WORD16 agc_calib; |
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354 } |
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355 T_RX_TEMP_COMP; |
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356 |
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357 // RF RX structure |
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358 typedef struct |
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359 { |
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360 T_AGC agc; |
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361 } |
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362 T_RF_RX; //common |
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363 |
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364 // RF RX structure |
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365 typedef struct |
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366 { |
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367 T_RX_CAL_PARAMS rx_cal_params; |
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368 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE]; |
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369 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE]; |
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370 } |
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371 T_RF_RX_BAND; |
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372 |
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373 |
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374 // TX parameters and tables |
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375 //------------------------- |
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376 |
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377 // TX temperature compensation |
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378 typedef struct |
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379 { |
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380 WORD16 temperature; |
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381 #if (ORDER2_TX_TEMP_CAL==1) |
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382 WORD16 a; |
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383 WORD16 b; |
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384 WORD16 c; |
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385 #else |
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386 WORD16 apc_calib; |
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387 #endif |
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388 } |
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389 T_TX_TEMP_CAL; |
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390 |
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391 // Ramp up and ramp down delay |
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392 typedef struct |
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393 { |
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394 UWORD16 up; |
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395 UWORD16 down; |
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396 } |
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397 T_RAMP_DELAY; |
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398 |
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399 typedef struct |
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400 { |
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401 UWORD16 arfcn_limit; |
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402 WORD16 chan_cal; |
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403 } |
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404 T_TX_CHAN_CAL; |
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405 |
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406 // RF TX structure |
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407 typedef struct |
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408 { |
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409 T_RAMP_DELAY ramp_delay; |
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410 UWORD8 guard_bits; // number of guard bits needed for ramp up |
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411 UWORD8 prg_tx; |
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412 } |
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413 T_RF_TX; //common |
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414 |
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415 // RF TX structure |
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416 typedef struct |
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417 { |
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418 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE]; |
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419 #if (REL99 && FF_PRF) |
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420 T_TX_LEVEL levels_power_reduction[MAX_UPLINK_TIME_SLOT]; |
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421 #endif |
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422 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS]; |
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423 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE]; |
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424 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE]; |
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425 } |
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426 T_RF_TX_BAND; |
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427 |
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428 // band structure |
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429 typedef struct |
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430 { |
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431 T_RF_RX_BAND rx; |
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432 T_RF_TX_BAND tx; |
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433 UWORD8 swap_iq; |
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434 } |
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435 T_RF_BAND; |
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436 |
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437 // RF structure |
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438 typedef struct |
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439 { |
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440 // common for all bands |
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441 UWORD16 rf_revision; |
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442 UWORD16 radio_band_support; |
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443 T_RF_RX rx; |
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444 T_RF_TX tx; |
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445 T_AFC_PARAMS afc; |
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446 } |
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447 T_RF; |
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448 |
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449 /************************************/ |
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450 /* MADC definitions */ |
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451 /************************************/ |
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452 // TRITON: 5 external channels |
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453 enum ADC_INDEX { |
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454 ADC_ADIN1, |
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455 ADC_ADIN2, |
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456 ADC_ADIN3, |
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457 ADC_BATT_TYPE, |
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458 ADC_BTEMP, |
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459 ADC_USBVBUS , |
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460 ADC_VBKP, |
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461 ADC_ICHG, |
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462 ADC_VCHG, |
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463 ADC_VBAT, |
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464 ADC_HOTDIE , |
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465 ADC_RFTEMP, |
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466 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums |
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467 }; |
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468 |
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469 |
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470 typedef struct |
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471 { |
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472 WORD16 converted[ADC_INDEX_END]; // converted |
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473 UWORD16 raw[ADC_INDEX_END]; // raw from ADC |
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474 } |
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475 T_ADC; |
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476 |
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|
477 |
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478 /************************************/ |
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479 /* MADC calibration */ |
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480 /************************************/ |
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481 typedef struct |
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482 { |
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483 UWORD16 a[ADC_INDEX_END]; |
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484 WORD16 b[ADC_INDEX_END]; |
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485 } |
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486 T_ADCCAL; |
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487 |
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488 // Conversion table: ADC value -> temperature |
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489 typedef struct |
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490 { |
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491 UWORD16 adc; // ADC reading is 10 bits |
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492 WORD16 temp; // temp is in approx. range -30..+80 |
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493 } |
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494 T_TEMP; |
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495 |
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496 typedef struct |
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497 { |
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498 char *name; |
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499 void *addr; |
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500 int size; |
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501 } |
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502 T_CONFIG_FILE; |
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503 |
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504 #if (L1_FF_MULTIBAND == 0) |
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505 |
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506 typedef struct |
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507 { |
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508 char *name; // name of ffs file suffix |
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509 T_RF_BAND *addr; // address to default flash structure |
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510 UWORD16 max_carrier; // max carrier |
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511 UWORD16 max_txpwr; // max tx power |
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512 } |
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513 T_BAND_CONFIG; |
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514 |
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515 typedef struct |
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516 { |
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517 UWORD8 band[GSM_BANDS]; // index to band address |
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518 UWORD8 txpwr_tp; // tx power turning point |
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519 UWORD16 first_arfcn; // first index |
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520 } |
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521 T_STD_CONFIG; |
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522 |
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523 enum GSMBAND_DEF |
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524 { |
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525 BAND_NONE, |
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526 BAND_EGSM900, |
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527 BAND_DCS1800, |
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528 BAND_PCS1900, |
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529 BAND_GSM850, |
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530 // put new bands here |
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531 BAND_GSM900 //last entry |
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532 }; |
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533 #endif // L1_FF_MULTIBAND == 0 |
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534 |
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535 /************************************/ |
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536 /* ABB (TRITON) Initialization */ |
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537 /************************************/ |
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538 |
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539 /* ABB_TABLE_SIZE definitions for Triton */ |
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540 #if (ANLG_FAM == 11) |
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541 #define ABB_TABLE_SIZE 15 |
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542 #endif |
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543 |
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544 /* ABB enum definitions for TRITON */ |
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545 #if (ANLG_FAM == 11) |
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546 enum ABB_REGISTERS { |
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547 ABB_VULGAIN = 0, |
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548 ABB_VDLGAIN, |
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549 ABB_SIDETONE, |
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550 ABB_CTRL1, |
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551 ABB_CTRL2, |
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552 ABB_CTRL3, |
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553 ABB_CTRL4, |
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554 ABB_CTRL5, |
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555 ABB_CTRL6, |
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556 ABB_POPAUTO, |
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557 ABB_OUTEN1, |
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558 ABB_OUTEN2, |
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559 ABB_OUTEN3, |
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560 ABB_AULGA, |
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561 ABB_AURGA |
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562 }; |
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563 #endif |
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564 |
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565 /*************************************/ |
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566 /* DRP WRAPPER Table */ |
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567 /*************************************/ |
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568 #define DRP_WRAPPER_TABLE_SIZE 3 |
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569 |
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570 enum DRP_WRAPPER_REGISTERS { |
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571 DRP_WRAPPER_APCCTRL2 = 0, |
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572 DRP_WRAPPER_APCDEL1, |
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573 DRP_WRAPPER_APCDEL2 |
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574 }; |
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575 |
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576 extern T_RF_BAND rf_band[]; |
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577 #endif //__L1_RF_H |