FreeCalypso > hg > freecalypso-citrine

annotate L1/include/l1_time.h @ 33:6a2b09d3b1b4

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disable L1_DYN_DSP_DWNLD and AMR by default
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 15 Oct 2016 04:23:58 +0000
parents f93dab57b032
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /************* Revision Controle System Header *************
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2 * GSM Layer 1 software
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3 * L1_TIME.H
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4 *
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5 * Filename l1_time.h
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6 * Copyright 2003 (C) Texas Instruments
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7 *
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8 ************* Revision Controle System Header *************/
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9
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10 // *********************************************************************
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11 // * *
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12 // * This file contains only RF independant defines. *
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13 // * *
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14 // *********************************************************************
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15 // Remarks:
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16 // --------
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17 // PRG_TX is RF dependant, it is therefore provided within
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18 // "l1_rf#.h".
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19 // **************************************************************************
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20 //
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21 // measurements
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22 // ------------
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23 //
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24 // | +-----+
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25 // | | PW |
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26 // -------------------|--------+ +--------------
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27 // clk=offset | |
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28 // (frame int.) >|-----|<-PW_BURST_DURATION
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29 // | | |
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30 // | SYNTH_SETUP_TIME | |
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31 // |<--------------------------|< |
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32 // | | |
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33 // | |
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34 // >|--------|<-PROVISION_TIME
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35 //
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36 //
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37 // Normal Burst reception
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38 // ----------------------
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39 //
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40 // | +---------+
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41 // | | RX WIN |
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42 // ---------------------|--------+ +----------
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43 // clk=offset | |
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44 // (frame int.) >|---------|<-NB_BURST_DURATION_DL
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45 // | | |
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46 // | SYNTH_SETUP_TIME | |
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47 // |<--------------------------|< |
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48 // | | |
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49 // | |
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50 // >|--------|<-PROVISION_TIME
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51 //
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52 //
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53 // Normal Burst transmission
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54 // -------------------------
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55 //
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56 // .
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57 // +---------+
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58 // | TX WIN |
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59 // --------------------------+ +----------
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60 // . |
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61 // clk=offset |
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62 // . |
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63 // . |<--STOP_TX_**
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64 // | SYNTH_SETUP_TIME .
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65 // |<---------------------->.<--START_TX
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66 // | .
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67 //
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68 //
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69 //
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70 // Frequency Burst search in Dedicated TCH
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71 // ---------------------------------------
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72 //
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73 // . +-----------(...)-------------+
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74 // . | FB search in TCH |
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75 // -------------------.--------+ +--------------
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76 // . | |
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77 // (FB26_ANCHORING_TIME)| |
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78 // . | |
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79 // SYNTH_SETUP_TIME | |
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80 // |<------------------------->| |<-STOP_RX_FB26
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81 // . |
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82 // . |<-START_RX_FB26
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83 // . |
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84 // . |
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85 // >.--------|<-PROVISION_TIME
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86 //
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87 //
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88 // **************************************************************************
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89
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90
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91 #define D_NSUBB_IDLE 296L // Nb of 48 samples window for FBNEW task.
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92 #if (CODE_VERSION==SIMULATION)
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93 #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task.
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94 #else
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95 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 32) || (DSP == 36)
0
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96 #define D_NSUBB_DEDIC 30L // Nb of 48 samples window for FB26 task.
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97 #else
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98 #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task.
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99 #endif
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100 #endif
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101
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102
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103 #define IMM ( 5000L ) // Immediate command for TPU.
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104 #define TN_WIDTH ( 625L )
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105 #define BP_DURATION TN_WIDTH
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106 #define TAIL_WIDTH ( 3L * 4L ) // = 12
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107 #define EXTENDED_TAIL_WIDTH ( 8L * 4L )
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108 #define TPU_CLOCK_RANGE ( 5000L )
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109 #define SWITCH_TIME ( TPU_CLOCK_RANGE - EPSILON_SYNC ) // = 4990, time for offset change.
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110
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111 #define PROVISION_TIME ( 66L )
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112 #define EPSILON_SYNC ( 10L ) // synchro change: max TOA shift=8qbits, 2qbits TPU scenario exec.
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113 #define EPSILON_OFFS ( 2L ) // offset change: 2qbits for TPU scenario exec.
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114 #define EPSILON_MEAS ( 20L ) // margin kept between RX and PW meas or between PW meas
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115 #define SERV_OFFS_REST_LOAD ( 1L ) // 1qbit TPU scen exec. for serv. cell offset restore
0
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116 #define TPU_SLEEP_LOAD ( 2L ) // 2qbit TPU scen exec. for TPU sleep
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117 #if (CODE_VERSION==SIMULATION)
3
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118 #define DL_ABB_DELAY ( 32L ) // RX ABB filter delay
0
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119 #else
3
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120 #define DL_ABB_DELAY ( 32L + 4L) // RX ABB filter delay
0
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121 #endif
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122
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123 // DMA threshold used for sample acquisition by the DSP
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124 #if (CODE_VERSION==SIMULATION)
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125 #define RX_DMA_THRES ( 1L )
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126 #else
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127 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
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128 #define RX_DMA_THRES ( 2L )
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129 #else
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130 #define RX_DMA_THRES ( 1L )
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131 #endif
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132 #endif
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133
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134 // BDLENA durations are calculated for a DMA threshold of 1
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135 // For a DMA threshold > 1 additional I/Q samples have to be acquired
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136 // An increase of BDLENA length by 2qbit is sufficient to acquire one additional I/Q sample
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137 // (ABB always outputs pairs of I/Q samples)
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138 #define RX_DMA_DELAY (RX_DMA_THRES - 1) * 2
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139
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140 #if (CODE_VERSION==SIMULATION)
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141 #define TULSET_DURATION ( 16L ) // Uplink power on setup time
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142 #define BULRUDEL_DURATION ( 2L )
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143 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
0
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144 // 16 qbits are added because the Calibration time is reduced of 4 GSM bit
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145 // due to a slow APC ramp of OMEGA (Cf. START_TX_NB)
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146 #define UL_VEGA_DELAY ( TULSET_DURATION + BULRUDEL_DURATION +16L ) // = 18qbits, TX Vega delay
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147 #endif
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148 #endif
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149
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150 #define SB_MARGIN ( 23L * 4L ) // = 92
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151 #define NB_MARGIN ( 3L * 4L ) // = 12
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152 #define TA_MAX ( 63L * 4L ) // = 252
0
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153
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154 #define SB_BURST_DURATION ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation
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155 #define NB_BURST_DURATION_DL ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation
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156 #define PW_BURST_DURATION ( 64L * 4L ) // = 256
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157 #define RA_BURST_DURATION ( EXTENDED_TAIL_WIDTH + TAIL_WIDTH + ( 77L * 4L ) ) // = 352 = 88*4
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158 #define NB_BURST_DURATION_UL ( 2*TAIL_WIDTH + ( 142L * 4L) ) // = 592 = 148 * 4
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159
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160 // PRG_TX has become a variable and will be substracted directly in the code
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161 #define TIME_OFFSET_TX ( PROVISION_TIME + (3L * TN_WIDTH)) // = 1902, Offset difference for TX with TA=0.
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162
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163 //================================
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164 // Definitions used by TPU drivers
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165 //================================
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166
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167 // BENA durations...
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168 //------------------
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169 #define SB_ACQUIS_DURATION ( SB_MARGIN + SB_BURST_DURATION + SB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 796 + DMA delay
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170 #define NB_ACQUIS_DURATION ( NB_MARGIN + NB_BURST_DURATION_DL + NB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 636 + DMA delay
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171 #define PW_ACQUIS_DURATION ( PW_BURST_DURATION + DL_ABB_DELAY + RX_DMA_DELAY ) // = 288 + DMA delay
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172 #define FB_ACQUIS_DURATION ( ( D_NSUBB_IDLE * 48L * 4L ) + ( 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY ) // = 57056 + DMA delay
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173 #define FB26_ACQUIS_DURATION ( ( D_NSUBB_DEDIC * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay
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174
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175 #define START_RX_FB ( PROVISION_TIME ) // = 66
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176 #define START_RX_SB ( PROVISION_TIME ) // = 66
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177 #define START_RX_SNB ( PROVISION_TIME ) // = 66
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178 #define START_RX_PW_1 ( PROVISION_TIME ) // = 66
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179 #define START_RX_FB26 ( PROVISION_TIME ) // = 66
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180
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181 #define START_TX_NB ( 0L )
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182 #define START_TX_RA ( 0L )
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183
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184 #define STOP_RX_FB ( (PROVISION_TIME + FB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 2122
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185 #define STOP_RX_SB ( (START_RX_SB + SB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 862
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186 #define STOP_RX_SNB ( (START_RX_SNB + NB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 702
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187 #define STOP_RX_PW_1 ( (START_RX_PW_1 + PW_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 354
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188 #define STOP_RX_FB26 ( (START_RX_FB26 + FB26_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 4314
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189
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190
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191 //================================
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192 // Definitions used for GPRS
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193 //================================
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194
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195 #if L1_GPRS
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196 #ifdef L1P_DRIVE_C
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197
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198 // Window positions for RX normal burst reception durations
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199 const UWORD16 RX_DOWN_TABLE[8] =
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200 {
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201 PROVISION_TIME + NB_ACQUIS_DURATION, //special case: only 1 RX, 151 IQ samples
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202 PROVISION_TIME + 2*BP_DURATION + DL_ABB_DELAY, // 2 * 156.25 samples
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203 PROVISION_TIME + 3*BP_DURATION + DL_ABB_DELAY, // 3 * 156.25 samples
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204 PROVISION_TIME + 4*BP_DURATION + DL_ABB_DELAY, // 4 * 156.25 samples
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205 PROVISION_TIME + 5*BP_DURATION + DL_ABB_DELAY, // 5 * 156.25 samples
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206 PROVISION_TIME + 6*BP_DURATION + DL_ABB_DELAY, // 6 * 156.25 samples
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207 PROVISION_TIME + 7*BP_DURATION + DL_ABB_DELAY, // 7 * 156.25 samples
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208 PROVISION_TIME + 8*BP_DURATION + DL_ABB_DELAY // 8 * 156.25 samples
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209 };
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diff changeset
210
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diff changeset
211 // Window positions for TX normal burst and PRACH transmission
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parents:
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212 const UWORD16 TX_TABLE[8] =
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213 {
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214 0,
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215 BP_DURATION,
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216 2*BP_DURATION,
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217 3*BP_DURATION,
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218 4*BP_DURATION,
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219 5*BP_DURATION,
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220 6*BP_DURATION,
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221 7*BP_DURATION
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222 };
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223
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224 #else
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225
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226 extern UWORD16 RX_DOWN_TABLE[8];
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227 extern UWORD16 TX_TABLE[8];
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228
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229 #endif
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230 #endif
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231
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232 //===============================================
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233 // New Definitions for new WIN-ID implementation
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234 //===============================================
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235
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236 #define BP_SPLIT_PW2 5
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237 #define BP_SPLIT 32
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238 #define FRAME_SPLIT 8*BP_SPLIT
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parents:
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239
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parents:
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240 // Load for TPU activity according to frame split
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241 #define PWR_LOAD 1 + PW_ACQUIS_DURATION / (BP_DURATION/BP_SPLIT)
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242 #define RX_LOAD 1 + NB_ACQUIS_DURATION / (BP_DURATION/BP_SPLIT)
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parents:
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243
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244 #if L1_GPRS
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245 #ifdef L1P_DRIVE_C
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246
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parents:
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247 // RX split load in case of multislot
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248 const UWORD16 RX_SPLIT_TABLE[8] =
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parents:
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249 {
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parents:
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250 1 + (NB_ACQUIS_DURATION ) / (BP_DURATION/BP_SPLIT),
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parents:
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251 1 + (2*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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252 1 + (3*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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253 1 + (4*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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254 1 + (5*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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255 1 + (6*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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256 1 + (7*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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257 1 + (8*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT)
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parents:
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258 };
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parents:
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259
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parents:
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260 #else
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parents:
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261
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parents:
diff changeset
262 extern UWORD16 RX_SPLIT_TABLE[8];
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parents:
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263
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parents:
diff changeset
264 #endif
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parents:
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265 #endif
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parents:
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266