FreeCalypso > hg > freecalypso-citrine

annotate L1/tpudrv/tpudrv10.h @ 33:6a2b09d3b1b4

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disable L1_DYN_DSP_DWNLD and AMR by default
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 15 Oct 2016 04:23:58 +0000
parents 75a11d740a02
children
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1 /****************** Revision Controle System Header ***********************
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2 * GSM Layer 1 software
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3 * Copyright (c) Texas Instruments 1998
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4 *
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5 * Filename tpudrv10.h
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6 * Copyright 2003 (C) Texas Instruments
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7 *
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8 ****************** Revision Controle System Header ***********************/
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9
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10 #define BIT_0 0x000001
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11 #define BIT_1 0x000002
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12 #define BIT_2 0x000004
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13 #define BIT_3 0x000008
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14 #define BIT_4 0x000010
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15 #define BIT_5 0x000020
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16 #define BIT_6 0x000040
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17 #define BIT_7 0x000080
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18 #define BIT_8 0x000100
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19 #define BIT_9 0x000200
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20 #define BIT_10 0x000400
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21 #define BIT_11 0x000800
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22 #define BIT_12 0x001000
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23 #define BIT_13 0x002000
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24 #define BIT_14 0x004000
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25 #define BIT_15 0x008000
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26 #define BIT_16 0x010000
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27 #define BIT_17 0x020000
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28 #define BIT_18 0x040000
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29 #define BIT_19 0x080000
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30 #define BIT_20 0x100000
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31 #define BIT_21 0x200000
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32 #define BIT_22 0x400000
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33 #define BIT_23 0x800000
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34
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35
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36 //TRF6150 definitions
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37 #define MODE0 0x000000
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38 #define MODE1 0x000001
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39 #define MODE2 0x000002
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40 #define MODE3 0x000003
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41 #define MODE4 0x000004
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42 #define MODE5 0x000005
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43 #define MODE6 0x000006
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44 #define MODE7 0x000007
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45
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46 #define REGUL_ON BIT_3 //MODE0
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47 #define BG_SPEEDUP BIT_4 //MODE0
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48 #define RX_ON_CLARA BIT_5 //MODE0
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49 #define TX_ON_CLARA BIT_6 //MODE0
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50 #define PA_CTRLR_ON BIT_7 //MODE0
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51 #define AUX_SYNTH_ON BIT_8 //MODE0
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52 #define MAIN_SYNTH_OFF 0x000000 //MODE0
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53 #define MAIN_SYNTH_ON_RX BIT_9 //MODE0
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54 #define MAIN_SYNTH_ON_TX BIT_10 //MODE0
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55 #define DCO_COMP_ON BIT_11 //MODE0
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56 #define DCO_COMP_RUN BIT_12 //MODE0
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57 #define BAND_SELECT_GSM BIT_13 //MODE0
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58 #define BAND_SELECT_850 BIT_13 //MODE0
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59 #define BAND_SELECT_PCS BIT_14 //MODE0
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60 #define BAND_SELECT_DCS (BIT_14 | BIT_13)
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61
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62 #define RX_RF_GAIN BIT_15 //MODE0
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63
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64 // MODE1 is only for Receiver gain programming (AGC)
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65
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66 #define AUX_SHDW_ADD(arfcn) ((arfcn >= 822) && (arfcn <= 885)) ? BIT_3 : 0 //MODE2
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67 #define AUX_SHDW_RCL BIT_4 //MODE2
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68 #define MAIN_FCU_REG_100 BIT_7 //MODE2
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69 #define PA_CTRL_I_DIOD BIT_23 //MODE2
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71 //MODE3
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72 #define TEST_MODE BIT_3 //MODE3
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73 #define HB_OPLL_PRECHARGE BIT_4 //MODE3
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74
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75 #define HB_OPLL_CP_CUR_0_125MA 0x000000 //0.125 mA
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76 #define HB_OPLL_CP_CUR_0_25MA BIT_5 //0.25 mA
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77 #define HB_OPLL_CP_CUR_0_5MA BIT_6 //0.5 mA
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78 #define HB_OPLL_CP_CUR_1MA (BIT_6 | BIT_5) //1 mA
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79 #define HB_OPLL_CP_CUR_2MA BIT_7 //2 mA
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80
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81 #define LB_OPLL_PRECHARGE BIT_8 //MODE3
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83 #define LB_OPLL_CP_CUR_0_125MA 0x000000 //0.125 mA
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84 #define LB_OPLL_CP_CUR_0_25MA BIT_9 //0.25 mA
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85 #define LB_OPLL_CP_CUR_0_5MA BIT_10 //0.5 mA
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86 #define LB_OPLL_CP_CUR_1MA (BIT_10 | BIT_9) //1 mA
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87 #define LB_OPLL_CP_CUR_2MA BIT_11 //2 mA
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88
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89 #define CLK_REF BIT_17 //MODE3
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90 #define MAIN_VCO_EN BIT_18 //MODE3
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91 #define AUX_VCO_EN BIT_19 //MODE3
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92 #define EXT_VCO_CONTROL BIT_20 //MODE3
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93 #define TEMP_SENSOR_EN BIT_21 //MODE3
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95 //MODE4
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96 #define MAIN_TIMER_RX_49_2US BIT_6 //MODE4
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97 #define MAIN_TIMER_RX_55_35US ( 8 << 3) //added 30.01.02
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98 #define MAIN_TIMER_RX_61_5US (10 << 3)
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99 #define MAIN_TIMER_RX_78_9US (13 << 3)
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100 #define MAIN_TIMER_RX_91_9US (15 << 3)
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101 #define MAIN_TIMER_RX_98_4US (16 << 3)
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102 #define MAIN_TIMER_RX_159_9US (26 << 3) //added 21.08 CR
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103
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104
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diff changeset
105 #define MAIN_TIMER_TX_49_2US BIT_11 //MODE4
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
106 #define MAIN_TIMER_TX_61_5US (10 << 8) //added 30.01.02
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
107 #define MAIN_TIMER_TX_104US (17 << 8) //added for RS
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
108 #define MAIN_TIMER_TX_98_4US (16 << 8)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
109 #define MAIN_TIMER_TX_123US (20 << 8) //added 21.08 CR
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
110
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
111 #define MAIN_CP_CUR_0 0x000000 //MODE4 400uA, 1.6mA
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
112 #define MAIN_CP_CUR_1 BIT_21 //MODE4 400uA, 3.2mA
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
113 #define MAIN_CP_CUR_2 BIT_22 //MODE4 800uA, 3.2mA
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
114 #define MAIN_CP_CUR_3 (BIT_22 | BIT_21)//MODE4 same as 2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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115
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
116 #define FC_60 (60 << 13)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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117 #define FC_63 (63 << 13)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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118 #define FC_70 (70 << 13)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
119 #define FC_100 (100 << 13)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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120 #define FC_109 (109 << 13)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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121 #define FC_110 (110 << 13)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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122
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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123 //MODE5
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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124 #define SHDW_LOAD BIT_3 //MODE5
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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125 #define AUX_PRG_MOD BIT_4 //MODE5
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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126 #define AUX_PFD BIT_14 //MODE5
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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127
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
128 //MODE6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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129 #define FREQ_CAL_ON BIT_4 //MODE6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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130 #define FREQ_CAL_MODE BIT_5 //MODE6
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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131
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
132 //MODE7
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
133 #define FREQ_CAL_DATA (0xd << 19) // 6.15 (00000)-8.88 (01101)-12.66 pF (11111)- modified CR 11.09.01, was (0xb << 19)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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134
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 // RF signals connected to TSPACT [0..7]
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137 //#define RESET_RF BIT_0 // act0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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138 #define CLA_SER_ON BIT_0 // act0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 #define CLA_SER_OFF 0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 #define TXVCO_ON 0 // act3 inverted
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 #define TXVCO_OFF BIT_3
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142 #define TX_ON BIT_5 // act5
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 #define TX_OFF 0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 // RF signals connected to TSPACT for Titanium v2.2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 #if 0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 //B-Sample
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 #define PA900_ON BIT_2 // signals are inverted therefore PA900_ON act1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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149 #define PA1800_ON BIT_1 // and PA1800_ON act2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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150 #define PA900_OFF BIT_1 //
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 #define PA1800_OFF BIT_2 //
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154 #if 0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 //C-Sample
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156 #define PA900_ON BIT_1 // signals are inverted therefore PA900_ON act1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 #define PA1800_ON BIT_2 // and PA1800_ON act2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 #define PA900_OFF BIT_2 //
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 #define PA1800_OFF BIT_1 //
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 #if 1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 //D-Sample
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 #define PA900_ON BIT_1 // signals are inverted therefore PA900_ON act1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165 #define PA1800_ON BIT_2 // and PA1800_ON act2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 #define RX1900_ON 0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167 #define PA900_OFF BIT_2 //
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 #define PA1800_OFF BIT_1 //
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 #define RX1900_OFF BIT_4
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 //RX_UP/DOWN and TX_UP/DOWN
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172 #define RU_900 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 #define RD_900 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 #define TU_900 (PA900_ON | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175 #define TD_900 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 #define TU_REV_900 (PA900_OFF | PA1800_ON | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 #define RU_850 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 #define RD_850 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 #define TU_850 (PA900_ON | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 #define TD_850 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182 #define TU_REV_850 (PA900_OFF | PA1800_ON | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 #define RU_1800 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 #define RD_1800 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 #define TU_1800 (PA900_OFF | PA1800_ON | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187 #define TD_1800 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 #define TU_REV_1800 (PA900_ON | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 #define RU_1900 (PA900_OFF | PA1800_OFF | RX1900_ON)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 #define RD_1900 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192 #define TU_1900 (PA900_OFF | PA1800_ON | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 #define TD_1900 (PA900_OFF | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 #define TU_REV_1900 (PA900_ON | PA1800_OFF | RX1900_OFF)
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 #endif
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 #define TC1_DEVICE_ABB TC1_DEVICE0
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 #define TC1_DEVICE_RF TC1_DEVICE2
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203 #define SL_SU_DELAY1 4 // No. bits to send + load data to shift + send write cmd + 1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 #define SL_SU_DELAY2 3 // load data to shift + send write cmd + 1
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 #define SL_SU_DELAY3 5 // SL_SU_DELAY1 + serialization
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 #define DLT 20 // (TRF6150) DownLoadTime
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209 #define DLT_1 1 // 1 tpu instruction = 1 qbit
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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210 #define DLT_2 2
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211 #define DLT_3 3
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212
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213 #define DLT_1B 4 // 3*move + 1*byte (download)
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214 #define DLT_2B 6 // 4*move + 2*byte
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215 #define DLT_3B 8 // 5*move + 3*byte
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216
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217 //#define crch_timing 420//250//420//0 // CR d.07.08.01 - Temperary movement of Rx and Tx timing for Titanium. Will be set to 0 when new LF is ready.
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218 #define rdt 0//359 // rx delta timing
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219 #define tdt 0//293 // tx delta timing
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220
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221 /*------------------------------------------*/
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222 /* Download delay values */
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223 /*------------------------------------------*/
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224 // 0.9230769 usec ~ 1 qbit i.e. 200 usec is ~ 217 qbit
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225
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226 #define T TPU_CLOCK_RANGE
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227
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228 #define TRF_I7 334 //qbit
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229 #define TRF_I8 378 //qbit
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230
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231 // time below are offset to when BDLENA goes low
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232 #define TRF_R15 ( 0 - DLT_1B) // 0, BDLENA low, needs DLT_1B to execute
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233 #define TRF_R13 ( - 32 - DLT_1B) // 8 right after, power off transceiver
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234
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235 //burst data comes here
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236 // time below are offset to when BDLENA goes high
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237 #define TRF_R12 (PROVISION_TIME - 0 - DLT_1B) // BDLENA i/q comes 32qbit later
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238 #define TRF_R10 (PROVISION_TIME - 8 - DLT_1B) // Set RX/TX switch (not really necessary as the default setting is RX mode)
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239 #define TRF_R9 (PROVISION_TIME - 16 - DLT_2B) // RX_ON_CLARA
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240 #define TRF_R7 (PROVISION_TIME - 66 - DLT_1B) // 67qbit duration BDLON + BDLCAL
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241 #define TRF_R6 (PROVISION_TIME - 83 - DLT_1B) // BDLON, RX_ON_CLARA
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242 #define TRF_R5 (PROVISION_TIME - 172 - DLT_2B - rdt) // DC offset comp. start LNA ON
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243 //#define TRF_R4 (PROVISION_TIME - 172 - DLT_2B - rdt) // DC offset comp. LNA
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244 #define TRF_R3 (PROVISION_TIME - 177 - DLT_2B - rdt) // DC offset comp. GAIN
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245 //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst
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246 //#define TRF_R2_1 (PROVISION_TIME - 199 - DLT_2B - rdt) // fc
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247 //#define TRF_R2 (PROVISION_TIME - 199 - DLT_2B - rdt) // select band
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248 #define TRF_R1 (PROVISION_TIME - 209 - DLT_3B - rdt) // Main PLL + set of Main PLL FC & CP current
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249
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250
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251 // time below are offset to when BULENA goes low
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252 #define TRF_T17 ( 32 - SL_SU_DELAY2) // right after, BULON low
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253 //#define TRF_T17 ( 32 ) // right after, BULON low
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254 #define TRF_T16 ( 26 - DLT_1B) // Power down Clara
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255 #define TRF_T15 ( 14 - DLT_1) // disable TX_ON
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256 #define TRF_T14 ( 0 - DLT_1B) // BULENA off
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257 #define TRF_T13_3 (- 40 - DLT_1B) // ADC read
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258 //burst data comes here
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259 // time below are offset to when BULENA goes high
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260 #define TRF_T13_2 ( 25 - DLT_1) // TX_ON
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261 #define TRF_T13_1 ( 17 - DLT_1) // set rf switch
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262 #define TRF_T12 (- 0 - DLT_1B) // BULENA Start of TX burst
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263 #define TRF_T10 (- 70 - DLT_3B - tdt) // normal speed
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264 #define TRF_T9 (- 121 - DLT_2B - tdt) // Power up TXVCO
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265 #define TRF_T8 (- 127 - DLT_1B - tdt) // BULON, disable BULCAL
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266 #define TRF_T7 (- 127 - DLT_1B - tdt) // 131 BULON, disable BULCAL
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267 #define TRF_T6 (- 137 - DLT_3B - tdt) // Speed up
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268 #define TRF_T4 (- 249 - DLT_1B - tdt) // prog AUX PLL & detector polarity
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269 #define TRF_T3_1 (- 258 - DLT_2B - tdt) // fc
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270 #define TRF_T3 (- 258 - DLT_2B - tdt) // 20 BULON + BULCAL + select band
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271 #define TRF_T2 (- 267 - DLT_3B - tdt) // set of Main PLL FC & CP current
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272 #define TRF_T1 (- 277 - DLT_3B - tdt) // BULON + Main PLL
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273
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274
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275 /*------------------------------------------*/
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276 /* Is arfcn in the DCS band (512-885) ? */
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277 /*------------------------------------------*/
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278 // is working only for GSM and DCS (not PCN)
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279 #define IS_DCS_HIGH(arfcn) (((arfcn >= 576) && (arfcn <= 885))? 1 : 0) //Changed by CR 30.08.01, was (((arfcn >= 822) && (arfcn <= 885))? 1 : 0)
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280
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281 #ifdef TPUDRV10_C
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282
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283 #endif
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284
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285