FreeCalypso > hg > freecalypso-citrine
annotate bsp/abb+spi/spi_pool_size.h @ 23:7155882cc49d
cfgmagic/processconf.sh: enable L1_DYN_DSP_DWNLD by default
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 10 Jun 2016 09:33:29 +0000 |
parents | 75a11d740a02 |
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Mychaela Falconia <falcon@freecalypso.org>
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1 /** |
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2 * @file spi_pool_size.h |
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3 * |
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4 * Declarations of: |
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Mychaela Falconia <falcon@freecalypso.org>
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5 * - the memory bank sizes and their watermark |
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Mychaela Falconia <falcon@freecalypso.org>
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6 * - the SWE stack size |
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Mychaela Falconia <falcon@freecalypso.org>
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7 * - the pool size needed (generally the sum of memory bank and stack sizes) |
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8 * |
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9 * @author Vincent Oberle |
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10 * @version 0.1 |
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11 */ |
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12 |
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13 /* |
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14 * History: |
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15 * |
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16 * Date Author Modification |
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17 * ------------------------------------------------------------------- |
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18 * 07/08/2003 Vincent Oberle Extracted from rvf_pool_size.h |
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19 * |
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20 * (C) Copyright 2003 by Texas Instruments Incorporated, All Rights Reserved |
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21 */ |
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22 |
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23 #ifndef __SPI_POOL_SIZE_H_ |
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24 #define __SPI_POOL_SIZE_H_ |
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25 |
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26 |
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27 /* |
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28 * Values used in spi_env.h |
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29 */ |
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30 #define SPI_STACK_SIZE (1000) |
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31 #define SPI_MB1_SIZE (256) |
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32 #define SPI_POOL_SIZE (SPI_STACK_SIZE + SPI_MB1_SIZE) |
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33 |
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34 |
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35 #endif /*__SPI_POOL_SIZE_H_*/ |