FreeCalypso > hg > freecalypso-citrine
annotate L1/cust0/mv100/l1_rf10.h @ 40:b56928f8c001
doc/Firmware_Architecture: stale links to docs updated
to new FTP and web locations
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 07 May 2017 16:20:07 +0000 |
parents | 75a11d740a02 |
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rev | line source |
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * |
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4 * Filename l1_rf10.h |
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5 * Version 1.18 |
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6 * Date 01/21/03 |
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7 * |
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8 ************* Revision Controle System Header *************/ |
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9 |
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10 // is this defined somewhere else? |
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11 //#define RF_HW_BAND_EGSM |
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12 //#define RF_HW_BAND_DCS |
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13 #define RF_HW_BAND_PCS 0x4 |
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14 #define RF_HW_BAND_DUAL_US 0x80 |
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15 #define RF_HW_BAND_DUAL_EXT 0x20 |
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16 |
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17 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS |
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18 /************************************/ |
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19 /* SYNTHESIZER setup time... */ |
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20 /************************************/ |
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21 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit. |
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22 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit. |
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23 |
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24 /************************************/ |
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25 /* time for TPU scenario ending... */ |
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26 /************************************/ |
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27 #define RX_TPU_SCENARIO_ENDING 0 // execution time of BDLENA down |
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28 // contained in serialization time |
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29 #define TX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 + 1 // execution time of BULON down |
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30 // minus serialization time + 1 TPU_MOVE |
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31 |
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32 /******************************************************/ |
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33 /* TXPWR configuration... */ |
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34 /* Fixed TXPWR value when GSM management is disabled. */ |
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35 /******************************************************/ |
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36 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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37 // #define FIXED_TXPWR 0x3f12 // TXPWR=10, value=252 |
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38 //#define FIXED_TXPWR 0x1952 |
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39 #define FIXED_TXPWR 0x1d12 // TXPWR=15 |
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40 #endif |
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41 |
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42 |
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43 /************************************/ |
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44 /* ANALOG delay (in qbits) */ |
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45 /************************************/ |
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46 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal |
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47 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block |
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48 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block |
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49 #if (ANALOG == 1) |
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50 #define UL_ABB_DELAY 6 // modulator input to output delay |
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51 #endif |
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52 #if ((ANALOG == 2) || (ANALOG == 3)) |
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53 #define UL_ABB_DELAY 3 // modulator input to output delay |
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54 #endif |
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55 |
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56 /************************************/ |
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57 /* TX Propagation delay... */ |
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58 /************************************/ |
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59 #if (ANALOG == 1) |
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60 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40 |
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61 #endif |
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62 #if (ANALOG == 2) || (ANALOG == 3) |
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63 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY + 2) // = 42 |
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64 #endif |
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65 |
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66 /************************************/ |
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67 /* Initial value for APC DELAY */ |
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68 /************************************/ |
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69 #if (ANALOG == 1) |
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70 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 |
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71 #define APCDEL_DOWN 2 // minimum value: 2 |
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72 #define APCDEL_UP (6+5) // minimum value: 6 |
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73 #endif |
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74 #if (ANALOG == 2) || (ANALOG == 3) |
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75 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 |
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76 #define APCDEL_DOWN (2+0) // minimum value: 2 |
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77 #define APCDEL_UP (6+8) // minimum value: 6 |
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78 #endif |
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79 |
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80 #define GUARD_BITS 8 |
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81 |
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82 /************************************/ |
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83 /* Initial value for AFC... */ |
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84 /************************************/ |
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85 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced) |
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86 |
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87 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames |
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88 // Clara (RF=10) LDO wakeup requires 3 frames |
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89 |
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90 /************************************/ |
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91 /* Baseband registers */ |
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92 /************************************/ |
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93 #if (ANALOG == 1) |
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94 // Omega registers values will be programmed at 1st DSP communication interrupt |
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95 #define C_DEBUG1 0x0000 // Enable f_tx delay of 400000 cyc DEBUG |
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96 #define C_AFCCTLADD 0x002a | TRUE // Value at reset |
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97 #define C_VBUR 0x418e | TRUE // Uplink gain amp 0dB, Sidetone gain to mute |
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98 #define C_VBDR 0x098c | TRUE // Downlink gain amp 0dB, Volume control 0 dB |
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99 #define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // value at reset-Changed from 0x0016- CR 27.12 |
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100 #define C_BULIOFF 0x3fc4 | TRUE // value at reset |
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101 #define C_BULQOFF 0x3fc6 | TRUE // value at reset |
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102 #define C_DAI_ON_OFF 0x0000 // value at reset |
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103 #define C_AUXDAC 0x0018 | TRUE // value at reset |
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104 #define C_VBCR 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1 |
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105 // BULRUDEL will be initialized on rach only .... |
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106 #define C_APCDEL (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004) |
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107 #define C_BBCTL 0x604c | TRUE // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified' |
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108 #endif |
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109 #if (ANALOG ==2) |
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110 // IOTA registers values will be programmed at 1st DSP communication interrupt |
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111 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG |
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112 #define C_AFCCTLADD 0x002a | TRUE // Value at reset |
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113 #define C_VBUR 0x418e | TRUE // No uplink mute, Side tone mute, PGA_UL 0dB |
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114 #define C_VBDR 0x098c | TRUE // PGA_DL 0dB, Volume 0dB |
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115 #define C_APCOFF 0x1016 | (0x28 << 6) | TRUE // value at reset-Changed from 3c to 28 CR 17.11.02// x2 slope 128 |
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116 #define C_BULIOFF 0x3fc4 | TRUE // value at reset |
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117 #define C_BULQOFF 0x3fc6 | TRUE // value at reset |
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118 #define C_DAI_ON_OFF 0x0000 // value at reset |
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119 #define C_AUXDAC 0x0018 | TRUE // value at reset |
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120 #define C_VBCR 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1 |
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121 #define C_VBCR2 0x0016 | TRUE // MICBIASEL=0, VDLHSO=0, MICAUX=0 |
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122 // BULRUDEL will be initialized on rach only .... |
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123 #define C_APCDEL (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004) |
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124 #define C_APCDEL2 0x0034 |
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125 #define C_BBCTL 0xb04c | TRUE // External RX I/Q DC offset calibration, Output common mode=1.35V |
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126 // Monoslot, Vpp=8/15*Vref |
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127 #define C_BULGCAL 0x001c | TRUE // IAG=0 dB, QAG=0 dB |
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128 #endif |
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129 |
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130 #if (ANALOG == 3) |
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131 // SYREN registers values will be programmed at 1st DSP communication interrupt |
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132 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG |
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133 #define C_AFCCTLADD 0x002a | TRUE // Value at reset |
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134 #define C_VBUR 0x1E6<<6 | VBUCTRL | TRUE // Side tone mute, PGA_UL 0dB |
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135 #define C_VBDR 0x026<<6 | VBDCTRL | TRUE // PGA_DL 0dB, Volume 0dB |
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136 #define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // x2 slope 128, APCSWP = 0 |
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137 #define C_BULIOFF 0x3fc4 | TRUE // value at reset |
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138 #define C_BULQOFF 0x3fc6 | TRUE // value at reset |
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139 #define C_DAI_ON_OFF 0x0000 // value at reset |
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140 #define C_AUXDAC (0x00<<6) | 0x18 | TRUE // value at reset |
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141 #define C_VBCR (0x108<<6) | 0x10 | TRUE // VULSWITCH=1 AUXI 28,2 dB |
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142 #define C_VBCR2 (0x01<<6) | 0x16 | TRUE // HSMIC on, SPKG gain @ 2,5dB |
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143 // BULRUDEL will be initialized on rach only .... |
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144 #define C_APCDEL (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004) |
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145 #define C_APCDEL2 0x0034 |
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146 #define C_BBCTL 0xB04c | TRUE // External autocalibration, Output common mode=1.35V |
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147 // Monoslot, Vpp=8/15*Vref |
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148 #define C_BULGCAL 0x001c | TRUE // IAG=0 dB, QAG=0 dB |
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149 |
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150 #define C_VBPOP (0x4)<<6 | 0x14 | TRUE // HSOAUTO enabled only |
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151 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames |
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152 #define C_VAUDCR (0x0)<<6 | 0x1e | TRUE // Init to zero |
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153 #define C_VAUOCR (0x155)<<6 | VAUOCTRL | TRUE // Sppech on all outputs |
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154 #define C_VAUSCR (0x0)<<6 | 0x20 | TRUE // Init to zero |
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155 #define C_VAUDPLL (0x0)<<6 | 0x24 | TRUE // Init to zero |
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156 |
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157 #endif |
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158 |
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159 |
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160 /************************************/ |
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161 /* Automatic frequency compensation */ |
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162 /************************************/ |
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163 /********************* C_Psi_sta definition *****************************/ |
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164 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */ |
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165 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */ |
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166 /* regarding Vega V/N = 2.4/4096 */ |
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167 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */ |
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168 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */ |
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169 /* = 0.000195748 */ |
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170 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */ |
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171 /************************************************************************/ |
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172 #define C_Psi_sta_inv 4174L // (1/C_Psi_sta) |
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173 #define C_Psi_st 13L // C_Psi_sta * 0.8 F0.16 |
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174 #define C_Psi_st_32 823216L // F0.32 |
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175 #define C_Psi_st_inv 5217L // (1/C_Psi_st) |
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176 |
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177 #if (VCXO_ALGO == 1) |
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178 // Linearity parameters |
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179 #define C_AFC_DAC_CENTER ((111)*8) |
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180 #define C_AFC_DAC_MIN ((-1196)*8) |
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181 #define C_AFC_DAC_MAX ((1419)*8) |
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182 |
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183 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10 |
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184 #endif |
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185 |
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186 typedef struct |
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187 { |
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188 WORD16 eeprom_afc; |
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189 UWORD32 psi_sta_inv; |
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190 UWORD32 psi_st; |
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191 UWORD32 psi_st_32; |
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192 UWORD32 psi_st_inv; |
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193 |
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194 #if (VCXO_ALGO == 1) |
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195 // VCXO adjustment parameters |
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196 // Parameters used when assuming linearity |
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197 WORD16 dac_center; |
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198 WORD16 dac_min; |
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199 WORD16 dac_max; |
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200 WORD16 snr_thr; |
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201 #endif |
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202 } |
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203 T_AFC_PARAMS; |
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204 |
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205 /************************************/ |
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206 /* Swap IQ definitions... */ |
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207 /************************************/ |
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208 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */ |
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209 #define SWAP_IQ_GSM 0 |
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210 #define SWAP_IQ_DCS 2 // was 2 for sara version 1 |
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211 #define SWAP_IQ_PCS 2 |
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212 #define SWAP_IQ_GSM850 0 //TBD |
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213 |
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214 /************************************/ |
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215 /************************************/ |
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216 // typedef |
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217 /************************************/ |
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218 /************************************/ |
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219 |
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220 /*************************************************************/ |
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221 /* Define structure for apc of TX Power ******/ |
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222 /*************************************************************/ |
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223 typedef struct |
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224 { // pcm-file "rf/tx/level.gsm|dcs" |
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225 UWORD16 apc; // 0..31 |
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226 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE |
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227 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE |
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228 } |
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229 T_TX_LEVEL; |
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230 |
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231 /************************************/ |
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232 /* Automatic Gain Control */ |
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233 /************************************/ |
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234 /* Define structure for sub-band definition of TX Power ******/ |
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235 typedef struct |
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236 { |
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237 UWORD16 upper_bound; //highest physical arfcn of the sub-band |
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238 WORD16 agc_calib; // AGC for each TXPWR |
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239 }T_RF_AGC_BAND; |
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240 |
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241 /************************************/ |
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242 /* Ramp definitions */ |
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243 /************************************/ |
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244 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) |
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245 typedef struct |
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246 { |
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247 UWORD8 ramp_up [16]; // Ramp-up profile |
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248 UWORD8 ramp_down [16]; // Ramp-down profile |
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249 } |
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250 T_TX_RAMP; |
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251 #endif |
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252 |
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253 |
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254 // RF structure definition |
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255 //======================== |
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256 |
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257 enum RfRevision { |
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258 RF_IGNORE = 0x0000, |
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259 RF_SL2 = 0x1000, |
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260 RF_GAIA_20X = 0x2000, |
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261 RF_GAIA_20A = 0x2001, |
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262 RF_GAIA_20B = 0x2002, |
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263 RF_ATLAS_20B = 0x2020, |
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264 RF_PASCAL_20 = 0x2030 |
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265 }; |
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266 |
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267 // Number of bands supported |
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268 #define GSM_BANDS 2 |
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269 |
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270 #define MULTI_BAND1 0 |
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271 #define MULTI_BAND2 1 |
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272 // RF table sizes |
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273 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands |
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274 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges |
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275 |
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276 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size |
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277 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table |
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278 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size |
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279 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions |
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280 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges |
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281 |
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282 #define AGC_TABLE_SIZE 27 |
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283 |
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284 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table |
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285 |
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286 |
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287 // RX parameters and tables |
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288 //------------------------- |
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289 |
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290 // AGC parameters and tables |
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291 typedef struct |
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292 { |
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293 UWORD16 low_agc_noise_thr; |
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294 UWORD16 high_agc_sat_thr; |
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295 UWORD16 low_agc; |
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296 UWORD16 high_agc; |
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297 UWORD8 il2agc_pwr[121]; |
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298 UWORD8 il2agc_max[121]; |
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299 UWORD8 il2agc_av[121]; |
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300 } |
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301 T_AGC; |
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302 |
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303 // Calibration parameters |
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304 typedef struct |
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305 { |
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306 UWORD16 g_magic; |
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307 UWORD16 lna_att; |
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308 UWORD16 lna_switch_thr_low; |
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309 UWORD16 lna_switch_thr_high; |
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310 } |
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311 T_RX_CAL_PARAMS; |
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312 |
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313 // RX temperature compensation |
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314 typedef struct |
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315 { |
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316 WORD16 temperature; |
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317 WORD16 agc_calib; |
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318 } |
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319 T_RX_TEMP_COMP; |
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320 |
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321 // RF RX structure |
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322 typedef struct |
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323 { |
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324 T_AGC agc; |
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325 } |
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326 T_RF_RX; //common |
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327 |
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328 // RF RX structure |
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329 typedef struct |
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330 { |
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331 T_RX_CAL_PARAMS rx_cal_params; |
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332 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE]; |
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333 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE]; |
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334 } |
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335 T_RF_RX_BAND; |
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336 |
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337 |
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338 // TX parameters and tables |
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339 //------------------------- |
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340 |
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341 // TX temperature compensation |
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342 typedef struct |
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343 { |
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344 WORD16 temperature; |
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345 #if (ORDER2_TX_TEMP_CAL==1) |
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346 WORD16 a; |
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347 WORD16 b; |
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348 WORD16 c; |
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349 #else |
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350 WORD16 apc_calib; //WORD16 c |
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351 #endif |
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352 } |
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353 T_TX_TEMP_CAL; |
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354 |
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355 |
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356 // Ramp up and ramp down delay |
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357 typedef struct |
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358 { |
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359 UWORD16 up; |
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360 UWORD16 down; |
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361 } |
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362 T_RAMP_DELAY; |
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363 |
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364 typedef struct |
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365 { |
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366 UWORD16 arfcn_limit; |
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367 WORD16 chan_cal; |
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368 } |
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369 T_TX_CHAN_CAL; |
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370 |
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371 // RF TX structure |
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372 typedef struct |
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373 { |
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374 T_RAMP_DELAY ramp_delay; |
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375 UWORD8 guard_bits; // number of guard bits needed for ramp up |
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376 UWORD8 prg_tx; |
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377 } |
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378 T_RF_TX; //common |
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379 |
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380 // RF TX structure |
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381 typedef struct |
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382 { |
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383 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE]; |
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384 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS]; |
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385 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE]; |
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386 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE]; |
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387 } |
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388 T_RF_TX_BAND; |
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389 |
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390 // band structure |
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391 typedef struct |
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392 { |
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393 T_RF_RX_BAND rx; |
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394 T_RF_TX_BAND tx; |
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395 UWORD8 swap_iq; |
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396 } |
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397 T_RF_BAND; |
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398 |
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399 // RF structure |
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400 typedef struct |
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401 { |
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402 // common for all bands |
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403 UWORD16 rf_revision; |
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404 UWORD16 radio_band_support; |
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405 T_RF_RX rx; |
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406 T_RF_TX tx; |
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407 T_AFC_PARAMS afc; |
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408 } |
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409 T_RF; |
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410 |
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411 /************************************/ |
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412 /* MADC definitions */ |
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413 /************************************/ |
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414 // Omega: 5 external channels if touch screen not used, 3 otherwise |
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415 enum ADC_INDEX { |
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416 ADC_VBAT, |
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417 ADC_VCHARG, |
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418 ADC_ICHARG, |
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419 ADC_VBACKUP, |
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420 ADC_BATTYP, |
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421 ADC_BATTEMP, |
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422 ADC_ADC3, // name of this ?? |
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423 ADC_RFTEMP, |
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424 ADC_ADC4, |
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425 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums |
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426 }; |
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427 |
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428 typedef struct |
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429 { |
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430 WORD16 converted[ADC_INDEX_END]; // converted |
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431 UWORD16 raw[ADC_INDEX_END]; // raw from ADC |
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432 } |
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433 T_ADC; |
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434 |
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435 /************************************/ |
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436 /* MADC calibration */ |
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437 /************************************/ |
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438 typedef struct |
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439 { |
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440 UWORD16 a[ADC_INDEX_END]; |
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|
441 WORD16 b[ADC_INDEX_END]; |
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442 } |
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443 T_ADCCAL; |
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|
444 |
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|
445 // Conversion table: ADC value -> temperature |
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446 typedef struct |
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|
447 { |
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|
448 UWORD16 adc; // ADC reading is 10 bits |
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449 WORD16 temp; // temp is in approx. range -30..+80 |
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|
450 } |
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|
451 T_TEMP; |
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|
452 |
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453 typedef struct |
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|
454 { |
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455 char *name; |
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456 void *addr; |
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|
457 int size; |
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|
458 } |
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|
459 T_CONFIG_FILE; |
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|
460 |
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|
461 typedef struct |
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|
462 { |
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|
463 char *name; // name of ffs file suffix |
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464 T_RF_BAND *addr; // address to default flash structure |
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465 UWORD16 max_carrier; // max carrier |
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466 UWORD16 max_txpwr; // max tx power |
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|
467 } |
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|
468 T_BAND_CONFIG; |
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|
469 |
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|
470 typedef struct |
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|
471 { |
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|
472 UWORD8 band[GSM_BANDS]; // index to band address |
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473 UWORD8 txpwr_tp; // tx power turning point |
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474 UWORD16 first_arfcn; // first index |
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|
475 } |
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|
476 T_STD_CONFIG; |
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parents:
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|
477 |
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|
478 enum GSMBAND_DEF |
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|
479 { |
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|
480 BAND_NONE, |
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481 BAND_EGSM900, |
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482 BAND_DCS1800, |
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483 BAND_PCS1900, |
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484 BAND_GSM850, |
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|
485 BAND_PCS1900_US, |
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|
486 // put new bands here |
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487 BAND_GSM900 //last entry |
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488 }; |
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|
489 |
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|
490 /************************************/ |
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|
491 /* ABB (Omega) Initialization */ |
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492 /************************************/ |
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|
493 |
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494 #if ((ANALOG == 1) || (ANALOG == 2)) |
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495 #define ABB_TABLE_SIZE 16 |
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496 #elif (ANALOG == 3) |
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497 #define ABB_TABLE_SIZE 22 |
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498 #endif |
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499 |
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500 // Note that this translation is probably not needed at all. But until L1 is |
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501 // (maybe) changed to simply initialize the ABB from a table of words, we |
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502 // use this to make things more easy-readable. |
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503 #if (ANALOG == 1) |
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504 enum ABB_REGISTERS { |
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505 ABB_AFCCTLADD = 0, |
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506 ABB_VBUR, |
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507 ABB_VBDR, |
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508 ABB_BBCTL, |
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509 ABB_APCOFF, |
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510 ABB_BULIOFF, |
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511 ABB_BULQOFF, |
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512 ABB_DAI_ON_OFF, |
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513 ABB_AUXDAC, |
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514 ABB_VBCR, |
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515 ABB_APCDEL |
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516 }; |
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517 #elif (ANALOG == 2) |
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518 enum ABB_REGISTERS { |
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519 ABB_AFCCTLADD = 0, |
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520 ABB_VBUR, |
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521 ABB_VBDR, |
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522 ABB_BBCTL, |
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523 ABB_BULGCAL, |
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524 ABB_APCOFF, |
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525 ABB_BULIOFF, |
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526 ABB_BULQOFF, |
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527 ABB_DAI_ON_OFF, |
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528 ABB_AUXDAC, |
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529 ABB_VBCR, |
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530 ABB_VBCR2, |
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531 ABB_APCDEL, |
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parents:
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532 ABB_APCDEL2 |
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533 }; |
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534 #elif (ANALOG == 3) |
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parents:
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535 enum ABB_REGISTERS { |
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536 ABB_AFCCTLADD = 0, |
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537 ABB_VBUR, |
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538 ABB_VBDR, |
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parents:
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539 ABB_BBCTL, |
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parents:
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540 ABB_BULGCAL, |
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541 ABB_APCOFF, |
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542 ABB_BULIOFF, |
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543 ABB_BULQOFF, |
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544 ABB_DAI_ON_OFF, |
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545 ABB_AUXDAC, |
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parents:
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546 ABB_VBCR, |
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547 ABB_VBCR2, |
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parents:
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|
548 ABB_APCDEL, |
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parents:
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|
549 ABB_APCDEL2, |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
550 ABB_VBPOP, |
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parents:
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551 ABB_VAUDINITD, |
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parents:
diff
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|
552 ABB_VAUDCR, |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
553 ABB_VAUOCR, |
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parents:
diff
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|
554 ABB_VAUSCR, |
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parents:
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|
555 ABB_VAUDPLL |
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Mychaela Falconia <falcon@freecalypso.org>
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|
556 }; |
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|
557 #endif |
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|
558 |