FreeCalypso > hg > freecalypso-citrine
comparison L1/audio_include/l1audio_const.h @ 0:75a11d740a02
initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 09 Jun 2016 00:02:41 +0000 |
parents | |
children | 420ac6391166 |
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1 /************* Revision Controle System Header ************* | |
2 * GSM Layer 1 software | |
3 * L1AUDIO_CONST.H | |
4 * | |
5 * Filename l1audio_const.h | |
6 * Copyright 2003 (C) Texas Instruments | |
7 * | |
8 ************* Revision Controle System Header *************/ | |
9 | |
10 #if (AUDIO_TASK == 1) | |
11 | |
12 // DRC API base address | |
13 #define C_DRC_API_BASE_ADDRESS 0x161E | |
14 | |
15 //---------------------------------------- | |
16 // LAYER 1 Synchronous audio process name. | |
17 //---------------------------------------- | |
18 | |
19 #define NBR_AUDIO_MANAGER 37 // Number of L1S audio managers | |
20 | |
21 #define L1S_KEYBEEP_STATE 0 // l1s_keybeep_manager() | |
22 #define L1S_TONE_STATE 1 // l1s_tone_manager() | |
23 #define L1S_MELODY0_STATE 2 // l1s_melody0_manager() | |
24 #define L1S_MELODY1_STATE 3 // l1s_melody1_manager() | |
25 #define L1S_VM_PLAY_STATE 4 // l1s_vm_play_manager() | |
26 #define L1S_VM_RECORD_STATE 5 // l1s_vm_record_manager() | |
27 #define L1S_TONE_UL_STATE 6 // l1s_tone_ul_manager() | |
28 #define L1S_SR_ENROLL_STATE 7 // l1s_sr_enroll_manager() | |
29 #define L1S_SR_UPDATE_STATE 8 // l1s_sr_update_manager() | |
30 #define L1S_SR_RECO_STATE 9 // l1s_sr_reco_manager() | |
31 #define L1S_SR_PROCESSING_STATE 10 // l1s_sr_processing_manager() | |
32 #define L1S_SR_SPEECH_STATE 11 // l1s_sr_speech_manager() | |
33 #define L1S_AEC_STATE 12 // l1s_aec_manager() | |
34 #define L1S_AUDIO_MODE_STATE 13 // l1s_audio_mode_manager() | |
35 #define L1S_MELODY0_E2_STATE 14 // l1s_melody0_e2_manager() | |
36 #define L1S_MELODY1_E2_STATE 15 // l1s_melody1_e2_manager() | |
37 #define L1S_VM_AMR_PLAY_STATE 16 // l1s_vm_amr_play_manager() | |
38 #define L1S_VM_AMR_RECORD_STATE 17 // l1s_vm_amr_record_manager() | |
39 #define L1S_CPORT_STATE 18 // l1s_cport_manager() | |
40 #define L1S_AUDIO_ONOFF_STATE 19 // l1s_audio_onoff_manager() | |
41 #define L1S_STEREOPATH_DRV_STATE 20 // l1s_stereopath_drv_manager() | |
42 #define L1S_MP3_STATE 21 // l1s_mp3_manager() | |
43 #define L1S_ANR_STATE 22 // l1s_anr_manager() | |
44 #define L1S_IIR_STATE 23 // l1s_iir_manager() | |
45 #define L1S_LIMITER_STATE 24 // l1s_limiter_manager() | |
46 #define L1S_ES_STATE 25 // l1s_es_manager() | |
47 #define L1S_MIDI_STATE 26 // l1s_midi_manager() | |
48 #define L1S_AGC_UL_STATE 27 // l1s_agc_ul_manager() | |
49 #define L1S_AGC_DL_STATE 28 // l1s_agc_dl_manager() | |
50 #define L1S_WCM_STATE 29 // l1s_wcm_manager() | |
51 #define L1S_DRC_STATE 30 // l1s_drc_manager() | |
52 #if (L1_AAC == 1) | |
53 | |
54 //added from e-sample for AAC | |
55 #define L1S_AAC_STATE 31 // l1s_aac_manager() | |
56 #endif | |
57 #if (L1_AUDIO_MCU_ONOFF == 1) | |
58 #define L1S_AUDIO_UL_ONOFF_STATE 32 // l1s_audio_ul_onoff_manager() | |
59 #define L1S_AUDIO_DL_ONOFF_STATE 33 // l1s_audio_dl_onoff_manager() | |
60 #endif | |
61 #define L1S_PCM_DOWNLOAD_STATE 34 // l1s_pcm_download_manager() | |
62 #define L1S_PCM_UPLOAD_STATE 35 // l1s_pcm_upload_manager() | |
63 #define L1S_FIR_STATE 36 // l1s_fir_manager() | |
64 | |
65 | |
66 //---------------------------------------- | |
67 // MCU<->DSP communication bit field. | |
68 //---------------------------------------- | |
69 | |
70 // bit in d_tch_mode for audio features | |
71 #define B_VOICE_MEMO_DTX (TRUE_L << 5) | |
72 #if (DSP >= 34) | |
73 #define B_VM_VOCODER_SELECT (TRUE_L << 6) | |
74 #endif | |
75 | |
76 // bits in d_toneskb_status | |
77 #define B_TONE (TRUE_L << 0) // Indicate if the DSP tone task is running | |
78 #define B_KEYBEEP (TRUE_L << 1) // Indicate if the DSP Keybeep task is running | |
79 #define B_VM_RECORD_ON_GOING (TRUE_L << 2) // Indicate if the DSP recording speech task is running | |
80 #define B_VM_PLAY_ON_GOING (TRUE_L << 3) // Indicate if the DSP playing task is running | |
81 #define B_VM_AMR_RECORD_ON_GOING (TRUE_L << 2) // Indicate if the DSP recording speech amr task is running | |
82 #define B_VM_AMR_PLAY_ON_GOING (TRUE_L << 3) // Indicate if the DSP playing amr task is running | |
83 #define B_SR_ENROLL_TASK (TRUE_L << 4) // Indicate if the DSP enroll task is running | |
84 #define B_SR_UPDATE_TASK (TRUE_L << 5) // Indicate if the DSP update task is running | |
85 #define B_SR_RECO_TASK (TRUE_L << 6) // Indicate if the DSP reco task is running | |
86 #define B_SR_PROCESSING_TASK (TRUE_L << 7) // Indicate if the DSP processing task is running | |
87 #define B_SR_ALIGNMENT_TASK (TRUE_L << 8) // Indicate if the DSP alignment task is running | |
88 #define B_IT_COM_REQ (TRUE_L << 9) // Indicate that the DSP requests an IT com for the next TDMA | |
89 #define B_AUDIO_ON_STATUS (TRUE_L << 14) // Set to 1 if DSP doesn'tpower OFF audio ABB if no DSP audio activity | |
90 | |
91 #if(L1_PCM_EXTRACTION) | |
92 #define B_PCM_UPLOAD_ON_GOING (TRUE_L << 4) | |
93 #define B_PCM_DOWNLOAD_ON_GOING (TRUE_L << 5) | |
94 #endif | |
95 | |
96 // bits in d_toneskb_init | |
97 #define B_VM_RECORD_START (TRUE_L << 2) // Start the DSP voice memo recording task | |
98 #define B_VM_RECORD_STOP (TRUE_L << 3) // Stop the DSP voice memo recording task | |
99 #define B_VM_PLAY_START (TRUE_L << 4) // Start the DSP voice memo playing task | |
100 #define B_VM_PLAY_STOP (TRUE_L << 5) // Stop the DSP voice memo playing task | |
101 #define B_VM_TONE_UL (TRUE_L << 6) // Generate the tone on the UL path | |
102 #define B_VM_AMR_RECORD_START (TRUE_L << 2)// Start the DSP voice memo amr recording task | |
103 #define B_VM_AMR_RECORD_STOP (TRUE_L << 3)// Stop the DSP voice memo amr recording task | |
104 #define B_VM_AMR_PLAY_START (TRUE_L << 4)// Start the DSP voice memo amr playing task | |
105 #define B_VM_AMR_PLAY_STOP (TRUE_L << 5)// Stop the DSP voice memo amr playing task | |
106 #define B_SR_ENROLL (TRUE_L << 7) // Start the DSP speech reco enroll task | |
107 #define B_SR_UPDATE (TRUE_L << 8) // Start the DSP speech reco update task | |
108 #define B_SR_RECO (TRUE_L << 9) // Start the DSP speech reco task | |
109 #define B_SR_PROCESSING (TRUE_L << 10) // Start the DSP speech reco processing task | |
110 #define B_SR_STOP (TRUE_L << 11) // Stop the current DSP speech reco task | |
111 | |
112 #define B_MELO (TRUE_L << 13) // Start the DSP melody module if it's not started | |
113 #define B_AUDIO_ON_START (TRUE_L << 14) // Use to start ABB audio and to not stop it when | |
114 // no audio activity on DSP side | |
115 #define B_AUDIO_OFF_STOP (TRUE_L << 15) // Use to stop ABB audio when no audio activity | |
116 | |
117 #if(L1_PCM_EXTRACTION) | |
118 #define B_PCM_UPLOAD_START (TRUE_L << 7) | |
119 #define B_PCM_UPLOAD_STOP (TRUE_L << 8) | |
120 #define B_PCM_DOWNLOAD_START (TRUE_L << 9) | |
121 #define B_PCM_DOWNLOAD_STOP (TRUE_L << 10) | |
122 #endif | |
123 | |
124 #if (L1_CPORT == 1) | |
125 //---------------------------------------- | |
126 // C_PORT constant. | |
127 //---------------------------------------- | |
128 | |
129 #define CPORT_READ_FLAG_OFFSET 11 // offset in configuration field of the "read register" bit | |
130 #define CPORT_REG_NB_OFFSET 12 // offset in configuration field of the register number | |
131 #define CPORT_READ_MASK 0xF800 // mask to get the read flag and the read reg id in the d_cport_status field | |
132 | |
133 // write register defines | |
134 #define CPORT_W_NONE 0 // do not write anything | |
135 #define CPORT_W_CTRL 1 // write CTRL, set bit 0 of configuration to 1 | |
136 #define CPORT_W_CPCFR1 1 << 1 // write CPCFR1, set bit 1 of configuration to 1 | |
137 #define CPORT_W_CPCFR2 1 << 2 // write CPCFR2, set bit 2 of configuration to 1 | |
138 #define CPORT_W_CPCFR3 1 << 3 // write CPCFR3, set bit 3 of configuration to 1 | |
139 #define CPORT_W_CPCFR4 1 << 4 // write CPCFR4, set bit 4 of configuration to 1 | |
140 #define CPORT_W_CPTCTL 1 << 5 // write CPTCTL, set bit 5 of configuration to 1 | |
141 #define CPORT_W_CPTTADDR 1 << 6 // write CPTTADDR, set bit 6 of configuration to 1 | |
142 #define CPORT_W_CPTDAT 1 << 7 // write CPTDAT, set bit 7 of configuration to 1 | |
143 #define CPORT_W_CPTVS 1 << 8 // write CPTVS, set bit 8 of configuration to 1 | |
144 | |
145 // read register defines | |
146 #define CPORT_R_NONE 0 // do not read anything | |
147 // for each of the following defines, set read flag (bit 11) to 1 and set reg_nb (bits 12..15) | |
148 #define CPORT_R_CTRL (0 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
149 #define CPORT_R_CPCFR1 (1 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
150 #define CPORT_R_CPCFR2 (2 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
151 #define CPORT_R_CPCFR3 (3 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
152 #define CPORT_R_CPCFR4 (4 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
153 #define CPORT_R_CPTCTL (5 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
154 #define CPORT_R_CPTTADDR (6 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
155 #define CPORT_R_CPTDAT (7 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
156 #define CPORT_R_CPTVS (8 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
157 #define CPORT_R_STATUS (9 << CPORT_REG_NB_OFFSET) | (1 << CPORT_READ_FLAG_OFFSET) | |
158 | |
159 #endif | |
160 | |
161 | |
162 #if (MELODY_E1) | |
163 //---------------------------------------- | |
164 // Melody constant. | |
165 //---------------------------------------- | |
166 | |
167 // Word to indicate that the oscillator must be stopped ASAP | |
168 #define SC_END_OSCILLATOR_MASK 0xfffe | |
169 | |
170 // Description of the ml_ocscil_x field (x= 0...SC_NUMBER_OSCILLATOR) | |
171 #define SC_MELO_OSCILLATOR_USED_MASK 0xff00 | |
172 #define SC_MELO_OSCILLATOR_USED_SHIFT SC_NUMBER_OSCILLATOR | |
173 | |
174 // Description of the ml_time_offset field | |
175 #define SC_MELO_TIME_OFFSET_MASK 0x00ff | |
176 #define SC_MELO_TIME_OFFSET_SHIFT 0 | |
177 | |
178 // Description of the ml_load1 bit | |
179 #define SC_MELO_LOAD1_MASK 0x0010 | |
180 #define SC_MELO_LOAD1_SHIFT 4 | |
181 | |
182 // Description of the ml_load2 bit | |
183 #define SC_MELO_LOAD2_MASK 0x0020 | |
184 #define SC_MELO_LOAD2_SHIFT 5 | |
185 | |
186 // Description of the ml_synchro bit | |
187 #define SC_MELO_SYNCHRO_MASK 0x0001 | |
188 #define SC_MELO_SYNCHRO_SHIFT 0 | |
189 | |
190 // Description of the ml_length field | |
191 #define SC_MELO_LENGTH_MASK 0xffc0 | |
192 #define SC_MELO_LENGTH_SHIFT 6 | |
193 #endif // MELODY_E1 | |
194 | |
195 #if (VOICE_MEMO) || (SPEECH_RECO) | |
196 //---------------------------------------- | |
197 // Voice memo constant. | |
198 //---------------------------------------- | |
199 | |
200 // Communication DSP<->MCU via the a_du_x buffer: | |
201 | |
202 // Mask for the bit to indicate: | |
203 // in VM play: if the DSP requests a new block | |
204 // in VM record: if the DSP has a new block | |
205 #define B_BLOCK_READY (TRUE_L<<10) | |
206 | |
207 // Mask for the bit of the a_du_x buffer to indicate if the block is the speech or noise | |
208 #define B_VM_SPEECH (TRUE_L<<15) | |
209 | |
210 // Size of the a_du_x buffer when the sample is a noise: | |
211 #define SC_VM_NOISE_SAMPLE 1 | |
212 | |
213 // Size of the a_du_x buffer when the sample is a speech: | |
214 #define SC_VM_SPEECH_SAMPLE 20 | |
215 #endif // VOICE_MEMO || SPEECH_RECO | |
216 | |
217 #if (L1_PCM_EXTRACTION) | |
218 #define B_PCM_DOWNLOAD_READY (TRUE_L << 0) | |
219 #define B_PCM_UPLOAD_READY (TRUE_L << 0) | |
220 #define SC_PCM_DOWNLOAD_SAMPLE 160 | |
221 #define SC_PCM_UPLOAD_SAMPLE 160 | |
222 #define B_PCM_UPLOAD_ERROR (TRUE_L << 0) | |
223 #define B_PCM_DOWNLOAD_ERROR (TRUE_L << 1) | |
224 #endif /* L1_PCM_EXTRACTION */ | |
225 | |
226 #if (L1_VOICE_MEMO_AMR) | |
227 //---------------------------------------- | |
228 // Voice memo amr constant. | |
229 //---------------------------------------- | |
230 | |
231 #define SC_VM_AMR_HEADER_SIZE 1 | |
232 | |
233 // Communication DSP<->MCU via the a_du_x buffer: | |
234 #define SC_RX_TX_TYPE_MASK (7<<3) | |
235 | |
236 // Communication DSP<->MCU via d_amms_ul_voc and b_amms_channel_type | |
237 #define SC_CHAN_TYPE_MASK 7 | |
238 | |
239 // RX_TYPE or TX_TYPE (See 06.93) | |
240 #define SC_VM_AMR_RXTX_SPEECH_GOOD (0<<3) | |
241 #define SC_VM_AMR_RXTX_SPEECH_DEGRADED (1<<3) | |
242 #define SC_VM_AMR_RXTX_ONSET (2<<3) | |
243 #define SC_VM_AMR_RXTX_SPEECH_BAD (3<<3) | |
244 #define SC_VM_AMR_RXTX_SID_FIRST (4<<3) | |
245 #define SC_VM_AMR_RXTX_SID_UPDATE (5<<3) | |
246 #define SC_VM_AMR_RXTX_SID_BAD (6<<3) | |
247 #define SC_VM_AMR_RXTX_NO_DATA (7<<3) | |
248 | |
249 // sample type for ONSET insertion in NO_SPEECH to SPEECH transition | |
250 #define SC_VM_AMR_SPEECH 0 | |
251 #define SC_VM_AMR_NOISE 1 | |
252 #define SC_VM_AMR_NO_DATA 2 | |
253 #define SC_VM_AMR_ONSET 3 | |
254 | |
255 // Speech channel type | |
256 #define SC_VM_AMR_SPEECH_475 0 | |
257 #define SC_VM_AMR_SPEECH_515 1 | |
258 #define SC_VM_AMR_SPEECH_59 2 | |
259 #define SC_VM_AMR_SPEECH_67 3 | |
260 #define SC_VM_AMR_SPEECH_74 4 | |
261 #define SC_VM_AMR_SPEECH_795 5 | |
262 #define SC_VM_AMR_SPEECH_102 6 | |
263 #define SC_VM_AMR_SPEECH_122 7 | |
264 | |
265 // Size of data bits in the a_du_x buffer when the sample is SPEECH | |
266 // a_du_x buffer contains header + 2 non-used words after header + data_bits => recorded size is DATA_SIZE + 1 | |
267 #define SC_VM_AMR_SPEECH_475_DATA_SIZE 12 | |
268 #define SC_VM_AMR_SPEECH_515_DATA_SIZE 13 | |
269 #define SC_VM_AMR_SPEECH_59_DATA_SIZE 15 | |
270 #define SC_VM_AMR_SPEECH_67_DATA_SIZE 17 | |
271 #define SC_VM_AMR_SPEECH_74_DATA_SIZE 19 | |
272 #define SC_VM_AMR_SPEECH_795_DATA_SIZE 20 | |
273 #define SC_VM_AMR_SPEECH_102_DATA_SIZE 26 | |
274 #define SC_VM_AMR_SPEECH_122_DATA_SIZE 31 | |
275 | |
276 // Size of the a_du_x buffer when the sample is SID_FIRST: | |
277 #define SC_VM_AMR_SID_FIRST_DATA_SIZE 5 | |
278 | |
279 // Size of the a_du_x buffer when the sample is SID_UPDATE: | |
280 #define SC_VM_AMR_SID_UPDATE_DATA_SIZE 5 | |
281 | |
282 // Size of the a_du_x buffer when the sample is SID_BAD: | |
283 #define SC_VM_AMR_SID_BAD_DATA_SIZE 5 | |
284 | |
285 // Size of the a_du_x buffer when the sample is NO_DATA: | |
286 #define SC_VM_AMR_NO_DATA_DATA_SIZE 0 | |
287 | |
288 // Size of the a_du_x buffer when the sample is ONSET: | |
289 #define SC_VM_AMR_ONSET_DATA_SIZE 0 | |
290 | |
291 #endif // L1_VOICE_MEMO_AMR | |
292 | |
293 #if (SPEECH_RECO) | |
294 //---------------------------------------- | |
295 // Speech recognition constant. | |
296 //---------------------------------------- | |
297 | |
298 // d_sr_status bit field | |
299 #define B_BAD_ACQUISITION (TRUE_L << 8) | |
300 #define B_GOOD_ACQUISITION (TRUE_L << 9) | |
301 #define B_BAD_UPDATE (TRUE_L << 10) | |
302 #define B_GOOD_UPDATE (TRUE_L << 11) | |
303 | |
304 // d_sr_status VAD indication | |
305 #define SC_SR_WORD_MASK 0x00FF | |
306 #define SC_SR_WORD_SEARCHING 0 | |
307 #define SC_SR_WORD_BEGINNING 1 | |
308 #define SC_SR_WORD_ON_GOING 2 | |
309 #define SC_SR_WORD_ENDING 3 | |
310 #define SC_SR_WORD_DONE 4 | |
311 | |
312 #endif // SPEECH_RECO | |
313 | |
314 #if (L1_AEC == 1) | |
315 #define B_AEC_ACK (TRUE_L << 0) // Bit set by the MCU to indicate a new AEC settings and | |
316 // clear by the DSP to confirm the new settings. | |
317 #if (L1_NEW_AEC) | |
318 #define B_AEC_VISIBILITY (TRUE_L << 9) // Bit set by the MCU to have internal output values of AEC copied in API | |
319 #define SC_AEC_VISIBILITY_SHIFT (9) | |
320 #endif | |
321 | |
322 #endif | |
323 | |
324 | |
325 #if (W_A_DSP_SR_BGD) | |
326 #define C_BGD_RECOGN 5 // TEMPORARY: DSP Background recognition task code (also used for bitmaps). | |
327 #define C_BGD_ALIGN 6 // TEMPORARY: DSP Background alignement | |
328 // bits in d_gsm_bgd_mgt - background task management | |
329 #define B_DSPBGD_RECO 1 // start of reco in dsp background | |
330 #define B_DSPBGD_UPD 2 // start of alignement update in dsp background | |
331 #endif | |
332 #if (AUDIO_MODE) | |
333 #define B_GSM_ONLY ((TRUE_L << 13) | (TRUE_L << 11)) // GSM normal mode | |
334 #define B_BT_CORDLESS (TRUE_L << 12) // Bluetooth cordless mode | |
335 #define B_BT_HEADSET (TRUE_L << 14) // Bluetooth headset mode | |
336 #endif | |
337 | |
338 #define SC_AUDIO_MCU_API_BEGIN_ADDRESS (0xFFD00000) // Start address of the API memory in MCU side | |
339 #define SC_AUDIO_DSP_API_BEGIN_ADDRESS (0x0800) // Start address o fthe API memory in DSP side | |
340 | |
341 #if (MELODY_E2) | |
342 // Number of oscillator available in the melody E2 | |
343 #define SC_MELODY_E2_NUMBER_OF_OSCILLATOR (16) | |
344 | |
345 // Code of extension for data=time | |
346 #define SC_TIME_CODE_OF_EXTENSION (1) | |
347 | |
348 // Position of the GlobalTimeFactor parameter | |
349 #define SC_MELODY_E2_GLOBALTIMEFACTOR_MASK (0xFF) | |
350 #define SC_MELODY_E2_GLOBALTIMEFACTOR_SHIFT (0) | |
351 | |
352 // Position of the Number of instrument parameter | |
353 #define SC_MELODY_E2_NUMBEROFINSTRUMENT_MASK (0xFF) | |
354 #define SC_MELODY_E2_NUMBEROFINSTRUMENT_SHIFT (0) | |
355 | |
356 // Position of the extension flag | |
357 #define SC_MELODY_E2_EXTENSION_FLAG_MASK (0x80) | |
358 #define SC_MELODY_E2_EXTENSION_FLAG_SHIFT (7) | |
359 | |
360 // Position of the code of extension | |
361 #define SC_MELODY_E2_CODE_OF_EXTENSION_MASK (0x70) | |
362 #define SC_MELODY_E2_CODE_OF_EXTENSION_SHIFT (4) | |
363 | |
364 // Position of data time | |
365 #define SC_MELODY_E2_DATA_TIME_MSB_MASK (0x07) | |
366 #define SC_MELODY_E2_DATA_TIME_MSB_SHIFT (0) | |
367 | |
368 // Position of data time | |
369 #define SC_MELODY_E2_DATA_TIME_LSB_MASK (0xFF00) | |
370 #define SC_MELODY_E2_DATA_TIME_LSB_SHIFT (8) | |
371 | |
372 // Position of the Delta Time | |
373 #define SC_MELODY_E2_DELTA_TIME_MASK (0x7F) | |
374 #define SC_MELODY_E2_DELTA_TIME_SHIFT (0) | |
375 | |
376 // Mask of the semaphore | |
377 #define SC_MELODY_E2_SEMAPHORE_MASK (0x0001) | |
378 | |
379 // Maximum size of the header of the melody E2 | |
380 #define SC_MELODY_E2_MAXIMUM_HEADER_SIZE (3 + SC_AUDIO_MELODY_E2_MAX_NUMBER_OF_INSTRUMENT) | |
381 | |
382 // Maximum number of extension | |
383 #define SC_MELODY_E2_MAXIMUM_NUMBER_OF_EXTENSION (2) | |
384 #endif // MELODY_E2 | |
385 | |
386 // Selection of the melody format | |
387 #define NO_MELODY_SELECTED (0) | |
388 #define MELODY_E0_SELECTED (1) | |
389 #define MELODY_E1_SELECTED (2) | |
390 #define MELODY_E2_SELECTED (3) | |
391 | |
392 #if (L1_STEREOPATH == 1) | |
393 // configuration | |
394 #define AUDIO_SP_SELF_CONF 0 | |
395 #define AUDIO_SP_MIDI_CONF 1 | |
396 #define AUDIO_SP_MP3_CONF 2 | |
397 #define AUDIO_SP_EXTAUDIO_CONF 3 | |
398 | |
399 #if (ANALOG == 3) | |
400 // sampling frequency | |
401 #define AUDIO_SP_FREQ_8 7 | |
402 #define AUDIO_SP_FREQ_11 6 | |
403 #define AUDIO_SP_FREQ_16 5 | |
404 #define AUDIO_SP_FREQ_22 4 | |
405 #define AUDIO_SP_FREQ_32 3 | |
406 #define AUDIO_SP_FREQ_44 2 | |
407 #define AUDIO_SP_FREQ_48 0 | |
408 #endif | |
409 | |
410 #if (ANALOG == 11 || CODE_VERSION == SIMULATION) | |
411 // sampling frequency index for Triton. This would be set in the | |
412 //SRW[0:3] bits of the CTRL5 register. | |
413 #define AUDIO_SP_FREQ_8 0 | |
414 #define AUDIO_SP_FREQ_11 1 | |
415 #define AUDIO_SP_FREQ_12 2 | |
416 #define AUDIO_SP_FREQ_16 3 | |
417 #define AUDIO_SP_FREQ_22 4 | |
418 #define AUDIO_SP_FREQ_24 5 | |
419 #define AUDIO_SP_FREQ_32 6 | |
420 #define AUDIO_SP_FREQ_44 7 | |
421 #define AUDIO_SP_FREQ_48 8 | |
422 #endif | |
423 | |
424 // DMA allocation | |
425 #define AUDIO_SP_DMA_ALLOC_MCU 0 | |
426 #define AUDIO_SP_DMA_ALLOC_DSP 1 | |
427 | |
428 // Data type | |
429 #define AUDIO_SP_DATA_S8 0 | |
430 #define AUDIO_SP_DATA_S16 1 | |
431 #define AUDIO_SP_DATA_S32 2 | |
432 | |
433 // Source port | |
434 #define AUDIO_SP_SOURCE_IMIF 0 | |
435 #define AUDIO_SP_SOURCE_API 2 | |
436 #if (CHIPSET == 15) | |
437 //In Locosto, EMIF is also a source port for the audio | |
438 #define AUDIO_SP_SOURCE_EMIF 4 | |
439 #endif | |
440 | |
441 // output type | |
442 #define AUDIO_SP_MONO_OUTPUT 0 | |
443 #define AUDIO_SP_STEREO_OUTPUT 1 | |
444 | |
445 // feature identifier | |
446 #define AUDIO_SP_MIDI_ID 0 | |
447 #define AUDIO_SP_EXT_AUDIO_ID 1 | |
448 #define AUDIO_SP_MP3_ID 2 | |
449 #define AUDIO_SP_TESTS_ID 3 | |
450 #if (L1_AAC == 1) | |
451 #define AUDIO_SP_AAC_ID 4 //added for AAC | |
452 #endif | |
453 | |
454 // Pattern | |
455 #define AUDIO_SP_SILENCE_PATTERN 0 | |
456 #define AUDIO_SP_SINUS1_PATTERN 1 | |
457 #define AUDIO_SP_SINUS2_PATTERN 2 | |
458 #define AUDIO_SP_SINUS3_PATTERN 3 | |
459 | |
460 #endif | |
461 | |
462 #endif // AUDIO_TASK | |
463 | |
464 #if (DSP == 17) || (DSP == 32) | |
465 #define B_FIR_START (TRUE_L << 0) // Bit set by the MCU to start the FIR task for the DSP code 32 and 17. | |
466 #endif | |
467 | |
468 #define B_FIR_LOOP (TRUE_L << 1) // Bit set by the MCU to close the loop between the audio UL and DL path. | |
469 // This features is used to find the FIR coefficient. | |
470 | |
471 /*************************************/ | |
472 /* ACOUSTIC interface */ | |
473 /*************************************/ | |
474 | |
475 /* Control values */ | |
476 /*----------------*/ | |
477 | |
478 #define B_ANR_ENABLE (TRUE_L << 0) | |
479 #define B_ANR_DISABLE (TRUE_L << 1) | |
480 #define B_ANR_FULL_UPDATE (TRUE_L << 2) | |
481 | |
482 #define B_IIR_ENABLE (TRUE_L << 0) | |
483 #define B_IIR_DISABLE (TRUE_L << 1) | |
484 #define B_IIR_FULL_UPDATE (TRUE_L << 2) | |
485 | |
486 #define B_AGC_ENABLE (TRUE_L << 0) | |
487 #define B_AGC_DISABLE (TRUE_L << 1) | |
488 #define B_AGC_FULL_UPDATE (TRUE_L << 2) | |
489 | |
490 #define B_WCM_ENABLE (TRUE_L << 0) | |
491 #define B_WCM_DISABLE (TRUE_L << 1) | |
492 #define B_WCM_FULL_UPDATE (TRUE_L << 2) | |
493 | |
494 #if (L1_DRC == 1) | |
495 #define DRC_LPF_LENGTH 17 | |
496 #define DRC_BPF_LENGTH 17 | |
497 #endif | |
498 | |
499 #define B_DRC_ENABLE (TRUE_L << 0) | |
500 #define B_DRC_DISABLE (TRUE_L << 1) | |
501 #define B_DRC_FULL_UPDATE (TRUE_L << 2) | |
502 | |
503 #define B_LIM_ENABLE (TRUE_L << 0) | |
504 #define B_LIM_DISABLE (TRUE_L << 1) | |
505 #define B_LIM_FULL_UPDATE (TRUE_L << 2) | |
506 #define B_LIM_UPDATE (TRUE_L << 3) | |
507 | |
508 #define B_ES_ENABLE (TRUE_L << 0) | |
509 #define B_ES_DISABLE (TRUE_L << 1) | |
510 #define B_ES_FULL_UPDATE (TRUE_L << 2) | |
511 | |
512 #if (L1_IIR == 2) | |
513 #define IIR_4X_ORDER_OF_SECTION 2 | |
514 #define IIR_4X_FIR_MAX_LENGTH 40 | |
515 #endif | |
516 | |
517 #if (L1_WCM == 1) | |
518 #define WCM_1X_GAIN_TABLE_LENGTH 16 | |
519 #endif | |
520 | |
521 /* d_aqi_status bits */ | |
522 /*-------------------*/ | |
523 #if (DSP == 38) || (DSP == 39) | |
524 #define B_DRC_DL_STATE (TRUE_L << 3) | |
525 #define B_IIR_DL_STATE (TRUE_L << 4) | |
526 #define B_LIM_STATE (TRUE_L << 5) | |
527 #define B_AGC_DL_STATE (TRUE_L << 6) | |
528 #define B_AEC_STATE (TRUE_L << 11) | |
529 #define B_ANR_UL_STATE (TRUE_L << 12) | |
530 #define B_ES_STATE (TRUE_L << 13) | |
531 #define B_AGC_UL_STATE (TRUE_L << 14) | |
532 #else | |
533 #define B_IIR_STATE (TRUE_L << 4) | |
534 #define B_LIM_STATE (TRUE_L << 5) | |
535 #define B_ANR_STATE (TRUE_L << 12) | |
536 #define B_ES_STATE (TRUE_L << 13) | |
537 #endif | |
538 | |
539 /* d_audio_apps_status bits */ | |
540 /*-------------------*/ | |
541 #if (DSP == 38) || (DSP == 39) | |
542 #define B_WCM_STATE (TRUE_L << 0) | |
543 #endif | |
544 | |
545 /*****************/ | |
546 /* ANR constants */ | |
547 /*****************/ | |
548 #if (L1_ANR == 1) | |
549 #define C_ANR_VAD_THR 0x1333 | |
550 #define C_ANR_GAMMA_SLOW 0x7F1B | |
551 #define C_ANR_GAMMA_FAST 0x75C3 | |
552 #define C_ANR_GAMMA_GAIN_SLOW 28836 | |
553 #define C_ANR_GAMMA_GAIN_FAST 32113 | |
554 #define C_ANR_THR2 0x01E0 | |
555 #define C_ANR_THR4 0x03DE | |
556 #define C_ANR_THR5 0x012C | |
557 #define C_ANR_MEAN_RATIO_THR1 10000 | |
558 #define C_ANR_MEAN_RATIO_THR2 6000 | |
559 #define C_ANR_MEAN_RATIO_THR3 5000 | |
560 #define C_ANR_MEAN_RATIO_THR4 4000 | |
561 #endif | |
562 | |
563 | |
564 #if (L1_ES == 1) | |
565 | |
566 /*******************/ | |
567 /* ES constants */ | |
568 /*******************/ | |
569 | |
570 // ES custom mode | |
571 #define ES_CUSTOM_PARAM 0xFF | |
572 | |
573 // ES mode definition | |
574 #define B_ES_UL (0x1 << 0) // ES UL enable | |
575 #define B_ES_DL (0x1 << 1) // ES DL enable | |
576 #define B_ES_CNG (0x1 << 2) // CNG enable | |
577 #define B_ES_NSF (0x1 << 3) // NSF enable | |
578 #define B_ES_ALS_UL (0x1 << 4) // ALS UL enable | |
579 #define B_ES_ALS_DL (0x1 << 5) // ALS DL enable | |
580 | |
581 // ES parameter values | |
582 #define C_ES_GAIN_DL_OFF 0x0 | |
583 #define C_ES_GAIN_UL_1_OFF 0x0 | |
584 #define C_ES_GAIN_UL_2_OFF 0x0 | |
585 | |
586 #define C_ES_TCL_M23DB 0x005E // ref. -23dB | |
587 #define C_ES_TCL_M6DB 0x0176 // ref. -6dB | |
588 #define C_ES_TCL_M3DB 0x02EA // ref. -6dB | |
589 #define C_ES_TCL_0DB 0x05D1 // ref. 0dB | |
590 #define C_ES_TCL_4DB 0x0E9D // ref. 4dB | |
591 #define C_ES_TCL_6DB 0x1729 // ref. 6dB | |
592 #define C_ES_TCL_10DB 0x3A2F // ref. 10dB | |
593 #define C_ES_TCL_12DB 0x5C36 // ref. 12dB | |
594 #define C_ES_TCL_B3_FE_LS 0x0004 // ref. -10dB | |
595 #define C_ES_TCL_B3_DT_LS 0x0001 // ref. -16dB | |
596 #define C_ES_TCL_B3_FE_NS 0x000F // ref. -10dB | |
597 #define C_ES_TCL_B3_DT_NS 0x0004 // ref. -16dB | |
598 #define C_ES_TCL_B3_NE 0x000F // ref. 0dB | |
599 | |
600 #define C_ES_TCL_FE_0 0x05D1 // ref. 0dB | |
601 #define C_ES_TCL_DT_0 0x05D1 // ref. 0dB | |
602 #define C_ES_TCL_NE_0 0x05D1 // ref. 0dB | |
603 | |
604 #define C_ES_TCL_LOUD 0x00BF // ref. 70dB | |
605 | |
606 #define C_ES_SW_CNT 5 // ref. switching time 100ms | |
607 #define C_ES_DT_CNT 5 // ref. double-talk time 100ms | |
608 | |
609 #define C_ES_HG_CNT_1 8 // ref. hangover time 150ms, A_S(IDLE) = -3dB | |
610 #define C_ES_HG_CNT_1A 8 // ref. hangover time 150ms, A_S(IDLE) = -3dB | |
611 #define C_ES_HG_CNT_2A 10 // ref. hangover time 200ms, A_S(IDLE) = -3dB | |
612 #define C_ES_HG_CNT_2B 13 // ref. hangover time 250ms, A_S(IDLE) = -3dB | |
613 #define C_ES_HG_CNT_2C 13 // ref. hangover time 250ms, A_S(IDLE) = -3dB | |
614 #define C_ES_HG_CNT_2C_IDLE 13 // ref. hangover time 250ms, A_S(IDLE) = -3dB | |
615 #define C_ES_HG_CNT_3 20 // ref. hangover time 400ms | |
616 | |
617 #define C_ES_ATT_LIN_0DB 0x7fff // ref. 0dB | |
618 #define C_ES_ATT_LIN_3DB 0x5A9D // ref. -3dB | |
619 #define C_ES_ATT_LIN_5DB 0x47FA // ref. -5dB | |
620 #define C_ES_ATT_LIN_6DB 0x4026 // ref. -6dB | |
621 #define C_ES_ATT_LIN_8DB 0x32F4 // ref. -8dB | |
622 #define C_ES_ATT_LIN_9DB 0x2D6A // ref. -9dB | |
623 #define C_ES_ATT_LIN_10DB 0x2879 // ref. -10dB | |
624 #define C_ES_ATT_LIN_12DB 0x2026 // ref. -12dB | |
625 #define C_ES_ATT_LIN_15DB 0x16C2 // ref. -15dB | |
626 #define C_ES_ATT_LIN_16DB 0x1449 // ref. -16dB | |
627 #define C_ES_ATT_LIN_19DB 0x0E5D // ref. -19dB | |
628 #define C_ES_ATT_LIN_21DB 0x0B68 // ref. -21dB | |
629 #define C_ES_ATT_LIN_24DB 0x0813 // ref. -24dB | |
630 #define C_ES_ATT_LIN_36DB 0x0207 // ref. -36dB | |
631 #define C_ES_ATT_LIN_48DB 0x0082 // ref. -48dB | |
632 #define C_ES_ATT_LIN_66DB 0x0010 // ref. -56dB | |
633 | |
634 #endif // L1_ES | |
635 #if(L1_EXT_AUDIO_MGT == 1) | |
636 #define AUDIO_EXT_MIDI_BUFFER_SIZE 2640 | |
637 #endif |