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comparison L1/cfile/l1_drive.c @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
parents
children b36540edb046
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-1:000000000000 0:75a11d740a02
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_DRIVE.C
4 *
5 * Filename l1_drive.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1_DRIVE_C
11
12 #include "config.h"
13 #include "l1_confg.h"
14
15 #if (RF_FAM == 61)
16 #include "apc.h"
17 #endif
18
19 #if ((W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)&&(W_A_DSP_PR20037 == 1))
20 #include "../../nucleus/nucleus.h"
21 #endif
22 #include "l1_macro.h"
23 #if (CODE_VERSION == SIMULATION)
24 #include <string.h>
25 #include "l1_types.h"
26 #include "sys_types.h"
27 #include "l1_const.h"
28 #include "l1_time.h"
29 #if TESTMODE
30 #include "l1tm_defty.h"
31 #endif
32 #if (AUDIO_TASK == 1)
33 #include "l1audio_const.h"
34 #include "l1audio_cust.h"
35 #include "l1audio_defty.h"
36 #endif
37 #if (L1_GTT == 1)
38 #include "l1gtt_const.h"
39 #include "l1gtt_defty.h"
40 #endif
41 #if (L1_MP3 == 1)
42 #include "l1mp3_defty.h"
43 #endif
44 #if (L1_MIDI == 1)
45 #include "l1midi_defty.h"
46 #endif
47 //ADDED FOR AAC
48 #if (L1_AAC == 1)
49 #include "l1aac_defty.h"
50 #endif
51 #include "l1_defty.h"
52 #include "l1_varex.h"
53 #include "cust_os.h"
54 #include "l1_msgty.h"
55 #if TESTMODE
56 #include "l1tm_varex.h"
57 #endif
58 #if L2_L3_SIMUL
59 #include "hw_debug.h"
60 #endif
61
62 #if L1_GPRS
63 #include "l1p_cons.h"
64 #include "l1p_msgt.h"
65 #include "l1p_deft.h"
66 #include "l1p_vare.h"
67 #include "l1p_sign.h"
68 #endif
69
70 #include <stdio.h>
71 #include "sim_cfg.h"
72 #include "sim_cons.h"
73 #include "sim_def.h"
74 #include "sim_var.h"
75
76 #include "l1_ctl.h"
77
78 #else
79
80 #include <string.h>
81 #include "l1_types.h"
82 #include "sys_types.h"
83 #include "l1_const.h"
84 #include "l1_time.h"
85 #if TESTMODE
86 #include "l1tm_defty.h"
87 #endif
88 #if (AUDIO_TASK == 1)
89 #include "l1audio_const.h"
90 #include "l1audio_cust.h"
91 #include "l1audio_defty.h"
92 #endif
93 #if (L1_GTT == 1)
94 #include "l1gtt_const.h"
95 #include "l1gtt_defty.h"
96 #endif
97 #if (L1_MP3 == 1)
98 #include "l1mp3_defty.h"
99 #endif
100 #if (L1_MIDI == 1)
101 #include "l1midi_defty.h"
102 #endif
103 //ADDED FOR AAC
104 #if (L1_AAC == 1)
105 #include "l1aac_defty.h"
106 #endif
107 #include "l1_defty.h"
108 #include "l1_varex.h"
109 #include "../../gpf/inc/cust_os.h"
110 #include "l1_msgty.h"
111 #if TESTMODE
112 #include "l1tm_varex.h"
113 #endif
114 #if L2_L3_SIMUL
115 #include "hw_debug.h"
116 #endif
117 #include "tpudrv.h"
118
119 #if L1_GPRS
120 #include "l1p_cons.h"
121 #include "l1p_msgt.h"
122 #include "l1p_deft.h"
123 #include "l1p_vare.h"
124 #include "l1p_sign.h"
125 #endif
126
127 #include "l1_ctl.h"
128
129 #endif
130
131 #if (RF_FAM == 61)
132 #include "tpudrv61.h"
133 #endif
134
135
136
137 /*
138 * Prototypes of external functions used in this file.
139 *
140 * FreeCalypso change: removed all those prototypes which appear
141 * in tpudrv.h, and kept only the additional ones.
142 */
143
144 #if ((REL99 == 1) && (FF_BHO == 1))
145 #if (L1_MADC_ON == 1)
146 void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq,UWORD8 adc_active);
147 #else
148 void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq);
149 #endif
150 #endif//#if ((REL99 == 1) && (FF_BHO == 1))
151
152 void Cust_get_ramp_tab(API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq);
153 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (RF_FAM == 61))
154 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq
155 #if(REL99 && FF_PRF)
156 ,UWORD8 number_uplink_timeslot
157 #endif
158 );
159 #endif
160
161 #if L1_GPRS
162 void l1ps_reset_db_mcu_to_dsp(T_DB_MCU_TO_DSP_GPRS *page_ptr);
163 #endif
164
165 /*-------------------------------------------------------*/
166 /* l1ddsp_load_info() */
167 /*-------------------------------------------------------*/
168 /* Parameters : */
169 /* Return : */
170 /* Functionality : */
171 /*-------------------------------------------------------*/
172 void l1ddsp_load_info(UWORD32 task, API *info_ptr, UWORD8 *data)
173 {
174 if(task == RACH_DSP_TASK)
175 // RACH info. format is only 2 words...
176 {
177 info_ptr[0] = ((API)(data[0])) | ((API)(data[1])<<8);
178 }
179 else
180 // Fill mcu-dsp comm. buffer.
181 {
182 UWORD8 i,j;
183
184 // Fill data block Header...
185 info_ptr[0] = (1 << B_BLUD); // 1st word: Set B_BLU bit.
186 info_ptr[1] = 0; // 2nd word: cleared.
187 info_ptr[2] = 0; // 3rd word: cleared.
188
189 if((info_ptr == l1s_dsp_com.dsp_ndb_ptr->a_du_0) ||
190 (info_ptr == l1s_dsp_com.dsp_ndb_ptr->a_du_1))
191 // DATA traffic buffers: size of buffer is 260 bit -> 17 words but DATA traffic uses
192 // only a max of 240 bit (30 bytes) -> 15 words.
193 {
194 for (i=0, j=(3+0); j<(3+15); j++)
195 {
196 info_ptr[j] = ((API)(data[i])) | ((API)(data[i+1]) << 8);
197 i += 2;
198 }
199 #if (TRACE_TYPE==3)
200 if (l1_stats.type == PLAY_UL)
201 {
202 for (i=0, j=(3+0); j<(3+17); j++)
203 {
204 info_ptr[j] = ((API)(data[i])) |
205 ((API)(data[i]) << 8);
206 i ++;
207 }
208 }
209 #endif
210 }
211 else
212 // Data block for control purpose is 184 bit length: 23 bytes: 12 words (16 bit/word).
213 {
214 // Copy first 22 bytes in the first 11 words after header.
215 for (i=0, j=(3+0); j<(3+11); j++)
216 {
217 info_ptr[j] = ((API)(data[i])) | ((API)(data[i+1]) << 8);
218 i += 2;
219 }
220
221 // Copy last UWORD8 (23rd) in the 12th word after header.
222 info_ptr[14] = data[22];
223 }
224 }
225 }
226
227 /*-------------------------------------------------------*/
228 /* l1ddsp_load_monit_task() */
229 /*-------------------------------------------------------*/
230 /* Parameters : */
231 /* Return : */
232 /* Functionality : */
233 /*-------------------------------------------------------*/
234 void l1ddsp_load_monit_task(API monit_task, API fb_mode)
235 {
236 l1s_dsp_com.dsp_db_w_ptr->d_task_md = monit_task; // Write number of measurements
237
238 if(l1a_l1s_com.mode == CS_MODE)
239 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = fb_mode; // Write FB detection algo. mode.
240 else
241 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = 1;
242 }
243
244
245 /* --------------------------------------------------- */
246
247 /* Locosto Changes....*/
248
249 // Parameters: UWORD16 afcval
250 // Return :Void
251 //Functionality: TPU to accept the afcvalue from the MCU and copy it
252 //to the mem_xtal before triggering of AFC Script in DRP
253
254 #if(RF_FAM == 61)
255 void l1dtpu_load_afc(UWORD16 afc)
256 {
257 l1dmacro_afc(afc, 0);
258 }
259
260 /* --------------------------------------------------- */
261
262 /* Locosto Changes....*/
263
264 /* Parameters: API dco_algo_ctl_sb */
265 /* Functionality: Loads the API d_dco_ctl_algo_sb in the API
266 This should be called after updating the value in the API via cust_Get_dco_algo_ctl(...) */
267
268 /* --------------------------------------------------- */
269
270 void l1ddsp_load_dco_ctl_algo_sb (UWORD16 dco_ctl_algo)
271 {
272 #if (DSP == 38) || (DSP == 39)
273 l1s_dsp_com.dsp_db_common_w_ptr->d_dco_algo_ctrl_sb = (API) dco_ctl_algo;
274 #endif
275 }
276
277 /* --------------------------------------------------- */
278
279 /* Locosto Changes....*/
280
281 /* Parameters: API dco_algo_ctl_nb */
282 /* Functionality: Loads the API d_dco_ctl_algo_nb in the API
283 This should be called after updating the value in the API via cust_Get_dco_algo_ctl(...) */
284
285 /* --------------------------------------------------- */
286
287 void l1ddsp_load_dco_ctl_algo_nb (UWORD16 dco_ctl_algo)
288 {
289 #if (DSP == 38) || (DSP == 39)
290 l1s_dsp_com.dsp_db_common_w_ptr->d_dco_algo_ctrl_nb = (API) dco_ctl_algo;
291 #endif
292
293 }
294 /* --------------------------------------------------- */
295
296 /* Locosto Changes....*/
297
298 /* Parameters: API dco_algo_ctl_pw */
299 /* Functionality: Loads the API d_dco_ctl_algo_pw in the API
300 This should be called after updating the value in the API via cust_Get_dco_algo_ctl(...) */
301
302 /* --------------------------------------------------- */
303
304 void l1ddsp_load_dco_ctl_algo_pw (UWORD16 dco_ctl_algo)
305 {
306 #if (DSP == 38) || (DSP == 39)
307 l1s_dsp_com.dsp_db_common_w_ptr->d_dco_algo_ctrl_pw = (API) dco_ctl_algo;
308 #endif
309 }
310
311 #endif
312
313 /*-------------------------------------------------------*/
314 /* l1ddsp_load_afc() */
315 /*-------------------------------------------------------*/
316 /* Parameters : */
317 /* Return : */
318 /* Functionality : */
319 /*-------------------------------------------------------*/
320 void l1ddsp_load_afc(API afc)
321 {
322 #if (L1_EOTD==1)
323 // NEW !!! For EOTD measurements in IDLE mode only, cut AFC updates....
324 #if (L1_GPRS)
325 if ( (l1a_l1s_com.nsync.eotd_meas_session == FALSE) ||
326 (l1a_l1s_com.mode == DEDIC_MODE)||
327 (l1a_l1s_com.l1s_en_task[PDTCH] == TASK_ENABLED))
328 #else
329 if ( (l1a_l1s_com.nsync.eotd_meas_session == FALSE) ||
330 (l1a_l1s_com.mode == DEDIC_MODE))
331 #endif
332
333 {
334 #endif
335 //######################## For DSP Rom #################################
336 l1s_dsp_com.dsp_db_w_ptr->d_afc = afc; // Write new afc command.
337 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (RF_FAM == 61))
338 // NOTE: In Locosto AFC loading is w.r.t DRP not in ABB
339 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= (1 << B_AFC); // Validate new afc value.
340 #endif
341 #if (L1_EOTD==1)
342 }
343 #endif
344
345 }
346
347 /*-------------------------------------------------------*/
348 /* l1ddsp_load_txpwr() */
349 /*-------------------------------------------------------*/
350 /* Parameters : */
351 /* Return : */
352 /* Functionality : */
353 /*Notes:
354
355 While Programming APC Ramp always Program the APCDEL also
356 Cal+:
357 APCDEL1: LSB Dwn(9:5):Up(4:0)
358 APCDEL2: MSB Dwn(9:5):Up(4:0)
359
360 Locosto:
361 APCDEL1: LSB Dwn(9:5):Up(4:0)
362 APCDEL2: MSB Dwn(9:5):Up(4:0)
363 -----
364 Cal+
365 APCRAM : Dwn(51:11)Up(10:6)Forced(0)
366 Locosto:
367 APCRAM: Dwn(9:5)Up(4:0)
368
369 For AFC, APCDEL1, APCDEL2, APCRAMP the Control word d_ctl_abb is checked
370 i f they are reqd to be updated.
371
372 For AUXAPC (Cal+), the last bit = 1 would mean the DSP would pick it at Tx
373 For APCLEV (Loc), it is picked at every Tx, for dummy burst DSP would make it 0
374 */
375
376 /*-------------------------------------------------------*/
377 void l1ddsp_load_txpwr(UWORD8 txpwr, UWORD16 radio_freq)
378 {
379 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (RF_FAM == 61))
380 UWORD16 pwr_data;
381 #endif
382
383 //config
384 if (l1_config.tx_pwr_code ==0)
385 {
386 // Fixed TXPWR.
387 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = l1_config.params.fixed_txpwr; // GSM management disabled: Fixed TXPWR used.
388
389
390 #if(RF_FAM == 61)
391 //Locosto has new API for Ramp
392 #if (DSP == 38) || (DSP == 39)
393 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp, txpwr, txpwr, radio_freq);
394 #endif
395 #else
396 #if (CODE_VERSION != SIMULATION)
397 /*** Reference to real ramp array (GSM: 15 power levels, 5-19, DCS: 16 power levels, 0-15) ***/
398 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
399 #endif
400 #endif
401
402 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
403 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
404 #endif
405
406 #if(RF_FAM == 61)
407 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
408 #endif
409
410 }
411 else
412 {
413 static UWORD8 last_used_freq_band = 0;
414 UWORD8 freq_band;
415
416 #if (L1_FF_MULTIBAND == 0)
417 // Check whether band has changed
418 // This will be used to reload ramps
419 if ((l1_config.std.id == DUAL) ||
420 (l1_config.std.id == DUALEXT) ||
421 (l1_config.std.id == DUAL_US))
422 {
423 if (radio_freq < l1_config.std.first_radio_freq_band2)
424 freq_band = BAND1;
425 else
426 freq_band = BAND2;
427 }
428 else
429 freq_band = BAND1;
430 #else
431
432 freq_band = l1_multiband_radio_freq_convert_into_effective_band_id(radio_freq);
433
434 #endif
435
436 // Note: txpwr = NO_TXPWR is reserved for forcing the transmitter off
437 // ----- (to suppress SACCH during handover, for example)
438
439 /*** Check to see if the TXPWR is to be suppressed (txpwr = NO_TXPWR) ***/
440
441 if(txpwr == NO_TXPWR)
442 {
443 /*** No transmit ***/
444 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
445 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = 0x12; // AUXAPC initialization addr 9 pg 0 Omega
446 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
447 #endif
448
449 #if(RF_FAM == 61 ) //Locosto without Syren Format
450 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = (API) 0; // APCLEV
451 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
452 #endif
453
454 l1s.last_used_txpwr = NO_TXPWR;
455 return;
456 }
457 else
458 {
459 /*** Get power data according to clipped TXPWR ***/
460 pwr_data = Cust_get_pwr_data(txpwr, radio_freq
461 #if(REL99 && FF_PRF)
462 ,1
463 #endif
464 );
465
466 /*** Load power control level adding the APC address register ***/
467 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
468 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = ((pwr_data << 6) | 0x12);
469 // AUXAPC initialization addr 9 pg 0 Omega
470 #endif
471
472 #if(RF_FAM == 61)
473 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = (API)(pwr_data);
474 #endif
475 }
476
477 #if TESTMODE
478 #if(RF_FAM == 61)
479 // Currently for RF_FAM=61 Enabling APC-Ramp, APCDEL1 and APCDEL2 writing always i.e. in every TDMA frame
480 // TODO: Check whether this is okay
481 if ((l1_config.TestMode) && (l1_config.tmode.rf_params.down_up & TMODE_UPLINK))
482 #else
483 if ((l1_config.TestMode) && (l1_config.tmode.rf_params.down_up & TMODE_UPLINK) &&
484 ((l1s.last_used_txpwr != txpwr) || (l1_config.tmode.rf_params.reload_ramps_flag)))
485 #endif
486 {
487 #if(RF_FAM == 61)
488 #if (DSP == 38) || (DSP == 39)
489 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp, txpwr, txpwr, radio_freq);
490 #endif
491 #else
492 #if (CODE_VERSION != SIMULATION)
493 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
494 #endif
495 #endif
496
497 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
498 // Setting bit 3 of this register causes DSP to write to APCDEL1 register in Omega. However,
499 // we are controlling this register from MCU through the SPI. Therefore, set it to 0.
500 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (0 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
501 #endif
502
503 #if (RF_FAM == 61)
504 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
505 #endif
506
507 l1s.last_used_txpwr = txpwr;
508 l1_config.tmode.rf_params.reload_ramps_flag = 0;
509 }
510 else
511 #endif
512
513 if ((l1s.last_used_txpwr != txpwr) || (last_used_freq_band != freq_band))
514 {
515 /*** Power level or band has changed, so update the ramp, and trigger the data send to ABB ***/
516
517 l1s.last_used_txpwr = txpwr;
518 last_used_freq_band = freq_band;
519
520 /*** Reference to real ramp array (GSM: 15 power levels, 5-19, DCS: 16 power levels, 0-15) ***/
521 #if(RF_FAM == 61)
522 #if (DSP == 38) || (DSP == 39)
523 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp, txpwr, txpwr, radio_freq);
524 #endif
525 #else
526 #if (CODE_VERSION != SIMULATION)
527 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
528 #endif
529 #endif
530
531 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) ||(RF_FAM == 61))
532 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
533 #endif
534 }
535 }
536 }
537
538 #if (FF_L1_FAST_DECODING == 1)
539 /*-------------------------------------------------------*/
540 /* l1ddsp_load_fp_task() */
541 /*-------------------------------------------------------*/
542 /* Parameters : */
543 /* Return : */
544 /* Functionality : */
545 /*-------------------------------------------------------*/
546 void l1ddsp_load_fast_dec_task(API task, UWORD8 burst_id)
547 {
548 if (l1s_check_fast_decoding_authorized(task))
549 {
550 //l1s_dsp_com.dsp_db_w_ptr->d_fast_paging_ctrl = 0x0001
551 l1s_dsp_com.dsp_db_common_w_ptr->d_fast_paging_ctrl = 0x00001;
552 if(burst_id == BURST_1)
553 {
554 l1s_dsp_com.dsp_db_common_w_ptr->d_fast_paging_ctrl |= 0x8000;
555 }
556 }
557 }
558 #endif /* FF_L1_FAST_DECODING */
559
560 /*-------------------------------------------------------*/
561 /* l1ddsp_load_rx_task() */
562 /*-------------------------------------------------------*/
563 /* Parameters : */
564 /* Return : */
565 /* Functionality : */
566 /*-------------------------------------------------------*/
567 void l1ddsp_load_rx_task(API rx_task, UWORD8 burst_id, UWORD8 tsq)
568 {
569 l1s_dsp_com.dsp_db_w_ptr->d_task_d = rx_task; // Write RX task Identifier.
570 l1s_dsp_com.dsp_db_w_ptr->d_burst_d = burst_id; // Write RX burst Identifier.
571 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsq << B_TSQ; // Write end of task DSP state.
572 }
573
574 /*-------------------------------------------------------*/
575 /* l1ddsp_load_tx_task() */
576 /*-------------------------------------------------------*/
577 /* Parameters : */
578 /* Return : */
579 /* Functionality : */
580 /*-------------------------------------------------------*/
581 void l1ddsp_load_tx_task(API tx_task, UWORD8 burst_id, UWORD8 tsq)
582 {
583 l1s_dsp_com.dsp_db_w_ptr->d_task_u = tx_task; // write TX task Identifier.
584 l1s_dsp_com.dsp_db_w_ptr->d_burst_u = burst_id; // write TX burst Identifier.
585 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsq << B_TSQ; // Write end of task DSP state.
586 }
587
588 /*-------------------------------------------------------*/
589 /* l1ddsp_load_ra_task() */
590 /*-------------------------------------------------------*/
591 /* Parameters : */
592 /* Return : */
593 /* Functionality : */
594 /*-------------------------------------------------------*/
595 void l1ddsp_load_ra_task(API ra_task)
596 {
597 l1s_dsp_com.dsp_db_w_ptr->d_task_ra = ra_task; // write RA task Identifier.
598 }
599
600 /*-------------------------------------------------------*/
601 /* l1ddsp_load_tch_mode() */
602 /*-------------------------------------------------------*/
603 /* Parameters : */
604 /* Return : */
605 /* Functionality : */
606 /*-------------------------------------------------------*/
607 void l1ddsp_load_tch_mode(UWORD8 dai_mode, BOOL dtx_allowed)
608 {
609 // TCH mode register.
610 // bit[0] -> b_eotd.
611 // bit[1] -> b_audio_async only for WCP
612 // bit [2] -> b_dtx.
613 // bit[3] -> play_ul when set to 1
614 // bit[4] -> play_dl when set to 1
615 // bit[5] -> DTX selection for voice memo
616 // bit[6] -> Reserved for ciphering debug
617 // bit[7..10] -> Reserved for ramp up control
618 // bit[11] -> Reserved for analog device selection
619
620 #if (DSP == 32)
621 UWORD16 mask = 0xfffb;
622 #else // NO OP_WCP
623 UWORD16 mask = 0xfff8;
624 #endif
625
626 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = (l1s_dsp_com.dsp_ndb_ptr->d_tch_mode & mask)
627 | (dtx_allowed<<2);
628 #if (L1_EOTD == 1)
629 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
630 #endif
631 }
632
633 #if (AMR == 1)
634 /*-------------------------------------------------------*/
635 /* l1ddsp_load_tch_param() */
636 /*-------------------------------------------------------*/
637 /* Parameters : */
638 /* Return : */
639 /* Functionality : */
640 /*-------------------------------------------------------*/
641 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
642 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
643 UWORD8 chan_type, UWORD8 subchannel,
644 UWORD8 tch_loop, UWORD8 sync_tch,
645 UWORD8 sync_amr,
646 UWORD8 reset_sacch,
647 #if !FF_L1_IT_DSP_DTX
648 UWORD8 vocoder_on)
649 #else
650 UWORD8 vocoder_on,
651 BOOL dtx_dsp_interrupt)
652 #endif
653 #else
654 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
655 UWORD8 chan_type, UWORD8 subchannel,
656 UWORD8 tch_loop, UWORD8 sync_tch,
657 #if !FF_L1_IT_DSP_DTX
658 UWORD8 sync_amr)
659 #else
660 UWORD8 sync_amr, BOOL dtx_dsp_interrupt)
661 #endif
662 #endif
663 {
664 UWORD32 count_0;
665 UWORD32 count_1;
666 UWORD32 d_ctrl_tch;
667 UWORD32 d_fn;
668
669 // d_ctrl_tch
670 // ----------
671 // bit [0..3] -> b_chan_mode
672 // bit [4..7] -> b_chan_type
673 // bit [8] -> b_sync_tch_ul
674 // bit [9] -> b_sync_amr
675 // bit [10] -> b_stop_tch_ul
676 // bit [11] -> b_stop_tch_dl
677 // bit [12..14] -> b_tch_loop
678 // bit [15] -> b_subchannel
679 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
680 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
681 (sync_tch<<B_SYNC_TCH_UL) | (sync_amr<<B_SYNC_AMR) |
682 (tch_loop<<B_TCH_LOOP) | (reset_sacch<<B_RESET_SACCH) | (vocoder_on<<B_VOCODER_ON);
683 #else
684 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
685 (sync_tch<<B_SYNC_TCH_UL) | (sync_amr<<B_SYNC_AMR) |
686 (tch_loop<<B_TCH_LOOP);
687 #endif
688
689 // d_fn
690 // ----
691 // bit [0..7] -> b_fn_report
692 // bit [8..15] -> b_fn_sid
693 d_fn = (next_time->fn_in_report) | ((next_time->fn%104)<<8);
694
695 // a_a5fn
696 // ------
697 // count_0 (a_a5fn[0]), bit [0..4] -> T2.
698 // count_0 (a_a5fn[1]), bit [5..10] -> T3.
699 // count_1 (a_a5fn[0]), bit [0..10] -> T1.
700 count_0 = ((UWORD16)next_time->t3 << 5) | (next_time->t2);
701 count_1 = (next_time->t1);
702
703 l1s_dsp_com.dsp_db_w_ptr->d_fn = d_fn; // write both Fn_sid, Fn_report.
704 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[0] = count_0; // cyphering FN part 1.
705 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[1] = count_1; // cyphering FN part 2.
706 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = d_ctrl_tch; // Channel config.
707 #if FF_L1_IT_DSP_DTX
708 // ### TBD: report this block below in the other instance of this function
709 // DTX interrupt request is latched by DSP in TDMA3 (TCH-AFS, TCH-AHS0) or TDMA0 (TCH-AHS1)
710 if ((chan_mode == TCH_AFS_MODE) || (chan_mode == TCH_AHS_MODE))
711 {
712 if (((next_time->fn_mod13_mod4 == 3) &&
713 ((chan_mode == TCH_AFS_MODE) || ((subchannel == 0)))) ||
714 ((next_time->fn_mod13_mod4 == 0) &&
715 ((chan_mode == TCH_AHS_MODE) && (subchannel == 1)))
716 )
717 {
718 if (dtx_dsp_interrupt)
719 l1s_dsp_com.dsp_ndb_ptr->d_fast_dtx_enable=1;
720 else
721 l1s_dsp_com.dsp_ndb_ptr->d_fast_dtx_enable=0;
722
723 }
724 }
725 // Fast DTX not supported
726 else
727 {
728 // No interrupt genaration
729 l1s_dsp_com.dsp_ndb_ptr->d_fast_dtx_enable=0;
730 }
731 #endif
732 }
733 #else
734 /*-------------------------------------------------------*/
735 /* l1ddsp_load_tch_param() */
736 /*-------------------------------------------------------*/
737 /* Parameters : */
738 /* Return : */
739 /* Functionality : */
740 /*-------------------------------------------------------*/
741 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
742 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
743 UWORD8 chan_type, UWORD8 subchannel,
744 UWORD8 tch_loop, UWORD8 sync_tch,
745 #if !FF_L1_IT_DSP_DTX
746 UWORD8 reset_sacch, UWORD8 vocoder_on)
747 #else
748 UWORD8 reset_sacch, UWORD8 vocoder_on,
749 BOOL dtx_dsp_interrupt)
750 #endif
751 #else
752 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
753 UWORD8 chan_type, UWORD8 subchannel,
754 #if !FF_L1_IT_DSP_DTX
755 UWORD8 tch_loop, UWORD8 sync_tch)
756 #else
757 UWORD8 tch_loop, UWORD8 sync_tch,
758 BOOL dtx_dsp_interrupt)
759 #endif
760 #endif
761 {
762 UWORD32 count_0;
763 UWORD32 count_1;
764 UWORD32 d_ctrl_tch;
765 UWORD32 d_fn;
766
767 // d_ctrl_tch
768 // ----------
769 // bit [0..3] -> b_chan_mode
770 // bit [4..7] -> b_chan_type
771 // bit [8] -> b_sync_tch_ul
772 // bit [9] -> b_sync_tch_dl
773 // bit [10] -> b_stop_tch_ul
774 // bit [11] -> b_stop_tch_dl
775 // bit [12..14] -> b_tch_loop
776 // bit [15] -> b_subchannel
777 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
778 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
779 (sync_tch<<B_SYNC_TCH_UL) | (sync_tch<<B_SYNC_TCH_DL) |
780 (tch_loop<<B_TCH_LOOP) | (reset_sacch<<B_RESET_SACCH) | (vocoder_on<<B_VOCODER_ON);
781 #else
782 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
783 (sync_tch<<B_SYNC_TCH_UL) | (sync_tch<<B_SYNC_TCH_DL) |
784 (tch_loop<<B_TCH_LOOP);
785 #endif
786
787 // d_fn
788 // ----
789 // bit [0..7] -> b_fn_report
790 // bit [8..15] -> b_fn_sid
791 d_fn = (next_time->fn_in_report) | ((next_time->fn%104)<<8);
792
793 // a_a5fn
794 // ------
795 // count_0 (a_a5fn[0]), bit [0..4] -> T2.
796 // count_0 (a_a5fn[1]), bit [5..10] -> T3.
797 // count_1 (a_a5fn[0]), bit [0..10] -> T1.
798 count_0 = ((UWORD16)next_time->t3 << 5) | (next_time->t2);
799 count_1 = (next_time->t1);
800
801 l1s_dsp_com.dsp_db_w_ptr->d_fn = d_fn; // write both Fn_sid, Fn_report.
802 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[0] = count_0; // cyphering FN part 1.
803 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[1] = count_1; // cyphering FN part 2.
804 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = d_ctrl_tch; // Channel config.
805 }
806 #endif
807
808 #if (L1_VOCODER_IF_CHANGE == 0)
809 // TODO: to be moved in API file (see BUG3093)
810 BOOL enable_tch_vocoder(BOOL vocoder)
811 {
812 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
813 // To enable the vocoder, we set the trigger => then handled in l1s_dedicated_mode_manager
814 #if (W_A_DSP_PR20037 == 1)
815 if ((vocoder==TRUE) && (l1a_l1s_com.dedic_set.start_vocoder == TCH_VOCODER_DISABLED))
816 {
817 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ;
818
819 #if ( W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)
820 NU_Sleep(DSP_VOCODER_ON_TRANSITION); // DSP transition
821 #endif
822 }
823 // When vocoder_on = FALSE, vocoder module is not executed
824 else if ((vocoder==FALSE) && (l1a_l1s_com.dedic_set.start_vocoder == TCH_VOCODER_ENABLED))
825 {
826 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_DISABLE_REQ;
827 }
828 #else // W_A_DSP_PR20037 == 0
829 if (vocoder)
830 {
831 l1a_l1s_com.dedic_set.start_vocoder = TRUE;
832 }
833 // When vocoder_on = FALSE, vocoder module is not executed
834 else
835 {
836 l1a_l1s_com.dedic_set.vocoder_on = FALSE;
837 }
838 #endif // W_A_DSP_PR20037
839
840 return TRUE;
841 #else
842 return FALSE;
843 #endif
844 }
845 #endif // L1_VOCODER_IF_CHANGE
846 BOOL l1_select_mcsi_port(UWORD8 port)
847 {
848 #if ( (CHIPSET == 12) && (RF_FAM != 61) )
849 l1s_dsp_com.dsp_ndb_ptr->d_mcsi_select = (API)port;
850 return TRUE;
851 #else
852 return FALSE;
853 #endif
854 }
855
856 // TODO: to be moved in API file
857
858 /*-------------------------------------------------------*/
859 /* l1ddsp_load_ciph_param() */
860 /*-------------------------------------------------------*/
861 /* Parameters : */
862 /* Return : */
863 /* Functionality : */
864 /*-------------------------------------------------------*/
865 void l1ddsp_load_ciph_param(UWORD8 a5mode,
866 T_ENCRYPTION_KEY *ciph_key)
867 {
868 // Store ciphering mode (0 for no ciphering) in MCU-DSP com.
869 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = a5mode; // A5 algorithm (0 for none).
870 // Store ciphering key.
871
872 #if (L1_A5_3 == 1)
873
874 if(a5mode == 3)
875 {
876 #if(OP_L1_STANDALONE != 1)
877 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
878 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
879 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
880 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
881 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[4] = (ciph_key->A[8]) | (ciph_key->A[9] << 8);
882 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[5] = (ciph_key->A[10]) | (ciph_key->A[11] << 8);
883 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[6] = (ciph_key->A[12]) | (ciph_key->A[13] << 8);
884 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[7] = (ciph_key->A[14]) | (ciph_key->A[15] << 8);
885 #else // (OP_L1_STANDALONE == 1)
886 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
887 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
888 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
889 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
890 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[4] = (ciph_key->A[8]) | (ciph_key->A[1] << 8);
891 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[5] = (ciph_key->A[10]) | (ciph_key->A[3] << 8);
892 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[6] = (ciph_key->A[12]) | (ciph_key->A[5] << 8);
893 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[7] = (ciph_key->A[14]) | (ciph_key->A[7] << 8);
894 #endif
895 }
896 else // a5mode == 1 or 2
897 {
898 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
899 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
900 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
901 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
902 }
903
904 #else
905
906 l1s_dsp_com.dsp_ndb_ptr->a_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
907 l1s_dsp_com.dsp_ndb_ptr->a_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
908 l1s_dsp_com.dsp_ndb_ptr->a_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
909 l1s_dsp_com.dsp_ndb_ptr->a_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
910
911 #endif
912 }
913
914 /*-------------------------------------------------------*/
915 /* l1ddsp_stop_tch() */
916 /*-------------------------------------------------------*/
917 /* Parameters : */
918 /* Return : */
919 /* Functionality : */
920 /*-------------------------------------------------------*/
921 void l1ddsp_stop_tch(void)
922 {
923 // Tch channel description.
924 // bit [10] -> b_stop_tch_ul, stop TCH/UL.
925 // bit [11] -> b_stop_tch_dl, stop TCH/DL.
926
927 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch |= 3 << B_STOP_TCH_UL;
928 }
929
930 /*-------------------------------------------------------*/
931 /* l1ddsp_meas_read() */
932 /*-------------------------------------------------------*/
933 /* Parameters : */
934 /* Return : */
935 /* Functionality : */
936 /*-------------------------------------------------------*/
937 void l1ddsp_meas_read(UWORD8 nbmeas, UWORD16 *pm)
938 {
939 UWORD8 i;
940
941 for (i= 0; i < nbmeas; i++)
942 {
943 pm[i] = ((l1s_dsp_com.dsp_db_r_ptr->a_pm[i] & 0xffff));
944 }
945
946 #if TESTMODE
947 if(l1_config.TestMode)
948 l1tm.tmode_stats.pm_recent = l1s_dsp_com.dsp_db_r_ptr->a_pm[0] & 0xffff;
949 #endif
950 }
951
952 #if (AMR == 1)
953 /*-------------------------------------------------------*/
954 /* l1ddsp_load_amr_param() */
955 /*-------------------------------------------------------*/
956 /* Parameters : AMR configuration */
957 /* Return : none */
958 /* Functionality : Download the AMR configuration to the */
959 /* DSP via API */
960 /*-------------------------------------------------------*/
961 void l1ddsp_load_amr_param(T_AMR_CONFIGURATION amr_param, UWORD8 cmip)
962 {
963 // Clear the AMR API buffer
964 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = (API)0;
965 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = (API)0;
966 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = (API)0;
967 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = (API)0;
968
969 // Set the AMR parameters
970 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[NSCB_INDEX] |= (API)((amr_param.noise_suppression_bit & NSCB_MASK ) << NSCB_SHIFT);
971 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMUL_INDEX] |= (API)((amr_param.initial_codec_mode & ICM_MASK ) << ICMUL_SHIFT);
972 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMDL_INDEX] |= (API)((amr_param.initial_codec_mode & ICM_MASK ) << ICMDL_SHIFT);
973 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMIUL_INDEX] |= (API)((amr_param.initial_codec_mode_indicator & ICMI_MASK ) << ICMIUL_SHIFT);
974 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMIDL_INDEX] |= (API)((amr_param.initial_codec_mode_indicator & ICMI_MASK ) << ICMIDL_SHIFT);
975 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ACSUL_INDEX] |= (API)((amr_param.active_codec_set & ACS_MASK ) << ACSUL_SHIFT);
976 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ACSDL_INDEX] |= (API)((amr_param.active_codec_set & ACS_MASK ) << ACSDL_SHIFT);
977 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[THR1_INDEX] |= (API)((amr_param.threshold[0] & THR_MASK ) << THR1_SHIFT);
978 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[THR2_INDEX] |= (API)((amr_param.threshold[1] & THR_MASK ) << THR2_SHIFT);
979 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[THR3_INDEX] |= (API)((amr_param.threshold[2] & THR_MASK ) << THR3_SHIFT);
980 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[HYST1_INDEX] |= (API)((amr_param.hysteresis[0] & HYST_MASK ) << HYST1_SHIFT);
981 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[HYST2_INDEX] |= (API)((amr_param.hysteresis[1] & HYST_MASK ) << HYST2_SHIFT);
982 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[HYST3_INDEX] |= (API)((amr_param.hysteresis[2] & HYST_MASK ) << HYST3_SHIFT);
983 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[CMIP_INDEX] |= (API)((cmip & CMIP_MASK ) << CMIP_SHIFT);
984 }
985 #endif
986
987 #if (L1_SAIC != 0)
988 /*-------------------------------------------------------*/
989 /* l1ddsp_load_swh_flag() */
990 /*-------------------------------------------------------*/
991 /* Parameters : SWH (Spatial Whitening) Flag */
992 /* Return : none */
993 /* Functionality : To write the d_swh_ApplyWhitening flag*/
994 /*-------------------------------------------------------*/
995 void l1ddsp_load_swh_flag (UWORD16 SWH_flag, UWORD16 SAIC_flag)
996 {
997
998 if(SAIC_flag)
999 {
1000 l1s_dsp_com.dsp_db_common_w_ptr->d_swh_ctrl_db = SAIC_ENABLE_DB;
1001 if(SWH_flag)
1002 {
1003 l1s_dsp_com.dsp_db_common_w_ptr->d_swh_ctrl_db |= (0x01<< B_SWH_DB);
1004 }
1005 }
1006 else
1007 {
1008 l1s_dsp_com.dsp_db_common_w_ptr->d_swh_ctrl_db = 0;
1009 }
1010 }
1011 #endif
1012
1013 /*-------------------------------------------------------*/
1014 /* l1ddsp_end_scenario() */
1015 /*-------------------------------------------------------*/
1016 /* Parameters : */
1017 /* Return : */
1018 /* Functionality : */
1019 /*-------------------------------------------------------*/
1020 void l1ddsp_end_scenario(UWORD8 type)
1021 {
1022 #if (CODE_VERSION == SIMULATION)
1023 #if (AUDIO_SIMULATION)
1024 switch(type)
1025 {
1026 case GSM_CTL:
1027 case GSM_MISC_CTL:
1028 // a DSP control for a GSM task or
1029 // a DSP control for a GSM and a MISC tasks
1030 //-----------------------------
1031 {
1032 // set DSP_ENB and DSP_PAG for communication interrupt
1033 l1s_tpu_com.reg_cmd->dsp_pag_bit = l1s_dsp_com.dsp_w_page;
1034 l1s_tpu_com.reg_cmd->dsp_enb_bit = ON;
1035
1036 // change DSP page pointer for next controle
1037 l1s_dsp_com.dsp_w_page ^= 1;
1038 }
1039 break;
1040
1041 case MISC_CTL:
1042 // a DSP control for a MISC task
1043 //------------------------------
1044 {
1045 // set only MISC task and reset MISC page
1046 // (don't change GSM PAGE).
1047 // set DSP communication Interrupt.
1048 // set DSP_ENB and the same DSP_PAG for communication interrupt
1049 l1s_tpu_com.reg_cmd->dsp_pag_bit = l1s_dsp_com.dsp_w_page^1;
1050 l1s_tpu_com.reg_cmd->dsp_enb_bit = ON;
1051 }
1052 break;
1053 }
1054 #else // NO AUDIO_SIMULATION
1055 // set DSP_ENB and DSP_PAG for communication interrupt
1056 l1s_tpu_com.reg_cmd->dsp_pag_bit = l1s_dsp_com.dsp_w_page;
1057 l1s_tpu_com.reg_cmd->dsp_enb_bit = ON;
1058
1059 // change DSP page pointer for next control
1060 l1s_dsp_com.dsp_w_page ^= 1;
1061 #endif // AUDIO_SIMULATION
1062
1063 #else // NOT_SIMULATION
1064 UWORD32 dsp_task=0 ;//omaps00090550;
1065 switch(type)
1066 {
1067 case GSM_CTL:
1068 // a DSP control for a GSM task
1069 //-----------------------------
1070 {
1071 // set only GSM task and GSM page
1072 dsp_task = B_GSM_TASK | l1s_dsp_com.dsp_w_page;
1073 // change DSP page pointer for next controle
1074 l1s_dsp_com.dsp_w_page ^= 1;
1075 }
1076 break;
1077
1078 case MISC_CTL:
1079 // a DSP control for a MISC task
1080 //------------------------------
1081 {
1082 UWORD32 previous_page = l1s_dsp_com.dsp_w_page ^ 1;
1083
1084 // set only MISC task and reset MISC page
1085 // (don't change GSM PAGE).
1086 // set DSP communication Interrupt.
1087 dsp_task = B_MISC_TASK | previous_page;
1088
1089 // Rem: DSP makes the DB header feedback even in case
1090 // of MISC task (like TONES). This created some
1091 // side effect which are "work-around" passing
1092 // the correct DB page to the DSP.
1093 }
1094 break;
1095
1096 case GSM_MISC_CTL:
1097 // a DSP control for a GSM and a MISC tasks
1098 //-----------------------------------------
1099 {
1100 // set GSM task, MISC task and GSM page bit.....
1101 dsp_task = B_GSM_TASK | B_MISC_TASK | l1s_dsp_com.dsp_w_page;
1102 // change DSP page pointer for next controle
1103 l1s_dsp_com.dsp_w_page ^= 1;
1104 }
1105 break;
1106 }
1107
1108 // write dsp tasks.....
1109 #if (DSP >= 33)
1110 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = (API) dsp_task;
1111 #else
1112 l1s_dsp_com.dsp_param_ptr->d_dsp_page = (API) dsp_task;
1113 #endif
1114
1115 // Enable frame IT on next TDMA
1116 l1dmacro_set_frame_it();
1117
1118 #if (DSP >= 38)
1119 // DSP CPU load measurement - write logic (provide TDMA frame number to DSP)
1120 (*((volatile UWORD16 *)(DSP_CPU_LOAD_MCU_W_TDMA_FN))) = (API)l1s.actual_time.fn_mod42432;
1121 #endif
1122
1123 #endif // NOT_SIMULATION
1124 }
1125
1126 /*-------------------------------------------------------*/
1127 /* l1dtpu_meas() */
1128 /*-------------------------------------------------------*/
1129 /* Parameters : */
1130 /* Return : */
1131 /* Functionality : */
1132
1133 /* Locosto : should take additional Param of task */
1134
1135 /*-------------------------------------------------------*/
1136 void l1dtpu_meas(UWORD16 radio_freq,
1137 WORD8 agc,
1138 UWORD8 lna_off,
1139 UWORD16 win_id,
1140 UWORD16 tpu_synchro, UWORD8 adc_active
1141 #if(RF_FAM == 61)
1142 ,UWORD8 afc_mode
1143 ,UWORD8 if_ctl
1144 #endif
1145 )
1146
1147 {
1148
1149 WORD16 offset;
1150 WORD16 when;
1151 UWORD16 offset_chg;
1152
1153 #if TESTMODE
1154 if (!l1_config.agc_enable)
1155 {
1156 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1157 // corresponds to the lna_off bit
1158 agc = l1_config.tmode.rx_params.agc;
1159 lna_off = l1_config.tmode.rx_params.lna_off;
1160 }
1161 #endif // TESTMODE
1162
1163 // Compute offset
1164 offset_chg = ((win_id * BP_DURATION) >> BP_SPLIT_PW2);
1165 offset = tpu_synchro + offset_chg;
1166 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE;
1167
1168 // Compute offset change timing
1169 when = offset_chg + PROVISION_TIME - (l1_config.params.rx_synth_setup_time + EPSILON_OFFS);
1170 if(when < 0) when += TPU_CLOCK_RANGE;
1171
1172 // Program TPU scenario
1173 l1dmacro_offset (offset, when); // change TPU offset according to win_id
1174 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1175 if(adc_active == ACTIVE)
1176 l1dmacro_adc_read_rx(); // pgme ADC measurement
1177
1178 l1dmacro_agc (radio_freq, agc,lna_off
1179 #if (RF_FAM == 61)
1180 ,if_ctl
1181 #endif
1182 ); // pgme AGC.
1183 #if (CODE_VERSION == SIMULATION)
1184 l1dmacro_rx_ms (radio_freq, 0); // pgm PWR acquisition.
1185 #else
1186 #if (L1_MADC_ON == 1)
1187 #if (RF_FAM == 61)
1188 l1dmacro_rx_ms (radio_freq,adc_active); // pgm PWR acquisition.
1189 #endif
1190 #else
1191 l1dmacro_rx_ms (radio_freq); // pgm PWR acquisition.
1192 #endif
1193 #endif
1194 l1dmacro_offset (tpu_synchro, IMM); // restore offset
1195
1196 //Locosto
1197 #if(RF_FAM == 61)
1198 // L1_AFC_SCRIPT_MODE - This is specific to Locosto to make AFC script run after
1199 // the second power measurement during FBNEW
1200 if ((win_id == 0) || (afc_mode == L1_AFC_SCRIPT_MODE))
1201 #else
1202 if (win_id == 0)
1203 #endif
1204 {
1205 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
1206 // NOTE: In Locosto AFC is in DRP not in triton
1207 l1ddsp_load_afc(l1s.afc);
1208 #endif
1209
1210 //Locosto
1211 #if(RF_FAM == 61)
1212 if(afc_mode != L1_AFC_NONE)
1213 {
1214 if(afc_mode == L1_AFC_SCRIPT_MODE)
1215 {
1216 l1dtpu_load_afc(l1s.afc); //Load the Initial afc value to the TPU. TPU would copy it to the DRP Wrapper Mem.
1217 }
1218 else
1219 {
1220 l1ddsp_load_afc(l1s.afc);
1221 }
1222 }
1223 #endif
1224 // end Locosto
1225 }
1226 }
1227
1228 /*-------------------------------------------------------*/
1229 /* l1dtpu_neig_fb() */
1230 /*-------------------------------------------------------*/
1231 /* Parameters : */
1232 /* Return : */
1233 /* Functionality : */
1234 /*-------------------------------------------------------*/
1235 void l1dtpu_neig_fb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off)
1236 {
1237 #if TESTMODE
1238 if (!l1_config.agc_enable)
1239 {
1240 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1241 // corresponds to the lna_off bit
1242 agc = l1_config.tmode.rx_params.agc;
1243 lna_off = l1_config.tmode.rx_params.lna_off;
1244 }
1245 #endif
1246
1247 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1248 l1dmacro_agc (radio_freq,agc, lna_off
1249 #if (RF_FAM == 61)
1250 ,IF_120KHZ_DSP
1251 #endif
1252 ); // pgme AGC.
1253 #if (L1_MADC_ON == 1)
1254 #if (RF_FAM == 61)
1255 l1dmacro_rx_fb (radio_freq,INACTIVE); // pgm FB acquisition.
1256 #endif
1257 #else
1258 l1dmacro_rx_fb (radio_freq); // pgm FB acquisition.
1259 #endif
1260 }
1261
1262 /*-------------------------------------------------------*/
1263 /* l1dtpu_neig_fb26() */
1264 /*-------------------------------------------------------*/
1265 /* Parameters : */
1266 /* Return : */
1267 /* Functionality : */
1268 /*-------------------------------------------------------*/
1269 void l1dtpu_neig_fb26(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off, UWORD32 offset_serv)
1270 {
1271 WORD16 offset;
1272
1273 #if TESTMODE
1274 if (!l1_config.agc_enable)
1275 {
1276 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1277 // corresponds to the lna_off bit
1278 agc = l1_config.tmode.rx_params.agc;
1279 lna_off = l1_config.tmode.rx_params.lna_off;
1280 }
1281 #endif
1282
1283 // Compute offset
1284 offset = offset_serv + l1_config.params.fb26_anchoring_time;
1285 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE;
1286
1287 // Program TPU scenario
1288 l1dmacro_offset (offset, l1_config.params.fb26_change_offset_time);
1289 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1290 l1dmacro_agc (radio_freq,agc, lna_off
1291 #if (RF_FAM == 61)
1292 ,IF_120KHZ_DSP
1293 #endif
1294 ); // pgme AGC.
1295 #if (L1_MADC_ON == 1)
1296 #if (RF_FAM == 61)
1297 l1dmacro_rx_fb26 (radio_freq, INACTIVE); // pgm FB acquisition.
1298 #endif
1299 #else
1300 l1dmacro_rx_fb26 (radio_freq); // pgm FB acquisition.
1301 #endif
1302 l1dmacro_offset (offset_serv, IMM); // restore offset
1303 }
1304
1305 /*-------------------------------------------------------*/
1306 /* l1dtpu_neig_sb() */
1307 /*-------------------------------------------------------*/
1308 /* Parameters : */
1309 /* Return : */
1310 /* Functionality : */
1311 /*-------------------------------------------------------*/
1312 void l1dtpu_neig_sb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
1313 UWORD32 time_alignmt, UWORD32 offset_serv, UWORD8 reload_flag,
1314 UWORD8 attempt
1315 #if (RF_FAM == 61)
1316 ,UWORD8 if_ctl
1317 #endif
1318 )
1319 {
1320 UWORD16 offset_neigh;
1321
1322 #if TESTMODE
1323 if (!l1_config.agc_enable)
1324 {
1325 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1326 // corresponds to the lna_off bit
1327 agc = l1_config.tmode.rx_params.agc;
1328 lna_off = l1_config.tmode.rx_params.lna_off;
1329 }
1330 #endif
1331
1332 // compute offset neighbour...
1333 offset_neigh = offset_serv + time_alignmt;
1334 if(offset_neigh >= TPU_CLOCK_RANGE) offset_neigh -= TPU_CLOCK_RANGE;
1335
1336 // load OFFSET with NEIGHBOUR value.
1337 l1dmacro_offset (offset_neigh, l1_config.params.rx_change_offset_time);
1338
1339 // Insert 1 NOP to correct the EPSILON_SYNC side effect.
1340 if(attempt != 2)
1341 if(time_alignmt >= (TPU_CLOCK_RANGE - EPSILON_SYNC))
1342 l1dmacro_offset (offset_neigh, 0); // load OFFSET with NEIGHBOUR value.
1343
1344 l1dmacro_rx_synth(radio_freq); // pgme SYNTH.
1345 l1dmacro_agc (radio_freq, agc, lna_off
1346 #if (RF_FAM == 61)
1347 ,if_ctl
1348 #endif
1349 ); // pgme AGC.
1350 #if (L1_MADC_ON == 1)
1351 #if (RF_FAM == 61)
1352 l1dmacro_rx_sb (radio_freq,INACTIVE); // pgm SB acquisition.
1353 #endif
1354 #else
1355 l1dmacro_rx_sb (radio_freq); // pgm SB acquisition.
1356 #endif
1357
1358 // Restore offset with serving value.
1359 if(reload_flag == TRUE)
1360 {
1361 l1dmacro_offset (offset_serv, IMM);
1362 }
1363 }
1364 /*-------------------------------------------------------*/
1365 /* l1dtpu_neig_fbsb() */
1366 /*-------------------------------------------------------*/
1367 /* Parameters : */
1368 /* Return : */
1369 /* Functionality : */
1370 /*-------------------------------------------------------*/
1371 #if ((REL99 == 1) && (FF_BHO == 1))
1372 /*void l1dtpu_neig_fbsb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off
1373 #if (RF_FAM == 61)
1374 ,UWORD8 if_ctl
1375 #endif
1376 )*/
1377 void l1dtpu_neig_fbsb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off)
1378 {
1379 #if TESTMODE
1380 if (!l1_config.agc_enable)
1381 {
1382 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1383 // corresponds to the lna_off bit
1384 agc = l1_config.tmode.rx_params.agc;
1385 lna_off = l1_config.tmode.rx_params.lna_off;
1386 }
1387 #endif // TESTMODE
1388
1389 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1390 /*l1dmacro_agc(radio_freq, agc, lna_off
1391 #if (RF_FAM == 61)
1392 ,if_ctl
1393 #endif
1394 ); // pgme AGC.
1395 */
1396 l1dmacro_agc (radio_freq,agc, lna_off
1397 #if (RF_FAM == 61)
1398 ,L1_CTL_LOW_IF
1399 #endif
1400 ); // pgme AGC.
1401 #if (L1_MADC_ON == 1)
1402 #if (RF_FAM == 61)
1403 l1dmacro_rx_fbsb(radio_freq,INACTIVE); // pgm FB acquisition.
1404 #endif
1405 #else
1406 l1dmacro_rx_fbsb(radio_freq); // pgm FB acquisition.- sajal commented
1407 #endif
1408 }
1409 #endif // #if ((REL99 == 1) && (FF_BHO == 1))
1410 /*-------------------------------------------------------*/
1411 /* l1dtpu_neig_sb26() */
1412 /*-------------------------------------------------------*/
1413 /* Parameters : */
1414 /* Return : */
1415 /* Functionality : */
1416 /*-------------------------------------------------------*/
1417 void l1dtpu_neig_sb26(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off, UWORD32 time_alignmt,
1418 UWORD32 fn_offset, UWORD32 offset_serv
1419 #if (RF_FAM == 61)
1420 ,UWORD8 if_ctl
1421 #endif
1422 )
1423 {
1424 UWORD16 offset_neigh;
1425
1426 #if TESTMODE
1427 if (!l1_config.agc_enable)
1428 {
1429 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1430 // corresponds to the lna_off bit
1431 agc = l1_config.tmode.rx_params.agc;
1432 lna_off = l1_config.tmode.rx_params.lna_off;
1433 }
1434 #endif
1435
1436 // compute offset neighbour...
1437 offset_neigh = offset_serv + time_alignmt;
1438 if(offset_neigh >= TPU_CLOCK_RANGE) offset_neigh -= TPU_CLOCK_RANGE;
1439
1440 if(fn_offset != 0)
1441 l1dmacro_offset (offset_neigh, 0); // 1 NOP in some case
1442 else
1443 l1dmacro_offset (offset_neigh, l1_config.params.fb26_change_offset_time);
1444
1445 l1dmacro_rx_synth(radio_freq); // pgme SYNTH.
1446 l1dmacro_agc(radio_freq, agc, lna_off
1447 #if (RF_FAM == 61)
1448 ,if_ctl
1449 #endif
1450 ); // pgme AGC.
1451 #if (L1_MADC_ON == 1)
1452 #if (RF_FAM == 61)
1453 l1dmacro_rx_sb (radio_freq, INACTIVE); // pgm SB acquisition.
1454 #endif
1455 #else
1456 l1dmacro_rx_sb (radio_freq); // pgm SB acquisition.
1457 #endif
1458 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value.
1459 }
1460
1461 /*-------------------------------------------------------*/
1462 /* l1dtpu_serv_rx_nb() */
1463 /*-------------------------------------------------------*/
1464 /* Parameters : */
1465 /* Return : */
1466 /* Functionality : */
1467 /*-------------------------------------------------------*/
1468 void l1dtpu_serv_rx_nb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
1469 UWORD32 synchro_serv,UWORD32 new_offset,BOOL change_offset,
1470 UWORD8 adc_active
1471 #if(RF_FAM == 61)
1472 , UWORD8 csf_filter_choice
1473 , UWORD8 if_ctl
1474 #endif
1475 #if (NEW_SNR_THRESHOLD == 1)
1476 , UWORD8 saic_flag
1477 #endif/* NEW_SNR_THRESHOLD == 1*/
1478 )
1479 {
1480
1481 #if (CODE_VERSION == SIMULATION)
1482 UWORD32 tpu_w_page;
1483
1484 if (hw.tpu_r_page==0)
1485 tpu_w_page=1;
1486 else
1487 tpu_w_page=0;
1488
1489 // Give the Ts related to the L1s
1490 hw.rx_id[tpu_w_page][0]= ((TPU_CLOCK_RANGE+new_offset-synchro_serv)%TPU_CLOCK_RANGE)/TN_WIDTH;
1491 hw.num_rx[tpu_w_page][0]=1;
1492 hw.rx_group_id[tpu_w_page]=1;
1493 #endif
1494
1495 #if TESTMODE
1496 if (!l1_config.agc_enable)
1497 {
1498 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1499 // corresponds to the lna_off bit
1500 agc = l1_config.tmode.rx_params.agc;
1501 lna_off = l1_config.tmode.rx_params.lna_off;
1502 }
1503 #endif
1504
1505 l1dmacro_synchro (l1_config.params.rx_change_synchro_time, synchro_serv); // Adjust serving OFFSET.
1506
1507 #if L2_L3_SIMUL
1508 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1509 buffer_trace(3, 0x43, synchro_serv,l1s.actual_time.fn,0);
1510 #endif
1511 #endif
1512
1513 // Need to slide offset to cope with the new synchro.
1514 if(change_offset)
1515 l1dmacro_offset(new_offset, l1_config.params.rx_change_offset_time);
1516
1517 l1dmacro_rx_synth(radio_freq); // load SYNTH.
1518 if(adc_active == ACTIVE)
1519 l1dmacro_adc_read_rx(); // pgme ADC measurement
1520
1521 l1dmacro_agc (radio_freq, agc, lna_off
1522 #if (RF_FAM == 61)
1523 ,if_ctl
1524 #endif
1525 );
1526
1527 #if TESTMODE && (CODE_VERSION != SIMULATION)
1528 // Continuous mode: Rx continuous scenario only on START_RX state.
1529 if ((l1_config.TestMode) &&
1530 (l1_config.tmode.rf_params.tmode_continuous == TM_START_RX_CONTINUOUS))
1531 #if (L1_MADC_ON == 1)
1532 #if (RF_FAM == 61)
1533 l1dmacro_rx_cont (FALSE, radio_freq,adc_active,csf_filter_choice
1534 #if (NEW_SNR_THRESHOLD == 1)
1535 ,saic_flag
1536 #endif /* NEW_SNR_THRESHOLD*/
1537 );
1538 #endif /* RF_FAM == 61*/
1539 #else /* L1_MADC_ON == 1 */
1540 #if (RF_FAM == 61)
1541 l1dmacro_rx_cont (FALSE, radio_freq,csf_filter_choice);
1542 #else
1543 l1dmacro_rx_cont (FALSE, radio_freq);
1544 #endif
1545 #endif
1546 //TBD Danny New MAcro for Cont Tx reqd, to use only External Trigger
1547 else
1548 #endif
1549 #if ( L1_MADC_ON == 1)
1550 #if (RF_FAM == 61)
1551 l1dmacro_rx_nb (radio_freq, adc_active, csf_filter_choice
1552 #if (NEW_SNR_THRESHOLD == 1)
1553 ,saic_flag
1554 #endif /* NEW_SNR_THRESHOLD*/
1555 ); // RX window for NB.
1556 #endif /* RF_FAM == 61*/
1557 #else /* L1_MADC_ON == 1*/
1558 #if (RF_FAM == 61)
1559 l1dmacro_rx_nb (radio_freq, csf_filter_choice); // RX window for NB.
1560 #else
1561 l1dmacro_rx_nb (radio_freq); // RX window for NB.
1562 #endif
1563 #endif
1564
1565 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
1566 l1ddsp_load_afc(l1s.afc);
1567 #endif
1568 #if (RF_FAM == 61)
1569 l1dtpu_load_afc(l1s.afc);
1570 #endif
1571
1572
1573 if(change_offset)
1574 l1dmacro_offset(synchro_serv, IMM); // Restore offset.
1575 }
1576
1577 /*-------------------------------------------------------*/
1578 /* l1dtpu_serv_tx_nb() */
1579 /*-------------------------------------------------------*/
1580 /* Parameters : */
1581 /* Return : */
1582 /* Functionality : */
1583 /*-------------------------------------------------------*/
1584 void l1dtpu_serv_tx_nb(UWORD16 radio_freq, UWORD8 timing_advance,
1585 UWORD32 offset_serv, UWORD8 txpwr, UWORD8 adc_active)
1586 {
1587 WORD32 time;
1588 UWORD32 offset_tx;
1589 UWORD32 timing_advance_in_qbit = (UWORD32)timing_advance << 2;
1590
1591 #if (CODE_VERSION == SIMULATION)
1592 UWORD32 tpu_w_page;
1593
1594 if (hw.tpu_r_page==0)
1595 tpu_w_page=1;
1596 else
1597 tpu_w_page=0;
1598
1599 hw.tx_id[tpu_w_page][0]=3;// MS synchronized on TN=0 for RX => TN=3 for TX
1600 hw.num_tx[tpu_w_page][0]=1;
1601 hw.tx_group_id[tpu_w_page]=1;
1602 #endif
1603
1604 // Reset timing advance if TA_ALGO not enabled.
1605 #if !TA_ALGO
1606 timing_advance_in_qbit = 0;
1607 #endif
1608
1609 // Compute offset value for TX.
1610 // PRG_TX has become variable, no longer contained in TIME_OFFSET_TX !
1611 offset_tx = (offset_serv + TIME_OFFSET_TX-l1_config.params.prg_tx_gsm - timing_advance_in_qbit) ;
1612 if (offset_tx >= TPU_CLOCK_RANGE) offset_tx -= TPU_CLOCK_RANGE;
1613
1614 // Check that RX controle has been already installed.
1615 // Offset for TX must be set an immediately if RX is there else
1616 // it must be performed EPSILON_SYNC before current offset time.
1617 if( l1s.tpu_ctrl_reg & CTRL_RX )
1618 time = l1_config.params.tx_change_offset_time - l1_config.params.prg_tx_gsm;
1619 else
1620 time = TPU_CLOCK_RANGE - EPSILON_SYNC;
1621
1622 l1dmacro_offset (offset_tx, time); // load OFFSET for TX before each burst.
1623
1624 #if L2_L3_SIMUL
1625 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1626 buffer_trace(2, offset_tx,l1s.actual_time.fn,0,0);
1627 #endif
1628 #endif
1629
1630 l1dmacro_tx_synth(radio_freq); // load SYNTH.
1631 #if TESTMODE && (CODE_VERSION != SIMULATION)
1632 // Continuous mode: Tx continuous scenario only on START_TX state.
1633 #if (RF_FAM != 61)
1634 if ((l1_config.TestMode) &&
1635 (l1_config.tmode.rf_params.tmode_continuous == TM_START_TX_CONTINUOUS))
1636 l1dmacro_tx_cont (radio_freq, txpwr); // TX window for NB.
1637 else
1638 #endif // RF_FAM != 61
1639 #if (RF_FAM == 61)
1640 // NOTE: In Test Mode and in TX Continuous, APC control is in manual mode
1641 // This is done in l1tm_async.c
1642 if ((l1_config.TestMode) &&
1643 (l1_config.tmode.rf_params.tmode_continuous == TM_START_TX_CONTINUOUS))
1644 {
1645 // NOTE: APC is set in manual mode from l1tm_async.c
1646 l1dmacro_tx_cont (radio_freq, txpwr); // TX window for NB.
1647 }
1648 else
1649 #endif // RF_FAM == 61
1650 #endif
1651 l1dmacro_tx_nb (radio_freq, txpwr, adc_active); // TX window for NB.
1652 // TX window for NB.
1653 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value.
1654
1655 #if L2_L3_SIMUL
1656 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1657 buffer_trace(2, offset_serv,l1s.actual_time.fn,0,0);
1658 #endif
1659 #endif
1660 }
1661
1662 /*-------------------------------------------------------*/
1663 /* l1dtpu_neig_rx_nb() */
1664 /*-------------------------------------------------------*/
1665 /* Parameters : */
1666 /* Return : */
1667 /* Functionality : */
1668 /*-------------------------------------------------------*/
1669 void l1dtpu_neig_rx_nb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
1670 UWORD32 time_alignmt, UWORD32 offset_serv, UWORD8 reload_flag,
1671 UWORD8 nop
1672 #if (RF_FAM == 61)
1673 ,UWORD8 if_ctl
1674 #endif
1675 #if (NEW_SNR_THRESHOLD == 1)
1676 ,UWORD8 saic_flag
1677 #endif /* NEW_SNR_THRESHOLD*/
1678 )
1679 {
1680 UWORD32 offset_neigh;
1681 #if (RF_FAM == 61)
1682 // By default we choose the hardware filter for neighbour Normal Bursts
1683 UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER;
1684 #endif
1685
1686 #if TESTMODE
1687 if (!l1_config.agc_enable)
1688 {
1689 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1690 // corresponds to the lna_off bit
1691 agc = l1_config.tmode.rx_params.agc;
1692 lna_off = l1_config.tmode.rx_params.lna_off;
1693 }
1694 #endif
1695
1696 // compute offset neighbour...
1697 offset_neigh = (offset_serv + time_alignmt) ;
1698 if (offset_neigh >= TPU_CLOCK_RANGE) offset_neigh -= TPU_CLOCK_RANGE;
1699
1700 l1dmacro_offset (offset_neigh, l1_config.params.rx_change_offset_time); // load OFFSET with NEIGHBOUR value.
1701 // Insert 1 NOP to correct the EPSILON_SYNC side effect
1702 if (nop ==1) l1dmacro_offset (offset_neigh,0);
1703
1704
1705 l1dmacro_rx_synth(radio_freq); // load SYNTH.
1706 l1dmacro_agc (radio_freq, agc, lna_off
1707 #if (RF_FAM == 61)
1708 ,if_ctl
1709 #endif
1710 );
1711 #if (L1_MADC_ON == 1)
1712 #if (RF_FAM == 61)
1713 l1dmacro_rx_nb (radio_freq, INACTIVE, csf_filter_choice
1714 #if (NEW_SNR_THRESHOLD == 1)
1715 ,saic_flag
1716 #endif /* NEW_SNR_THRESHOLD*/
1717 ) ; // RX window for NB.
1718 #endif /* RF_FAM == 61*/
1719 #else /* L1_MADC_ON == 1*/
1720 #if (RF_FAM == 61)
1721 l1dmacro_rx_nb (radio_freq, csf_filter_choice); // RX window for NB.
1722 #else
1723 l1dmacro_rx_nb (radio_freq); // RX window for NB.
1724 #endif
1725 #endif
1726
1727 // Restore offset with serving value.
1728 if(reload_flag == TRUE)
1729 l1dmacro_offset (offset_serv, IMM);
1730
1731 }
1732
1733 /*-------------------------------------------------------*/
1734 /* l1dtpu_serv_tx_ra() */
1735 /*-------------------------------------------------------*/
1736 /* Parameters : "burst_id" gives the burst identifier */
1737 /* which is used for offset management. */
1738 /* Return : */
1739 /* Functionality : */
1740 /*-------------------------------------------------------*/
1741 void l1dtpu_serv_tx_ra(UWORD16 radio_freq, UWORD32 offset_serv, UWORD8 txpwr, UWORD8 adc_active)
1742 {
1743 WORD32 time;
1744 UWORD32 offset_tx;
1745
1746 // Compute offset value for TX.
1747 // Rem: Timing Advance is always 0 for a RA.
1748 // PRG_TX has become variable, no longer contained in TIME_OFFSET_TX !
1749 offset_tx = (offset_serv + TIME_OFFSET_TX-l1_config.params.prg_tx_gsm);
1750 if (offset_tx >= TPU_CLOCK_RANGE) offset_tx -= TPU_CLOCK_RANGE;
1751
1752 // Check that RX controle has been already installed.
1753 // Offset for TX must be set an immediately if RX is there else
1754 // it must be performed EPSILON_SYNC before current offset time.
1755 if( l1s.tpu_ctrl_reg & CTRL_RX )
1756 time = l1_config.params.tx_change_offset_time - l1_config.params.prg_tx_gsm;
1757 else
1758 time = TPU_CLOCK_RANGE - EPSILON_SYNC;
1759
1760 l1dmacro_offset (offset_tx, time); // load OFFSET for TX before each burst.
1761 #if L2_L3_SIMUL
1762 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1763 buffer_trace(2, offset_tx,l1s.actual_time.fn,0,0);
1764 #endif
1765 #endif
1766 l1dmacro_tx_synth(radio_freq); // load SYNTH.
1767 l1dmacro_tx_ra (radio_freq, txpwr,adc_active); // TX window for RA.
1768 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value.
1769 #if L2_L3_SIMUL
1770 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1771 buffer_trace(2, offset_serv,l1s.actual_time.fn,0,0);
1772 #endif
1773 #endif
1774 }
1775
1776 /*-------------------------------------------------------*/
1777 /* l1dtpu_end_scenario() */
1778 /*-------------------------------------------------------*/
1779 /* Parameters : */
1780 /* Return : */
1781 /* Functionality : */
1782 /*-------------------------------------------------------*/
1783 void l1dtpu_end_scenario(void)
1784 {
1785
1786 // write IDLE at end of TPU page
1787 // TPU_ENB and TPU_PAG are set in L1DMACRO_IDLE(). The TPU change
1788 // is executed by the TPU itself and the TPU pointer is reset to
1789 // start of page by l1dmacro_idle();
1790 l1dmacro_idle();
1791
1792 #if (CODE_VERSION == SIMULATION)
1793 #if LOGTPU_TRACE
1794 log_macro();
1795 #endif
1796 #endif
1797 // init pointer within new TPU page at 1st line
1798 #if (CODE_VERSION == SIMULATION)
1799 // set TPU_ENB, TPU_PAG for communication interrupt
1800 l1s_tpu_com.reg_cmd->tpu_pag_bit = l1s_tpu_com.tpu_w_page;
1801 l1s_tpu_com.reg_cmd->tpu_enb_bit = ON;
1802
1803 // change TPU and DSP page pointer for next control
1804 l1s_tpu_com.tpu_w_page ^= 1;
1805
1806 // points on new "write TPU page"...
1807 l1s_tpu_com.tpu_page_ptr=&(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
1808
1809 #endif
1810
1811 }
1812
1813 /*-------------------------------------------------------*/
1814 /* l1d_reset_hw() */
1815 /*-------------------------------------------------------*/
1816 /* Parameters : */
1817 /* Return : */
1818 /* Functionality : */
1819 /*-------------------------------------------------------*/
1820 void l1d_reset_hw(UWORD32 offset_value)
1821 {
1822 #if (CODE_VERSION == SIMULATION)
1823 // Reset DSP write/read page, Reset TPU write page, reset "used" flag.
1824 l1s_dsp_com.dsp_w_page = 0;
1825 l1s_dsp_com.dsp_r_page = 0;
1826 l1s_tpu_com.tpu_w_page = 0;
1827 l1s_dsp_com.dsp_r_page_used = 0;
1828
1829 // Reset communication pointers.
1830 l1s_dsp_com.dsp_ndb_ptr = &(buf.ndb); // MCU<->DSP comm. read/write (Non Double Buffered comm. memory).
1831 l1s_dsp_com.dsp_db_r_ptr = &(buf.mcu_rd[l1s_dsp_com.dsp_r_page]); // MCU<->DSP comm. read page (Double Buffered comm. memory).
1832 l1s_dsp_com.dsp_db_w_ptr = &(buf.mcu_wr[l1s_dsp_com.dsp_w_page]); // MCU<->DSP comm. write page (Double Buffered comm. memory).
1833
1834 // Reset task commands.
1835 l1s_dsp_com.dsp_db_w_ptr->d_task_d = NO_DSP_TASK; // Init. RX task to NO TASK.
1836 l1s_dsp_com.dsp_db_w_ptr->d_task_u = NO_DSP_TASK; // Init. TX task to NO TASK.
1837 l1s_dsp_com.dsp_db_w_ptr->d_task_ra = NO_DSP_TASK; // Init. RA task to NO TASK.
1838 l1s_dsp_com.dsp_db_w_ptr->d_task_md = NO_DSP_TASK; // Init. MONITORING task to NO TASK.
1839
1840
1841 //Reset the TCH channel description
1842 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = 0;
1843
1844 #if (L1_GPRS)
1845 // Reset communication pointers.
1846 l1ps_dsp_com.pdsp_db_r_ptr = &(buf.mcu_rd_gprs[l1s_dsp_com.dsp_r_page]);
1847 l1ps_dsp_com.pdsp_db_w_ptr = &(buf.mcu_wr_gprs[l1s_dsp_com.dsp_w_page]);
1848
1849 // Reset MCU->DSP page.
1850 l1ps_reset_db_mcu_to_dsp(l1ps_dsp_com.pdsp_db_w_ptr);
1851 #endif // L1_GPRS
1852
1853 // Direct access to TPU_RESET_BIT.
1854 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // Reset TPU.
1855
1856 // Reset TPU_ENB, DSP_ENB and TPU_PAG, DSP_PAG for communication interrupt
1857 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
1858 l1s_tpu_com.reg_cmd->dsp_pag_bit = 0;
1859 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
1860 l1s_tpu_com.reg_cmd->dsp_enb_bit = OFF;
1861
1862 // Init pointer within TPU page 0 at 1st line
1863 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[0].line[0]);
1864
1865 // Load offset register according to serving cell.
1866 l1dmacro_offset(offset_value, IMM);
1867
1868 #else // NOT_SIMULATION
1869
1870 // Reset DSP write/read page, Reset TPU write page, reset "used" flag.
1871 l1s_dsp_com.dsp_w_page = 0;
1872 l1s_dsp_com.dsp_r_page = 0;
1873 l1s_tpu_com.tpu_w_page = 0;
1874 l1s_dsp_com.dsp_r_page_used = 0;
1875
1876 // Reset communication pointers.
1877 l1s_dsp_com.dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR; // MCU<->DSP comm. read/write (Non Double Buffered comm. memory).
1878 l1s_dsp_com.dsp_db_r_ptr = (T_DB_DSP_TO_MCU *) DB_R_PAGE_0; // MCU<->DSP comm. read page (Double Buffered comm. memory).
1879 l1s_dsp_com.dsp_db_w_ptr = (T_DB_MCU_TO_DSP *) DB_W_PAGE_0; // MCU<->DSP comm. write page (Double Buffered comm. memory).
1880 l1s_dsp_com.dsp_param_ptr= (T_PARAM_MCU_DSP *) PARAM_ADR;
1881
1882 #if (DSP == 38) || (DSP == 39)
1883 l1s_dsp_com.dsp_db_common_w_ptr = (T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_0;
1884 #endif
1885
1886 // Reset task commands.
1887 l1s_dsp_com.dsp_db_w_ptr->d_task_d = NO_DSP_TASK; // Init. RX task to NO TASK.
1888 l1s_dsp_com.dsp_db_w_ptr->d_task_u = NO_DSP_TASK; // Init. TX task to NO TASK.
1889 l1s_dsp_com.dsp_db_w_ptr->d_task_ra = NO_DSP_TASK; // Init. RA task to NO TASK.
1890 l1s_dsp_com.dsp_db_w_ptr->d_task_md = NO_DSP_TASK; // Init. MONITORING task to NO TASK.
1891
1892 //Reset the TCH channel description
1893 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = 0;
1894
1895 // Clear DSP_PAG bit
1896 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
1897 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = 0;
1898 #else
1899 l1s_dsp_com.dsp_param_ptr->d_dsp_page = 0;
1900 #endif
1901
1902 #if (L1_GPRS)
1903 // Reset communication pointers.
1904 l1ps_dsp_com.pdsp_ndb_ptr = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS;
1905 l1ps_dsp_com.pdsp_db_r_ptr = (T_DB_DSP_TO_MCU_GPRS *) DB_R_PAGE_0_GPRS;
1906 l1ps_dsp_com.pdsp_db_w_ptr = (T_DB_MCU_TO_DSP_GPRS *) DB_W_PAGE_0_GPRS;
1907 l1ps_dsp_com.pdsp_param_ptr= (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS;
1908
1909 // Reset MCU->DSP page.
1910 l1ps_reset_db_mcu_to_dsp(l1ps_dsp_com.pdsp_db_w_ptr);
1911 #endif // L1_GPRS
1912
1913 #if (DSP_DEBUG_TRACE_ENABLE == 1)
1914 l1s_dsp_com.dsp_db2_current_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_0;
1915 l1s_dsp_com.dsp_db2_other_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_1;
1916 #endif
1917
1918 // Reset TPU and Reload offset register with Serving value.
1919 // Clear TPU_PAG
1920 l1dmacro_reset_hw(offset_value);
1921 #endif // NOT_SIMULATION
1922 }
1923
1924
1925 #if(RF_FAM == 61)
1926
1927 /*-------------------------------------------------------*/
1928 /* l1apc_init_ramp_tables() */
1929 /*-------------------------------------------------------*/
1930 /* Parameters : void */
1931 /* Return : void */
1932 /* Functionality : This would copy the Ramp table */
1933 /* values to the MCU DSP API */
1934 /*-------------------------------------------------------*/
1935 void l1dapc_init_ramp_tables(void)
1936 {
1937
1938 #if (CODE_VERSION == SIMULATION)
1939 // Do Nothing there is no APC task
1940 #else
1941 #if ( DSP == 38) || (DSP == 39)
1942 // Load RAMP up/down in NDB memory...
1943 if (l1_config.tx_pwr_code == 0)
1944 {
1945 Cust_get_ramp_tab( l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp,
1946 0 /* not used */,
1947 0 /* not used */,
1948 1 /* arbitrary value for arfcn*/);
1949
1950 }
1951 else
1952 {
1953 Cust_get_ramp_tab( l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp,
1954 5 /* arbitrary value working in any case */,
1955 5 /* arbitrary value working in any case */,
1956 1 /* arbitrary value for arfcn*/);
1957 }
1958 #endif
1959 // Is it required to load ramptables for GPRS a_drp2_ramp_gprs
1960
1961 #endif
1962
1963 }
1964
1965
1966
1967 /*-------------------------------------------------------*/
1968 /* l1ddsp_apc_load_apcctrl2 */
1969 /*-------------------------------------------------------*/
1970 /* Parameters : void */
1971 /* Return : void */
1972 /* Functionality : This would copy the Ramp table */
1973 /* values to the MCU DSP API */
1974 /*-------------------------------------------------------*/
1975 void l1ddsp_apc_load_apcctrl2(UWORD16 apcctrl2)
1976 {
1977 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 = ((apcctrl2) | (0x8000));
1978 }
1979
1980 /*-------------------------------------------------------*/
1981 /* l1ddsp_apc_set_manual_mode */
1982 /*-------------------------------------------------------*/
1983 /* Parameters : void */
1984 /* Return : void */
1985 /* Functionality : This would set the APC in manual */
1986 /* OR external trigger mode */
1987 /*-------------------------------------------------------*/
1988 void l1ddsp_apc_set_manual_mode(void)
1989 {
1990 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 |= ((APC_APC_MODE) | (0x8000));
1991 }
1992
1993 /*-------------------------------------------------------*/
1994 /* l1ddsp_apc_set_automatic_mode */
1995 /*-------------------------------------------------------*/
1996 /* Parameters : void */
1997 /* Return : void */
1998 /* Functionality : This would set APC in automatic */
1999 /* OR internal sequencer mode */
2000 /*-------------------------------------------------------*/
2001 void l1ddsp_apc_set_automatic_mode(void)
2002 {
2003 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 &= ~(APC_APC_MODE);
2004 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 |= (0x8000);
2005 }
2006
2007 #ifdef TESTMODE
2008
2009 /*-------------------------------------------------------*/
2010 /* l1ddsp_apc_load_apclev */
2011 /*-------------------------------------------------------*/
2012 /* Parameters : void */
2013 /* Return : void */
2014 /* Functionality : This function writes the apclev */
2015 /* val into the APCLEV register via DSP */
2016 /* NOTE: Used only in TESTMODE and only when */
2017 /* l1_config.tmode.rf_params.down_up == TMODE_UPLINK; */
2018 /*-------------------------------------------------------*/
2019 void l1ddsp_apc_load_apclev(UWORD16 apclev)
2020 {
2021 l1s_dsp_com.dsp_ndb_ptr->d_apclev = ((apclev) | (0x8000));
2022 }
2023
2024
2025 #endif // TESTMODE
2026
2027 #endif
2028 #if FF_L1_IT_DSP_DTX
2029 /*-------------------------------------------------------*/
2030 /* l1ddsp_dtx_interrupt_pending() */
2031 /*-------------------------------------------------------*/
2032 /* Parameters : */
2033 /* Return : DTX interrupt status */
2034 /* Functionality : Test and clear the DTX IT pending */
2035 /* flag for DSP ISR screening purpose */
2036 /*-------------------------------------------------------*/
2037 BOOL l1ddsp_dtx_interrupt_pending(void)
2038 {
2039 if (l1s_dsp_com.dsp_ndb_ptr->d_dsp_hint_flag & (2 << B_DTX_HINT_ISSUED))
2040 {
2041 // Flag HISR to be scheduled
2042 l1a_apihisr_com.dtx.pending = TRUE;
2043 // Clear API ISR condition
2044 l1s_dsp_com.dsp_ndb_ptr->d_dsp_hint_flag &= ~(2 << B_DTX_HINT_ISSUED);
2045 return TRUE;
2046 }
2047 else
2048 return FALSE;
2049 }
2050 #endif
2051
2052
2053 #define L1_DEBUG_IQ_DUMP 0
2054
2055 #if (L1_DEBUG_IQ_DUMP == 1)
2056
2057 #define IQ_DUMP_MAX_LOG_SIZE (400) /* i.e. 200 I-Q Sample Pair */
2058 #define IQ_DUMP_BUFFER_SIZE (1280)
2059 #define L1_DSP_DUMP_IQ_BUFFER_PAGE0 (0xFFD00000 + ((0x2000 - 0x800)*2))
2060 #define L1_DSP_DUMP_IQ_BUFFER_PAGE1 (0xFFD00000 + ((0x2190 - 0x800)*2))
2061
2062 typedef struct
2063 {
2064 UWORD8 task;
2065 UWORD8 hole;
2066 UWORD16 size;
2067 UWORD16 fn_mod42432;
2068 UWORD16 iq_sample[IQ_DUMP_MAX_LOG_SIZE];
2069 }T_IQ_LOG_BUFFER;
2070
2071 #pragma DATA_SECTION(iq_dump_buffer,".debug_data");
2072 T_IQ_LOG_BUFFER iq_dump_buffer[IQ_DUMP_BUFFER_SIZE];
2073
2074 UWORD32 iq_dump_buffer_log_index = 0;
2075 UWORD32 iq_overflow_ind=0;
2076
2077 #endif
2078
2079 void l1ddsp_read_iq_dump(UWORD8 task)
2080 {
2081
2082 #if (L1_DEBUG_IQ_DUMP == 1)
2083 UWORD16 *p_dsp_iq_buffer_ptr;
2084 UWORD16 size;
2085 int i;
2086
2087 /* get the page logic*/
2088 p_dsp_iq_buffer_ptr = (UWORD16 *)(L1_DSP_DUMP_IQ_BUFFER_PAGE0);
2089 if(l1s_dsp_com.dsp_r_page){
2090 p_dsp_iq_buffer_ptr = (UWORD16 *)(L1_DSP_DUMP_IQ_BUFFER_PAGE1);
2091 }
2092
2093 /* */
2094 size = *p_dsp_iq_buffer_ptr;
2095
2096 if(size == 0)
2097 return;
2098
2099 /* size given by DSP is in units of I-Q sample pair */
2100 if(size > (IQ_DUMP_MAX_LOG_SIZE /2)){
2101 size = (IQ_DUMP_MAX_LOG_SIZE/2);
2102 }
2103
2104 /* make size as zero again */
2105 *p_dsp_iq_buffer_ptr++ = 0;
2106
2107 if(iq_dump_buffer_log_index >= IQ_DUMP_BUFFER_SIZE){
2108 iq_overflow_ind=1;
2109 iq_dump_buffer_log_index = 0;
2110 }
2111
2112 iq_dump_buffer[iq_dump_buffer_log_index].task = task;
2113 iq_dump_buffer[iq_dump_buffer_log_index].hole = 0;
2114 iq_dump_buffer[iq_dump_buffer_log_index].size = size;
2115 iq_dump_buffer[iq_dump_buffer_log_index].fn_mod42432 = l1s.actual_time.fn_mod42432;
2116
2117 memcpy(&iq_dump_buffer[iq_dump_buffer_log_index].iq_sample[0],
2118 p_dsp_iq_buffer_ptr,
2119 size*2*2); /* size * 2 (as size is in IQsample pair) * 2 (to convert to bytes) */
2120
2121 iq_dump_buffer_log_index = iq_dump_buffer_log_index + 1;
2122
2123 #endif
2124 }
2125
2126