FreeCalypso > hg > freecalypso-citrine
comparison L1/cfile/l1_func.c @ 0:75a11d740a02
initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 09 Jun 2016 00:02:41 +0000 |
parents | |
children | b36540edb046 |
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-1:000000000000 | 0:75a11d740a02 |
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1 /************* Revision Controle System Header ************* | |
2 * GSM Layer 1 software | |
3 * L1_FUNC.C | |
4 * | |
5 * Filename l1_func.c | |
6 * Copyright 2003 (C) Texas Instruments | |
7 * | |
8 ************* Revision Controle System Header *************/ | |
9 | |
10 #define L1_FUNC_C | |
11 | |
12 #include "config.h" | |
13 #include "l1_confg.h" | |
14 #include "l1_macro.h" | |
15 | |
16 #if (CODE_VERSION == SIMULATION) | |
17 #include <string.h> | |
18 #include "l1_types.h" | |
19 #include "sys_types.h" | |
20 #include "l1_const.h" | |
21 #include "l1_time.h" | |
22 #include "l1_signa.h" | |
23 #if TESTMODE | |
24 #include "l1tm_defty.h" | |
25 #endif | |
26 #if (AUDIO_TASK == 1) | |
27 #include "l1audio_const.h" | |
28 #include "l1audio_cust.h" | |
29 #include "l1audio_defty.h" | |
30 #endif | |
31 #if (L1_GTT == 1) | |
32 #include "l1gtt_const.h" | |
33 #include "l1gtt_defty.h" | |
34 #endif | |
35 #if (L1_MP3 == 1) | |
36 #include "l1mp3_defty.h" | |
37 #endif | |
38 #if (L1_MIDI == 1) | |
39 #include "l1midi_defty.h" | |
40 #endif | |
41 //ADDED FOR AAC | |
42 #if (L1_AAC == 1) | |
43 #include "l1aac_defty.h" | |
44 #endif | |
45 #include "l1_defty.h" | |
46 #include "cust_os.h" | |
47 #include "l1_msgty.h" | |
48 #include "l1_varex.h" | |
49 #include "l1_proto.h" | |
50 #include "l1_mftab.h" | |
51 #include "l1_tabs.h" | |
52 #include "l1_ver.h" | |
53 | |
54 #if L1_GPRS | |
55 #include "l1p_cons.h" | |
56 #include "l1p_msgt.h" | |
57 #include "l1p_deft.h" | |
58 #include "l1p_vare.h" | |
59 #include "l1p_tabs.h" | |
60 #include "l1p_macr.h" | |
61 #endif | |
62 | |
63 #include "l1_rf2.h" | |
64 #include <stdio.h> | |
65 #include "sim_cfg.h" | |
66 #include "sim_cons.h" | |
67 #include "sim_def.h" | |
68 #include "sim_var.h" | |
69 | |
70 #else | |
71 | |
72 #include <string.h> | |
73 #include "l1_types.h" | |
74 #include "sys_types.h" | |
75 #include "l1_const.h" | |
76 #if (RF_FAM == 12) | |
77 #include "l1_rf12.h" | |
78 #elif (RF_FAM == 61) | |
79 #include "l1_rf61.h" | |
80 #endif | |
81 #include "l1_time.h" | |
82 #include "l1_signa.h" | |
83 | |
84 #if TESTMODE | |
85 #include "l1tm_defty.h" | |
86 #endif | |
87 #if (AUDIO_TASK == 1) | |
88 #include "l1audio_const.h" | |
89 #include "l1audio_cust.h" | |
90 #include "l1audio_defty.h" | |
91 #endif | |
92 #if (L1_GTT == 1) | |
93 #include "l1gtt_const.h" | |
94 #include "l1gtt_defty.h" | |
95 #endif | |
96 #if (L1_MP3 == 1) | |
97 #include "l1mp3_defty.h" | |
98 #endif | |
99 #if (L1_MIDI == 1) | |
100 #include "l1midi_defty.h" | |
101 #endif | |
102 //ADDED FOR AAC | |
103 #if (L1_AAC == 1) | |
104 #include "l1aac_defty.h" | |
105 #endif | |
106 #include "l1_defty.h" | |
107 #include "../../gpf/inc/cust_os.h" | |
108 #include "l1_msgty.h" | |
109 #include "l1_varex.h" | |
110 #include "l1_proto.h" | |
111 #include "l1_mftab.h" | |
112 #include "l1_tabs.h" | |
113 #include "l1_ver.h" | |
114 #include "tpudrv.h" | |
115 | |
116 #include "../../bsp/mem.h" | |
117 #include "../../bsp/inth.h" | |
118 #include "../../bsp/clkm.h" | |
119 #include "../../bsp/rhea_arm.h" | |
120 #include "../../bsp/dma.h" | |
121 #include "../../bsp/ulpd.h" | |
122 #include "../dsp/leadapi.h" | |
123 | |
124 #if (OP_L1_STANDALONE) | |
125 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \ | |
126 (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15) | |
127 #include "dynamic_clock.h" | |
128 #endif | |
129 #endif | |
130 | |
131 | |
132 #if L1_GPRS | |
133 #include "l1p_cons.h" | |
134 #include "l1p_msgt.h" | |
135 #include "l1p_deft.h" | |
136 #include "l1p_vare.h" | |
137 #include "l1p_tabs.h" | |
138 #include "l1p_macr.h" | |
139 #endif | |
140 | |
141 #endif | |
142 #include "l1_trace.h" | |
143 | |
144 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7)) | |
145 extern void L1_trace_string(char *s); | |
146 #endif | |
147 | |
148 | |
149 #if (CODE_VERSION != SIMULATION) | |
150 | |
151 /* DSP patch */ | |
152 #if (DWNLD == NO_DWNLD) | |
153 const UWORD8 patch_array[1] = {0}; | |
154 const UWORD8 DspCode_array[1] = {0}; | |
155 const UWORD8 DspData_array[1] = {0}; | |
156 #elif (DWNLD == PATCH_DWNLD) | |
157 extern const UWORD8 patch_array[] ; | |
158 const UWORD8 DspCode_array[1] = {0}; | |
159 const UWORD8 DspData_array[1] = {0}; | |
160 #elif (DWNLD == DSP_DWNLD) | |
161 const UWORD8 patch_array[1] = {0}; | |
162 extern const UWORD8 DspCode_array[] ; | |
163 extern const UWORD8 DspData_array[]; | |
164 #else | |
165 extern const UWORD8 patch_array[] ; | |
166 extern const UWORD8 DspCode_array[] ; | |
167 extern const UWORD8 DspData_array[]; | |
168 #endif | |
169 | |
170 extern const UWORD8 bootCode[] ; | |
171 UWORD32 fn_prev; // Added as a debug stage.. | |
172 /* DSP patch */ | |
173 | |
174 | |
175 /*-------------------------------------------------------*/ | |
176 /* Prototypes of internal functions used in this file. */ | |
177 /*-------------------------------------------------------*/ | |
178 void l1s_init_voice_blocks (void); | |
179 | |
180 /*-------------------------------------------------------*/ | |
181 /* Prototypes of external functions used in this file. */ | |
182 /*-------------------------------------------------------*/ | |
183 void l1dmacro_synchro (UWORD32 when, UWORD32 value); | |
184 void LA_ReleaseLead(void); | |
185 #if (CODE_VERSION != SIMULATION) | |
186 void l1s_audio_path_control (UWORD16 FIR_selection, UWORD16 audio_loop); | |
187 #endif | |
188 | |
189 #if (L1_GPRS) | |
190 // external functions from GPRS implementation | |
191 void initialize_l1pvar(void); | |
192 void l1pa_reset_cr_freq_list(void); | |
193 #endif | |
194 /*-------------------------------------------------------*/ | |
195 /* dsp_power_on() */ | |
196 /*-------------------------------------------------------*/ | |
197 /* Parameters : */ | |
198 /* Return : */ | |
199 /* Functionality : */ | |
200 /* Remarq : USART Buffer is 256 characters. While USART*/ | |
201 /* is not run during Application_Initialize */ | |
202 /* (hisrs not served because Nucleus scheduler*/ | |
203 /* is not running yet) : */ | |
204 /* ==> check string size < 256 !!!!!! */ | |
205 /*-------------------------------------------------------*/ | |
206 void dsp_power_on(void) | |
207 { | |
208 UWORD16 dsp_start_address =0 ;//omaps00090550 | |
209 UWORD16 param_size; | |
210 #if IDS | |
211 UWORD16 param_size2; | |
212 #endif | |
213 | |
214 API i; | |
215 API *pt; | |
216 volatile WORD16 j; | |
217 | |
218 T_NDB_MCU_DSP * dsp_ndb_ptr; | |
219 | |
220 #if (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
221 static API_SIGNED param_tab[] = { | |
222 | |
223 D_TRANSFER_RATE, | |
224 | |
225 // ..................Latencies | |
226 D_LAT_MCU_BRIDGE, D_LAT_MCU_HOM2SAM, | |
227 | |
228 D_LAT_MCU_BEF_FAST_ACCESS, D_LAT_DSP_AFTER_SAM, | |
229 | |
230 //...................p_gprs_install_adress | |
231 D_HOLE, | |
232 | |
233 //...................d_misc_config | |
234 D_MISC_CONFIG, | |
235 | |
236 | |
237 //...................d_cn_sw_workaround | |
238 C_DSP_SW_WORK_AROUND, | |
239 | |
240 //...................Reserved | |
241 D_HOLE, D_HOLE, | |
242 D_HOLE, D_HOLE, | |
243 | |
244 //...................Frequency burst | |
245 D_FB_MARGIN_BEG, D_FB_MARGIN_END, | |
246 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
247 D_FB_THR_DET_TRACK, | |
248 //...................Demodulation | |
249 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
250 D_DEM_POND_RED, | |
251 //...................TCH Full Speech | |
252 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
253 D_GU, D_GO, D_ATTMAX, | |
254 D_SM, D_B, | |
255 | |
256 //...................V42 bis | |
257 D_V42B_SWITCH_HYST, D_V42B_SWITCH_MIN, D_V42B_SWITCH_MAX, | |
258 D_V42B_RESET_DELAY, | |
259 | |
260 //...................TCH Half Speech | |
261 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR, | |
262 D_GU_HR, D_GO_HR, D_B_HR, | |
263 D_SM_HR, D_ATTMAX_HR, | |
264 | |
265 //...................Added variables for EFR | |
266 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR, | |
267 C_GU_EFR, C_GO_EFR, C_B_EFR, | |
268 C_SM_EFR, C_ATTMAX_EFR, | |
269 | |
270 //...................Full rate variables | |
271 D_SD_MIN_THR_TCHFS, | |
272 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
273 | |
274 //...................TCH Half Speech | |
275 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS, | |
276 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, | |
277 | |
278 //...................TCH Enhanced Full Rate Speech | |
279 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS, | |
280 D_MD1_MAX_THR_TCHEFS, D_WED_FIL_INI, | |
281 | |
282 D_WED_FIL_TC, D_X_MIN, D_X_MAX, | |
283 D_SLOPE, D_Y_MIN, D_Y_MAX, | |
284 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, | |
285 | |
286 D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES, | |
287 D_M1_THRES, D_MAX_OVSP_DL, D_GSM_BGD_MGT | |
288 }; | |
289 param_size = 79; | |
290 | |
291 #if (OP_L1_STANDALONE) | |
292 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \ | |
293 (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15) | |
294 /* Dynamic clock configuration */ | |
295 param_tab[0] = p_dynamic_clock_cfg->d_transfer_rate; | |
296 param_tab[1] = p_dynamic_clock_cfg->d_lat_mcu_bridge; | |
297 param_tab[2] = p_dynamic_clock_cfg->d_lat_mcu_hom2sam; | |
298 param_tab[3] = p_dynamic_clock_cfg->d_lat_mcu_bef_fast_access; | |
299 param_tab[4] = p_dynamic_clock_cfg->d_lat_dsp_after_sam; | |
300 #endif | |
301 #endif | |
302 | |
303 #elif (DSP == 33) | |
304 static API_SIGNED param_tab[] = { | |
305 | |
306 D_TRANSFER_RATE, | |
307 | |
308 // ..................Latencies | |
309 D_LAT_MCU_BRIDGE, D_LAT_MCU_HOM2SAM, | |
310 | |
311 D_LAT_MCU_BEF_FAST_ACCESS, D_LAT_DSP_AFTER_SAM, | |
312 | |
313 //...................p_gprs_install_adress | |
314 D_HOLE, | |
315 | |
316 //...................d_misc_config | |
317 D_MISC_CONFIG, | |
318 | |
319 //...................d_cn_sw_workaround | |
320 C_DSP_SW_WORK_AROUND, | |
321 | |
322 #if DCO_ALGO | |
323 //...................d_cn_dco_param | |
324 C_CN_DCO_PARAM, | |
325 #else | |
326 //.................. Reserved | |
327 D_HOLE, | |
328 #endif | |
329 | |
330 //...................Reserved | |
331 D_HOLE, D_HOLE, | |
332 D_HOLE, | |
333 | |
334 //...................Frequency burst | |
335 D_FB_MARGIN_BEG, D_FB_MARGIN_END, | |
336 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
337 D_FB_THR_DET_TRACK, | |
338 //...................Demodulation | |
339 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
340 D_DEM_POND_RED, | |
341 //...................TCH Full Speech | |
342 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
343 D_GU, D_GO, D_ATTMAX, | |
344 D_SM, D_B, | |
345 | |
346 //...................V42 bis | |
347 D_V42B_SWITCH_HYST, D_V42B_SWITCH_MIN, D_V42B_SWITCH_MAX, | |
348 D_V42B_RESET_DELAY, | |
349 | |
350 //...................TCH Half Speech | |
351 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR, | |
352 D_GU_HR, D_GO_HR, D_B_HR, | |
353 D_SM_HR, D_ATTMAX_HR, | |
354 | |
355 //...................Added variables for EFR | |
356 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR, | |
357 C_GU_EFR, C_GO_EFR, C_B_EFR, | |
358 C_SM_EFR, C_ATTMAX_EFR, | |
359 | |
360 //...................Full rate variables | |
361 D_SD_MIN_THR_TCHFS, | |
362 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
363 | |
364 //...................TCH Half Speech | |
365 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS, | |
366 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, | |
367 | |
368 //...................TCH Enhanced Full Rate Speech | |
369 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS, | |
370 D_MD1_MAX_THR_TCHEFS, D_WED_FIL_INI, | |
371 | |
372 D_WED_FIL_TC, D_X_MIN, D_X_MAX, | |
373 D_SLOPE, D_Y_MIN, D_Y_MAX, | |
374 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, | |
375 | |
376 D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES, | |
377 D_M1_THRES, D_MAX_OVSP_DL, D_GSM_BGD_MGT | |
378 }; | |
379 param_size = 79; | |
380 | |
381 #if (OP_L1_STANDALONE) | |
382 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \ | |
383 (CHIPSET == 11) || (CHIPSET == 12) | |
384 /* Dynamic clock configuration */ | |
385 param_tab[0] = p_dynamic_clock_cfg->d_transfer_rate; | |
386 param_tab[1] = p_dynamic_clock_cfg->d_lat_mcu_bridge; | |
387 param_tab[2] = p_dynamic_clock_cfg->d_lat_mcu_hom2sam; | |
388 param_tab[3] = p_dynamic_clock_cfg->d_lat_mcu_bef_fast_access; | |
389 param_tab[4] = p_dynamic_clock_cfg->d_lat_dsp_after_sam; | |
390 #endif | |
391 #endif | |
392 | |
393 #else | |
394 | |
395 #if (VOC == FR) | |
396 static API_SIGNED param_tab[] = { | |
397 //...................Frequency burst | |
398 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
399 D_FB_THR_DET_TRACK, | |
400 //...................Demodulation | |
401 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
402 D_DEM_POND_RED, D_HOLE, D_HOLE, | |
403 //...................TCH Full Speech | |
404 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
405 D_GU, D_GO, D_ATTMAX, | |
406 D_SM, D_B, D_SD_MIN_THR_TCHFS, | |
407 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
408 //...................TCH Half Speech | |
409 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS, | |
410 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, D_WED_FIL_INI, | |
411 D_WED_FIL_TC, D_X_MIN, D_X_MAX, | |
412 D_SLOPE, D_Y_MIN, D_Y_MAX, | |
413 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, | |
414 D_DSP_TEST | |
415 }; | |
416 param_size = 38; | |
417 #endif | |
418 | |
419 #if (VOC == FR_HR) | |
420 static API_SIGNED param_tab[] = { | |
421 //...................Frequency burst | |
422 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
423 D_FB_THR_DET_TRACK, | |
424 //...................Demodulation | |
425 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
426 D_DEM_POND_RED, D_HOLE, D_HOLE, | |
427 //...................TCH Full Speech | |
428 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
429 D_GU, D_GO, D_ATTMAX, | |
430 D_SM, D_B, | |
431 //...................TCH Half Speech | |
432 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR, | |
433 D_GU_HR, D_GO_HR, D_B_HR, | |
434 D_SM_HR, D_ATTMAX_HR, | |
435 //...................TCH Full Speech | |
436 D_SD_MIN_THR_TCHFS, | |
437 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
438 //...................TCH Half Speech | |
439 D_SD_MIN_THR_TCHHS, | |
440 D_MA_MIN_THR_TCHHS, | |
441 D_SD_AV_THR_TCHHS, | |
442 D_MD_MAX_THR_TCHHS, | |
443 D_MD1_MAX_THR_TCHHS, | |
444 D_WED_FIL_INI, | |
445 D_WED_FIL_TC, | |
446 D_X_MIN, | |
447 D_X_MAX, | |
448 D_SLOPE, | |
449 D_Y_MIN, | |
450 D_Y_MAX, | |
451 D_WED_DIFF_THRESHOLD, | |
452 D_MABFI_MIN_THR_TCHHS, | |
453 D_FACCH_THR, | |
454 D_DSP_TEST | |
455 }; | |
456 param_size = 46; | |
457 #endif | |
458 | |
459 #if (VOC == FR_EFR) | |
460 static API_SIGNED param_tab[] = { | |
461 //...................Frequency burst | |
462 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
463 D_FB_THR_DET_TRACK, | |
464 //...................Demodulation | |
465 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
466 D_DEM_POND_RED, D_HOLE, D_HOLE, | |
467 | |
468 //...................TCH Full Speech | |
469 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
470 D_GU, D_GO, D_ATTMAX, | |
471 D_SM, D_B, | |
472 | |
473 //...................Added variables for EFR | |
474 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR, | |
475 C_GU_EFR, C_GO_EFR, C_B_EFR, | |
476 C_SM_EFR, C_ATTMAX_EFR, | |
477 | |
478 //...................Full rate variables | |
479 D_SD_MIN_THR_TCHFS, | |
480 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
481 | |
482 //...................TCH Enhanced Full Rate Speech | |
483 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS, | |
484 D_MD1_MAX_THR_TCHEFS, D_HOLE, D_WED_FIL_INI, | |
485 | |
486 D_WED_FIL_TC, D_X_MIN, D_X_MAX, | |
487 D_SLOPE, D_Y_MIN, D_Y_MAX, | |
488 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, | |
489 D_DSP_TEST | |
490 }; | |
491 param_size = 46; | |
492 #endif | |
493 | |
494 #if (VOC == FR_HR_EFR) | |
495 static API_SIGNED param_tab[] = { | |
496 //...................Frequency burst | |
497 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, | |
498 D_FB_THR_DET_TRACK, | |
499 //...................Demodulation | |
500 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, | |
501 D_DEM_POND_RED, D_HOLE, D_TRANSFER_RATE, | |
502 //...................TCH Full Speech | |
503 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, | |
504 D_GU, D_GO, D_ATTMAX, | |
505 D_SM, D_B, | |
506 | |
507 //...................TCH Half Speech | |
508 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR, | |
509 D_GU_HR, D_GO_HR, D_B_HR, | |
510 D_SM_HR, D_ATTMAX_HR, | |
511 | |
512 //...................Added variables for EFR | |
513 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR, | |
514 C_GU_EFR, C_GO_EFR, C_B_EFR, | |
515 C_SM_EFR, C_ATTMAX_EFR, | |
516 | |
517 //...................Full rate variables | |
518 D_SD_MIN_THR_TCHFS, | |
519 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, | |
520 | |
521 //...................TCH Half Speech | |
522 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS, | |
523 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, | |
524 | |
525 //...................TCH Enhanced Full Rate Speech | |
526 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS, | |
527 D_MD1_MAX_THR_TCHEFS, D_HOLE, D_WED_FIL_INI, | |
528 | |
529 D_WED_FIL_TC, D_X_MIN, D_X_MAX, | |
530 D_SLOPE, D_Y_MIN, D_Y_MAX, | |
531 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, | |
532 D_HOLE, | |
533 | |
534 //...................Data patch provisions | |
535 D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, D_HOLE, | |
536 | |
537 //...................Version Number, TI Number | |
538 D_HOLE, D_HOLE, | |
539 | |
540 // ..................DSP page | |
541 D_DSP_TEST | |
542 | |
543 #if IDS | |
544 ,D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES, | |
545 D_M1_THRES, D_MAX_OVSP_DL | |
546 #endif | |
547 | |
548 }; | |
549 param_size = 67; | |
550 #if IDS | |
551 // Take care to not erased "d_version_number, d_ti_version and d_dsp_page" wrote by DSP before ARM | |
552 // set PARAM memory | |
553 param_size2 = 5; | |
554 #endif | |
555 #endif | |
556 #endif // (end of DSP != 33 || DSP != 34 || DSP != 35 || DSP != 36) || (DSP != 37) || (DSP != 38) || (DSP != 39) | |
557 | |
558 // NDB pointer. | |
559 dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR; | |
560 | |
561 | |
562 //------------- | |
563 // DSP STARTUP | |
564 //------------- | |
565 { | |
566 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) | |
567 #if (CHIPSET == 1) | |
568 L1_trace_string ("\n\r\n\rGEMINI/POLESTAR test code\n\r-------------------------"); | |
569 #elif (CHIPSET == 2) | |
570 L1_trace_string ("\n\r\n\rHERCULES test code\n\r------------------"); | |
571 #elif (CHIPSET == 3) | |
572 L1_trace_string ("\n\r\n\rULYSSE/ULYSSE G0 test code\n\r--------------------------"); | |
573 #elif (CHIPSET == 4) | |
574 L1_trace_string ("\n\r\n\rSAMSON test code\n\r----------------"); | |
575 #elif (CHIPSET == 5) | |
576 L1_trace_string ("\n\r\n\rULYSSE G1 test code 13 MHz\n\r-------------------"); | |
577 #elif (CHIPSET == 6) | |
578 L1_trace_string ("\n\r\n\rULYSSE G1 test code 26 MHz\n\r-------------------"); | |
579 #elif (CHIPSET == 7) | |
580 L1_trace_string ("\n\r\n\rCALYPSO Rev A test code\n\r-------------------"); | |
581 #elif (CHIPSET == 8) | |
582 L1_trace_string ("\n\r\n\rCALYPSO Rev B test code\n\r-------------------"); | |
583 #elif (CHIPSET == 9) | |
584 L1_trace_string ("\n\r\n\rULYSSE C035 test code\n\r-------------------"); | |
585 #elif (CHIPSET == 10) || (CHIPSET == 11) | |
586 L1_trace_string ("\n\r\n\rCALYPSO C035 test code\n\r-------------------"); | |
587 #elif (CHIPSET == 12) | |
588 L1_trace_string ("\n\r\n\rCALYPSO PLUS test code\n\r-------------------"); | |
589 #elif (CHIPSET == 15) | |
590 L1_trace_string ("\n\r\n\rLOCOSTO test code\n\r-------------------"); | |
591 #endif | |
592 #endif | |
593 | |
594 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) | |
595 /* Display Audio Configuration */ | |
596 L1_trace_string ("\n\rAUDIO: "); | |
597 #if (KEYBEEP) | |
598 L1_trace_string ("KB "); | |
599 #endif | |
600 #if (TONE) | |
601 L1_trace_string ("TN "); | |
602 #endif | |
603 #if (MELODY_E1) | |
604 L1_trace_string ("E1 "); | |
605 #endif | |
606 #if (MELODY_E2) | |
607 L1_trace_string ("E2 "); | |
608 #endif | |
609 #if (VOICE_MEMO) | |
610 L1_trace_string ("VM "); | |
611 #endif | |
612 #if (L1_VOICE_MEMO_AMR) | |
613 L1_trace_string ("VMA "); | |
614 #endif | |
615 #if (SPEECH_RECO) | |
616 L1_trace_string ("SR "); | |
617 #endif | |
618 #if (L1_NEW_AEC) | |
619 L1_trace_string ("NEWAEC "); | |
620 #elif (AEC) | |
621 L1_trace_string ("AEC "); | |
622 #endif | |
623 #if (L1_GTT) | |
624 L1_trace_string ("GTT "); | |
625 #endif | |
626 #if (FIR) | |
627 L1_trace_string ("FIR "); | |
628 #endif | |
629 #if (AUDIO_MODE) | |
630 L1_trace_string ("AUM "); | |
631 #endif | |
632 #if (L1_CPORT == 1) | |
633 L1_trace_string ("CPO "); | |
634 #endif | |
635 #if (L1_STEREOPATH == 1) | |
636 L1_trace_string ("STP "); | |
637 #endif | |
638 #if (L1_EXT_AUDIO_MGT == 1) | |
639 L1_trace_string ("EAM "); | |
640 #endif | |
641 L1_trace_string ("\n\r"); | |
642 #endif | |
643 // Release Lead reset before DSP code/patch download to insure proper reset of DSP | |
644 LA_ReleaseLead(); | |
645 | |
646 // Init PLL : PLONOFF =1, PLMU = 0010 (k=3), PLLNDIV=1, PLLDIV=0 | |
647 LA_InitialLeadBoot(bootCode); // Load the bootCode in API | |
648 LA_StartLead(CLKSTART); // LEAD_PLL_CNTL register (on MCU side) | |
649 // On SAMSON, only the LEAD reset is released | |
650 | |
651 // GSM 1.5 | |
652 //----------------------------------------------------------------- | |
653 // After RESET release, DSP is in SAM Mode ! while API_CNTR (0xF900) | |
654 // register is in reset state: HOM mode, PLL off, Bridge off. No ws | |
655 // are applied for MCU<-->API access !!!!! So, MCU must wait for | |
656 // end of Leadboot execution before accessing API. | |
657 wait_ARM_cycles(convert_nanosec_to_cycles(10000)); // wait 10us | |
658 | |
659 | |
660 if(l1_config.dwnld == NO_DWNLD) | |
661 // NO DOWNLOAD... | |
662 { | |
663 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) | |
664 L1_trace_string ("\n\r-> No download !!"); | |
665 #endif | |
666 | |
667 // Wait for READY status from DSP. | |
668 while(*((volatile UWORD16 *)DOWNLOAD_STATUS) != LEAD_READY); | |
669 | |
670 // Set DSP start address. | |
671 dsp_start_address = DSP_START; | |
672 } | |
673 else | |
674 if(l1_config.dwnld == DSP_DWNLD) | |
675 // DSP CODE DOWNLOAD... | |
676 { | |
677 WORD32 load_result; | |
678 | |
679 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
680 #if (VOC == FR) | |
681 L1_trace_string ("\n\r-> Downloading FR DSP code..."); | |
682 #endif | |
683 | |
684 #if (VOC == FR_HR) | |
685 L1_trace_string ("\n\r-> Downloading FR&HR DSP code..."); | |
686 #endif | |
687 | |
688 #if (VOC == FR_EFR) | |
689 L1_trace_string ("\n\r-> Downloading FR&EFR DSP code..."); | |
690 #endif | |
691 | |
692 #if (VOC == FR_HR_EFR) | |
693 #if IDS | |
694 L1_trace_string ("\n\r-> Download FR&IDS DSP code..."); | |
695 #else | |
696 L1_trace_string ("\n\r-> Downloading 3VOC DSP code..."); | |
697 #endif | |
698 #endif | |
699 #endif | |
700 | |
701 // Download DSP code into DSP via API / bootcode. | |
702 load_result = LA_LoadPage(DspCode_array,0,0); | |
703 | |
704 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
705 if(load_result) | |
706 L1_trace_string ("\n\r-> Download FAILED !!"); | |
707 else | |
708 L1_trace_string ("\n\r-> ... finished !!"); | |
709 #endif | |
710 | |
711 #if (VOC == FR_HR) || (VOC == FR_EFR) || (VOC == FR_HR_EFR) | |
712 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
713 #if (VOC == FR_HR) | |
714 L1_trace_string ("\n\r-> Downloading FR&HR DSP data ROM..."); | |
715 #endif | |
716 | |
717 #if (VOC == FR_EFR) | |
718 L1_trace_string ("\n\r-> Downloading FR&EFR DSP data ROM..."); | |
719 #endif | |
720 | |
721 #if (VOC == FR_HR_EFR) | |
722 #if IDS | |
723 L1_trace_string ("\n\r-> Download FR&IDS DSP Data ROM..."); | |
724 #else | |
725 L1_trace_string ("\n\r-> Downloading 3VOC DSP DATA ROM..."); | |
726 #endif | |
727 #endif | |
728 #endif | |
729 | |
730 load_result = LA_LoadPage(DspData_array,1,0); | |
731 | |
732 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
733 if(load_result) | |
734 L1_trace_string ("\n\r-> Download FAILED !!"); | |
735 else | |
736 L1_trace_string ("\n\r-> ... finished !!"); | |
737 #endif | |
738 #endif | |
739 | |
740 // Set DSP start address; | |
741 dsp_start_address = DSP_START; | |
742 } | |
743 else | |
744 if(l1_config.dwnld == PATCH_DWNLD) | |
745 // DSP PATCH DOWNLOAD... | |
746 { | |
747 WORD32 load_result; | |
748 | |
749 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
750 L1_trace_string ("\n\r-> Downloading patch..."); | |
751 #endif | |
752 | |
753 // Download DSP patch into DSP via API / bootcode. | |
754 load_result = LA_LoadPage(patch_array,0,0); | |
755 | |
756 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
757 if(load_result) | |
758 L1_trace_string ("\n\r-> Download FAILED !!"); | |
759 else | |
760 L1_trace_string ("\n\r-> ... finished !!"); | |
761 #endif | |
762 | |
763 // Catch start address always from patch_file#.c. | |
764 dsp_start_address = (WORD16)patch_array[3]; | |
765 dsp_start_address <<= 8; | |
766 dsp_start_address += (WORD16)patch_array[2]; | |
767 | |
768 // if COFF2CP output, the file begins by a null tag | |
769 if(dsp_start_address == 0) | |
770 { | |
771 dsp_start_address = (WORD16)patch_array[13]; | |
772 dsp_start_address <<= 8; | |
773 dsp_start_address += (WORD16)patch_array[12]; | |
774 } | |
775 } | |
776 else | |
777 if(l1_config.dwnld == PATCH_DSP_DWNLD) | |
778 // DSP CODE DOWNLOAD + PATCH DOWNLOAD... | |
779 { | |
780 WORD32 load_result; | |
781 | |
782 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
783 #if (VOC == FR) | |
784 L1_trace_string ("\n\r-> Downloading FR DSP code..."); | |
785 #endif | |
786 | |
787 #if (VOC == FR_HR) | |
788 L1_trace_string ("\n\r-> Downloading FR&HR DSP code..."); | |
789 #endif | |
790 | |
791 #if (VOC == FR_EFR) | |
792 L1_trace_string ("\n\r-> Downloading FR&EFR DSP code..."); | |
793 #endif | |
794 | |
795 #if (VOC == FR_HR_EFR) | |
796 #if IDS | |
797 L1_trace_string ("\n\r-> Download FR&IDS DSP code..."); | |
798 #else | |
799 L1_trace_string ("\n\r-> Downloading 3VOC DSP code..."); | |
800 #endif | |
801 #endif | |
802 #endif | |
803 | |
804 // Download DSP code into DSP via API / bootcode. | |
805 load_result = LA_LoadPage(DspCode_array,0,0); | |
806 | |
807 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
808 if(load_result) | |
809 L1_trace_string ("\n\r-> Download FAILED !!"); | |
810 else | |
811 L1_trace_string ("\n\r-> ... finished !!"); | |
812 #endif | |
813 | |
814 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
815 L1_trace_string ("\n\r-> Downloading patch..."); | |
816 #endif | |
817 | |
818 // Download DSP patch into DSP via API / bootcode. | |
819 load_result = LA_LoadPage(patch_array,0,0); | |
820 | |
821 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
822 if(load_result) | |
823 L1_trace_string ("\n\r-> Download FAILED !!"); | |
824 else | |
825 L1_trace_string ("\n\r-> ... finished !!"); | |
826 #endif | |
827 | |
828 #if ((VOC == FR_HR) || (VOC == FR_EFR) || (VOC == FR_HR_EFR)) | |
829 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
830 #if (VOC == FR_HR) | |
831 L1_trace_string ("\n\r-> Downloading FR&HR DSP data ROM..."); | |
832 #endif | |
833 | |
834 #if (VOC == FR_EFR) | |
835 L1_trace_string ("\n\r-> Downloading FR&EFR DSP data ROM..."); | |
836 #endif | |
837 | |
838 #if (VOC == FR_HR_EFR) | |
839 #if IDS | |
840 L1_trace_string ("\n\r-> Download FR&IDS DSP data ROM..."); | |
841 #else | |
842 L1_trace_string ("\n\r-> Downloading 3VOC DSP data ROM..."); | |
843 #endif | |
844 #endif | |
845 #endif | |
846 | |
847 load_result = LA_LoadPage(DspData_array,1,0); | |
848 | |
849 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE == 7) | |
850 if(load_result) | |
851 L1_trace_string ("\n\r-> Download FAILED !!"); | |
852 else | |
853 L1_trace_string ("\n\r-> ... finished !!"); | |
854 #endif | |
855 #endif | |
856 | |
857 | |
858 // Catch start address always from patch_file#.c. | |
859 dsp_start_address = (WORD16)patch_array[3]; | |
860 dsp_start_address <<= 8; | |
861 dsp_start_address += (WORD16)patch_array[2]; | |
862 | |
863 // if COFF2CP output, the file begins by a null tag | |
864 if(dsp_start_address == 0) | |
865 { | |
866 dsp_start_address = (WORD16)patch_array[13]; | |
867 dsp_start_address <<= 8; | |
868 dsp_start_address += (WORD16)patch_array[12]; | |
869 } | |
870 } | |
871 | |
872 #if (DSP == 16 || DSP == 17 || DSP == 30 || DSP == 31 || DSP == 32) | |
873 dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1; // PLL variable (multiply by 3 factor)+ Power consumpt. | |
874 dsp_ndb_ptr->d_pll_clkmod2 = CLKMOD2; // PLL variable (40 us lock time) | |
875 #endif | |
876 } | |
877 | |
878 #if (TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==7) | |
879 L1_trace_string ("\n\r\n\r"); | |
880 #endif | |
881 | |
882 //-------------------------------------------------------------- | |
883 // Loading of NDB parameters....... | |
884 //-------------------------------------------------------------- | |
885 | |
886 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
887 // Initialize background control variable to No background. Background tasks can be launch in GPRS | |
888 // as in GSM. | |
889 dsp_ndb_ptr->d_background_enable = 0; | |
890 dsp_ndb_ptr->d_background_abort = 0; | |
891 dsp_ndb_ptr->d_background_state = 0; | |
892 dsp_ndb_ptr->d_debug_ptr = 0x0074; | |
893 dsp_ndb_ptr->d_debug_bk = 0x0001; | |
894 dsp_ndb_ptr->d_pll_config = C_PLL_CONFIG; | |
895 dsp_ndb_ptr->p_debug_buffer = C_DEBUG_BUFFER_ADD; | |
896 dsp_ndb_ptr->d_debug_buffer_size = C_DEBUG_BUFFER_SIZE; | |
897 dsp_ndb_ptr->d_debug_trace_type = C_DEBUG_TRACE_TYPE; | |
898 | |
899 | |
900 #if (CHIPSET == 12) || (CHIPSET == 15) | |
901 dsp_ndb_ptr->d_swh_flag_ndb = 0; /* interpolation off for non SAIC build*/ | |
902 dsp_ndb_ptr->d_swh_Clipping_Threshold_ndb = 0x0000; | |
903 #if (DSP == 36) || (DSP == 37) || (DSP == 39) | |
904 #if (L1_SAIC != 0) | |
905 dsp_ndb_ptr->d_swh_flag_ndb = SAIC_INITIAL_VALUE; | |
906 dsp_ndb_ptr->d_swh_Clipping_Threshold_ndb = 0x4000; | |
907 #endif | |
908 #endif | |
909 #endif | |
910 | |
911 #if (W_A_DSP_IDLE3 == 1) | |
912 // Deep Sleep work around used on Calypso | |
913 // This init is used to backward compatibility with old patch. | |
914 dsp_ndb_ptr->d_dsp_state = C_DSP_IDLE3; | |
915 #endif | |
916 | |
917 dsp_ndb_ptr->d_audio_gain_ul = 0; | |
918 dsp_ndb_ptr->d_audio_gain_dl = 0; | |
919 | |
920 // for patch >= 2100, use new AEC | |
921 #if (!L1_NEW_AEC) | |
922 dsp_ndb_ptr->d_es_level_api = 0x5213; | |
923 #endif | |
924 dsp_ndb_ptr->d_mu_api = 0x5000; | |
925 #else | |
926 #if L1_GPRS | |
927 { | |
928 T_NDB_MCU_DSP_GPRS *p_ndb_gprs = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS; | |
929 | |
930 // Initialize background control variable to No background. | |
931 p_ndb_gprs->d_background_enable = 0; | |
932 p_ndb_gprs->d_background_abort = 0; | |
933 p_ndb_gprs->d_background_state = 0; | |
934 } | |
935 #endif | |
936 | |
937 #if (AMR == 1) | |
938 // Reset NDB pointer for AMR trace | |
939 dsp_ndb_ptr->p_debug_amr = 0; | |
940 #endif | |
941 | |
942 #endif | |
943 | |
944 //-------------------------------------------------------------- | |
945 // Loading of PARAM area....... | |
946 //-------------------------------------------------------------- | |
947 // Load PARAM memory... | |
948 pt = (API *) PARAM_ADR; | |
949 | |
950 for (i=0; i<param_size; i++) *pt++ = param_tab[i]; | |
951 #if (DSP < 33) && (IDS) | |
952 pt += 3; | |
953 for (i= param_size + 3; i<param_size + 3 + param_size2; i++) *pt++ = param_tab[i]; | |
954 #endif | |
955 | |
956 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
957 { | |
958 T_PARAM_MCU_DSP *pt_param = (T_PARAM_MCU_DSP *) PARAM_ADR; | |
959 | |
960 // "d_gprs_install_address" has to be set only if no PATCH is download, i.e. | |
961 // "d_gprs_install_address" is automatically set by DSP if a PATCH is download | |
962 if ((l1_config.dwnld == DSP_DWNLD) || (l1_config.dwnld == NO_DWNLD)) | |
963 pt_param->d_gprs_install_address = INSTALL_ADD; | |
964 } | |
965 #endif | |
966 | |
967 #if L1_GPRS | |
968 //-------------------------------------------------------------- | |
969 // Loading of GPRS PARAM area....... | |
970 //-------------------------------------------------------------- | |
971 // Load GPRS PARAM memory... | |
972 { | |
973 T_PARAM_MCU_DSP_GPRS *pt_gprs = (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS; | |
974 | |
975 // WARNING: must be configured according to the ARM & DSP clock speed. | |
976 // The following values are required with a 13MHz ARM clock and with a 65 MIPS DSP. | |
977 pt_gprs->d_overlay_rlcmac_cfg_gprs = 0; | |
978 pt_gprs->d_mac_threshold = 0x4e20; | |
979 pt_gprs->d_sd_threshold = 0x0016; | |
980 pt_gprs->d_nb_max_iteration = 0x0004; | |
981 | |
982 #if (DSP != 33) && (DSP != 34) && (DSP != 35) && (DSP != 36) && (DSP != 37) && (DSP != 38) && (DSP != 39) | |
983 | |
984 #if (OP_L1_STANDALONE) | |
985 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || \ | |
986 (CHIPSET == 11) || (CHIPSET == 12) | |
987 pt_gprs->d_lat_mcu_bridge = p_dynamic_clock_cfg->d_lat_mcu_bridge; | |
988 pt_gprs->d_lat_mcu_hom2sam = p_dynamic_clock_cfg->d_lat_mcu_hom2sam; | |
989 #endif | |
990 #endif | |
991 | |
992 #if (CHIPSET == 4) | |
993 #if (!OP_L1_STANDALONE) | |
994 // Latency for DSP at 78 MIPS | |
995 pt_gprs->d_lat_mcu_bridge = 0x0009; | |
996 #endif | |
997 pt_gprs->d_lat_pll2div = 0x000C; | |
998 #if (!OP_L1_STANDALONE) | |
999 pt_gprs->d_lat_mcu_hom2sam = 0x000C; | |
1000 #endif | |
1001 #else | |
1002 #if (!OP_L1_STANDALONE) | |
1003 pt_gprs->d_lat_mcu_bridge = 0x0008; | |
1004 #endif | |
1005 pt_gprs->d_lat_pll2div = 0x000A; | |
1006 #if (!OP_L1_STANDALONE) | |
1007 pt_gprs->d_lat_mcu_hom2sam = 0x000A; | |
1008 #endif | |
1009 #endif | |
1010 | |
1011 // To be removed once G0 patch process will be aligned with G1 & G2 | |
1012 // i.e. "d_gprs_install_address" automatically set by DSP if a Patch is present. | |
1013 #if (DSP == 31) | |
1014 if ((l1_config.dwnld == PATCH_DSP_DWNLD) || | |
1015 (l1_config.dwnld == PATCH_DWNLD)) | |
1016 pt_gprs->d_gprs_install_address = INSTALL_ADD_WITH_PATCH; | |
1017 else | |
1018 pt_gprs->d_gprs_install_address = INSTALL_ADD; | |
1019 #else | |
1020 if ((l1_config.dwnld == DSP_DWNLD) || (l1_config.dwnld == NO_DWNLD)) | |
1021 pt_gprs->d_gprs_install_address = INSTALL_ADD; | |
1022 #endif | |
1023 #endif // DSP != 33 && DSP != 34 && (DSP != 35) && DSP != 36 && DSP != 37 && DSP != 38 | |
1024 } | |
1025 #endif // L1_GPRS | |
1026 | |
1027 *(volatile UWORD16 *) DOWNLOAD_SIZE = 0; // Size=0 to force DSP to start from address... | |
1028 *(volatile UWORD16 *) DOWNLOAD_ADDR = dsp_start_address; // Start address. | |
1029 *(volatile UWORD16 *) DOWNLOAD_STATUS = BLOCK_READY; // Start DSP... | |
1030 | |
1031 } | |
1032 #endif //#if CODE_VERSION!=SIMULATION | |
1033 | |
1034 /*-------------------------------------------------------*/ | |
1035 /* l1s_reset_db_mcu_to_dsp() */ | |
1036 /*-------------------------------------------------------*/ | |
1037 /* Parameters : */ | |
1038 /* Return : */ | |
1039 /* Functionality : */ | |
1040 /*-------------------------------------------------------*/ | |
1041 void l1s_reset_db_mcu_to_dsp(T_DB_MCU_TO_DSP *page_ptr) | |
1042 { | |
1043 API i; | |
1044 API size = sizeof(T_DB_MCU_TO_DSP) / sizeof(API); | |
1045 API *ptr = (API *)page_ptr; | |
1046 | |
1047 // Clear all locations. | |
1048 for(i=0; i<size; i++) *ptr++ = 0; | |
1049 } | |
1050 | |
1051 #if (DSP == 38) || (DSP == 39) | |
1052 /*-------------------------------------------------------*/ | |
1053 /* l1s_reset_db_common_mcu_to_dsp() */ | |
1054 /*-------------------------------------------------------*/ | |
1055 /* Parameters : */ | |
1056 /* Return : */ | |
1057 /* Functionality : */ | |
1058 /*-------------------------------------------------------*/ | |
1059 void l1s_reset_db_common_mcu_to_dsp(T_DB_COMMON_MCU_TO_DSP *page_ptr) | |
1060 { | |
1061 API i; | |
1062 API size = sizeof(T_DB_COMMON_MCU_TO_DSP) / sizeof(API); | |
1063 API *ptr = (API *)page_ptr; | |
1064 | |
1065 // Clear all locations. | |
1066 for(i=0; i<size; i++) *ptr++ = 0; | |
1067 } | |
1068 #endif | |
1069 /*-------------------------------------------------------*/ | |
1070 /* l1s_reset_db_dsp_to_mcu() */ | |
1071 /*-------------------------------------------------------*/ | |
1072 /* Parameters : */ | |
1073 /* Return : */ | |
1074 /* Functionality : */ | |
1075 /*-------------------------------------------------------*/ | |
1076 void l1s_reset_db_dsp_to_mcu(T_DB_DSP_TO_MCU *page_ptr) | |
1077 { | |
1078 API i; | |
1079 API size = sizeof(T_DB_DSP_TO_MCU) / sizeof(API); | |
1080 API *ptr = (API *)page_ptr; | |
1081 | |
1082 // Clear all locations. | |
1083 for(i=0; i<size; i++) *ptr++ = 0; | |
1084 | |
1085 // Set crc result as "SB not found". | |
1086 page_ptr->a_sch[0] = (1<<B_SCH_CRC); // B_SCH_CRC =1, BLUD =0 | |
1087 } | |
1088 | |
1089 /*-------------------------------------------------------*/ | |
1090 /* l1s_increment_time() */ | |
1091 /*-------------------------------------------------------*/ | |
1092 /* Parameters : */ | |
1093 /* Return : */ | |
1094 /* Functionality : */ | |
1095 /*-------------------------------------------------------*/ | |
1096 void l1s_increment_time(T_TIME_INFO *time, UWORD32 fn_offset) | |
1097 { | |
1098 // Increment FN % MAX_FN. | |
1099 //------------------------ | |
1100 IncMod(time->fn, fn_offset, MAX_FN); | |
1101 | |
1102 if(fn_offset == 1) | |
1103 // Frame by frame increment... | |
1104 //---------------------------- | |
1105 { | |
1106 IncMod(time->t2, 1, 26); // increment T2 % 26. | |
1107 IncMod(time->t3, 1, 51); // increment T3 % 51. | |
1108 IncMod(time->fn_mod42432, 1, 42432); // increment FN % 42432. | |
1109 IncMod(time->fn_mod13, 1, 13); // increment FN % 13. | |
1110 IncMod(time->fn_mod13_mod4, 1, 4); // increment (FN % 13) % 4. | |
1111 if(time->fn_mod13 == 0) | |
1112 time->fn_mod13_mod4 = 0; | |
1113 | |
1114 if(time->t3 == 0) | |
1115 // new FN is a multiple of 51. | |
1116 { | |
1117 // Increment TC ((FN/51) % 8). | |
1118 IncMod(time->tc, 1, 8); | |
1119 | |
1120 // New FN is a multiple of 26 and 51 -> increment T1 % 2048 (T1=FN div (26*51)). | |
1121 if(time->t2 == 0) IncMod(time->t1, 1, 2048); | |
1122 } | |
1123 | |
1124 #if (L1_GPRS) | |
1125 IncMod(time->fn_mod52, 1, 52); // increment FN % 52. | |
1126 IncMod(time->fn_mod104, 1, 104); // increment FN % 104. | |
1127 | |
1128 if((time->fn_mod13 == 0) || (time->fn_mod13 == 4) || (time->fn_mod13 == 8)) | |
1129 IncMod(time->block_id, 1, MAX_BLOCK_ID); | |
1130 #endif | |
1131 | |
1132 } | |
1133 | |
1134 else | |
1135 // Jumping on a new serving cell. | |
1136 //------------------------------- | |
1137 { | |
1138 time->t2 = time->fn % 26; // T2 = FN % 26. | |
1139 time->t3 = time->fn % 51; // T3 = FN % 51. | |
1140 time->t1 = time->fn / (26L*51L); // T1 = FN div 26*51 | |
1141 time->tc = (time->fn / 51) % 8; // TC = (FN div 51) % 8 | |
1142 time->fn_mod42432 = time->fn % 42432; // FN%42432. | |
1143 time->fn_mod13 = time->fn % 13; // FN % 13. | |
1144 time->fn_mod13_mod4 = time->fn_mod13 % 4; // FN % 13 % 4. | |
1145 | |
1146 #if (L1_GPRS) | |
1147 time->fn_mod104 = time->fn % 104; // FN % 104. | |
1148 | |
1149 if(time->fn_mod104 >= 52) // FN % 52. | |
1150 time->fn_mod52 = time->fn_mod104 - 52; | |
1151 else | |
1152 time->fn_mod52 = time->fn_mod104; | |
1153 | |
1154 time->block_id = ((3 * (time->fn / 13)) + (time->fn_mod13 / 4)); | |
1155 #endif | |
1156 | |
1157 } | |
1158 | |
1159 // Computes reporting period frame number according to the current FN | |
1160 if(l1a_l1s_com.l1s_en_task[DEDIC] == TASK_ENABLED) | |
1161 { | |
1162 T_CHANNEL_DESCRIPTION *desc_ptr; | |
1163 UWORD8 timeslot_no; | |
1164 UWORD8 subchannel; | |
1165 | |
1166 // Get a meaningfull channel description. | |
1167 //--------------------------------------- | |
1168 // Rem1: this is to avoid a bad setting of "fn_in_report" when synchro is performed | |
1169 // whereas L1 is waiting for starting time and no channel discribed BEFORE STI. | |
1170 // Rem2: "fn_in_report" is computed with "CHAN1" parameters since it is the channel | |
1171 // which carries the SACCH. | |
1172 if(l1a_l1s_com.dedic_set.aset->chan1.desc_ptr->channel_type == INVALID_CHANNEL) | |
1173 desc_ptr = &l1a_l1s_com.dedic_set.aset->chan1.desc; | |
1174 else | |
1175 desc_ptr = l1a_l1s_com.dedic_set.aset->chan1.desc_ptr; | |
1176 | |
1177 timeslot_no = desc_ptr->timeslot_no; | |
1178 subchannel = desc_ptr->subchannel; | |
1179 if(desc_ptr->channel_type == TCH_H) timeslot_no = (2*(timeslot_no/2) + subchannel); | |
1180 | |
1181 | |
1182 // Compute "fn_in_report" according to the channel_type. | |
1183 //------------------------------------------------------ | |
1184 if(desc_ptr->channel_type == SDCCH_4) | |
1185 // FN_REPORT for SDCCH/4 is: fn%102 in [37..36]. | |
1186 { | |
1187 l1s.actual_time.fn_in_report = (UWORD8)((l1s.actual_time.fn - 37 + 102) % 102); | |
1188 l1s.next_time.fn_in_report = (UWORD8)((l1s.next_time.fn - 37 + 102) % 102); | |
1189 } | |
1190 else | |
1191 if(desc_ptr->channel_type == SDCCH_8) | |
1192 // FN_REPORT for SDCCH/4 is: fn%102 in [12..11]. | |
1193 { | |
1194 l1s.actual_time.fn_in_report = (UWORD8)((l1s.actual_time.fn - 12 + 102) % 102); | |
1195 l1s.next_time.fn_in_report = (UWORD8)((l1s.next_time.fn - 12 + 102) % 102); | |
1196 } | |
1197 else | |
1198 // TCH_F or TCH_H... | |
1199 { | |
1200 // 1) (timeslot_no * 13) is computed in order to substract the considered beginning for this | |
1201 // timeslot and then always be in the range 0..103 | |
1202 // 2) 104 is added in order to cope with negative numbers. | |
1203 l1s.actual_time.fn_in_report = (UWORD8)((l1s.actual_time.fn - (timeslot_no * 13) + 104) % 104); | |
1204 l1s.next_time.fn_in_report = (UWORD8)((l1s.next_time.fn - (timeslot_no * 13) + 104) % 104); | |
1205 } | |
1206 } | |
1207 } | |
1208 | |
1209 /*-------------------------------------------------------*/ | |
1210 /* l1s_encode_rxlev() */ | |
1211 /*-------------------------------------------------------*/ | |
1212 /* Parameters : */ | |
1213 /* Return : */ | |
1214 /* Functionality : */ | |
1215 /*-------------------------------------------------------*/ | |
1216 WORD16 l1s_encode_rxlev(UWORD8 inlevel) | |
1217 { | |
1218 WORD16 rxlev; | |
1219 | |
1220 rxlev = (221 - inlevel) / 2; // the result is divided by 2 due to | |
1221 // the IL format is 7.1 and rxlev format is 8.0 | |
1222 | |
1223 return(rxlev); | |
1224 } | |
1225 | |
1226 /*-------------------------------------------------------*/ | |
1227 /* l1s_send_ho_finished() */ | |
1228 /*-------------------------------------------------------*/ | |
1229 /* Parameters : */ | |
1230 /* Return : */ | |
1231 /* Functionality : */ | |
1232 /*-------------------------------------------------------*/ | |
1233 void l1s_send_ho_finished(UWORD8 cause) | |
1234 { | |
1235 xSignalHeaderRec *msg; | |
1236 | |
1237 msg = os_alloc_sig(sizeof(T_MPHC_HANDOVER_FINISHED)); | |
1238 DEBUGMSG(status,NU_ALLOC_ERR) | |
1239 msg->SignalCode = L1C_HANDOVER_FINISHED; | |
1240 ((T_MPHC_HANDOVER_FINISHED *)(msg->SigP))->cause = cause; | |
1241 | |
1242 os_send_sig(msg, L1C1_QUEUE); | |
1243 DEBUGMSG(status,NU_SEND_QUEUE_ERR) | |
1244 } | |
1245 | |
1246 | |
1247 /*-------------------------------------------------------*/ | |
1248 /* l1s_get_versions() */ | |
1249 /*-------------------------------------------------------*/ | |
1250 /* Parameters : */ | |
1251 /* Return : */ | |
1252 /* Functionality : return address of version structur */ | |
1253 /*-------------------------------------------------------*/ | |
1254 T_VERSION *l1s_get_version (void) | |
1255 { | |
1256 //update the fields not initialized by the sw init. | |
1257 | |
1258 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) | |
1259 l1s.version.dsp_code_version = l1s_dsp_com.dsp_ndb_ptr->d_version_number1; | |
1260 l1s.version.dsp_patch_version = l1s_dsp_com.dsp_ndb_ptr->d_version_number2; | |
1261 // Note: if l1s.version.dsp_checksum is not initialized (field set to 0) | |
1262 // use TST_TEST_HW_REQ message to initialize the whole structur. | |
1263 #else | |
1264 l1s.version.dsp_patch_version = l1s_dsp_com.dsp_param_ptr->d_version_number; | |
1265 // Note: if l1s.version.dsp_code_version and l1s.version.dsp_checksum | |
1266 // are not initialized (fields set to 0) | |
1267 // use TST_TEST_HW_REQ message to initialize the whole structur. | |
1268 #endif | |
1269 | |
1270 return (&l1s.version); | |
1271 } | |
1272 | |
1273 /*-------------------------------------------------------*/ | |
1274 /* l1s_reset_dedic_meas() */ | |
1275 /*-------------------------------------------------------*/ | |
1276 /* Parameters : */ | |
1277 /* Return : */ | |
1278 /* Functionality : */ | |
1279 /*-------------------------------------------------------*/ | |
1280 void l1s_reset_dedic_serving_meas(void) | |
1281 { | |
1282 // Reset rxlev related fields | |
1283 l1a_l1s_com.Scell_info.meas.acc = 0; | |
1284 l1a_l1s_com.Scell_info.meas.nbr_meas = 0; | |
1285 l1a_l1s_com.Smeas_dedic.acc_sub = 0; | |
1286 l1a_l1s_com.Smeas_dedic.nbr_meas_sub = 0; | |
1287 | |
1288 // Reset rxqual related fields | |
1289 l1a_l1s_com.Smeas_dedic.qual_acc_full = 0; | |
1290 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_full = 0; | |
1291 l1a_l1s_com.Smeas_dedic.qual_acc_sub = 0; | |
1292 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_sub = 0; | |
1293 | |
1294 | |
1295 #if REL99 | |
1296 #if FF_EMR | |
1297 // Reset EMR variables | |
1298 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_acc = 0; | |
1299 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_nbr_meas = 0; | |
1300 l1a_l1s_com.Smeas_dedic_emr.nbr_rcvd_blocks = 0; | |
1301 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_acc = 0; | |
1302 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_acc = 0; | |
1303 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_num = 0; | |
1304 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_num = 0; | |
1305 #endif | |
1306 #endif | |
1307 | |
1308 | |
1309 // Reset dtx frame counter | |
1310 l1a_l1s_com.Smeas_dedic.dtx_used = 0; | |
1311 } | |
1312 | |
1313 /*-------------------------------------------------------*/ | |
1314 /* SwapIQ_dl() */ | |
1315 /*-------------------------------------------------------*/ | |
1316 /* Parameters : */ | |
1317 /* Return : */ | |
1318 /* Functionality : */ | |
1319 /*-------------------------------------------------------*/ | |
1320 UWORD32 l1s_swap_iq_dl(UWORD16 radio_freq, UWORD8 task) | |
1321 { | |
1322 UWORD8 swap_iq; | |
1323 UWORD32 task_tab= 0; //omaps00090550 | |
1324 | |
1325 #if (L1_FF_MULTIBAND == 0) | |
1326 if(((l1_config.std.id == DUAL) || (l1_config.std.id == DUALEXT) || (l1_config.std.id == DUAL_US)) && | |
1327 (radio_freq >= l1_config.std.first_radio_freq_band2)) | |
1328 { | |
1329 swap_iq = l1_config.std.swap_iq_band2; | |
1330 } | |
1331 else | |
1332 { | |
1333 swap_iq = l1_config.std.swap_iq_band1; | |
1334 } | |
1335 #else // L1_FF_MULTIBAND = 1 below | |
1336 | |
1337 UWORD16 physical_band_id; | |
1338 physical_band_id = | |
1339 l1_multiband_radio_freq_convert_into_physical_band_id(radio_freq); | |
1340 swap_iq = rf_band[physical_band_id].swap_iq; | |
1341 | |
1342 #endif // #if (L1_FF_MULTIBAND == 0) else | |
1343 | |
1344 switch(swap_iq) | |
1345 { | |
1346 case 0: /* No swap at all. */ | |
1347 case 2: /* DL, no swap. */ | |
1348 task_tab = (UWORD32)DSP_TASK_CODE[task]; | |
1349 break; | |
1350 case 1: /* DL I/Q swap. */ | |
1351 case 3: /* DL I/Q swap. */ | |
1352 task_tab = (UWORD32)DSP_TASK_CODE[task]; | |
1353 task_tab |= 0x8000L; | |
1354 break; | |
1355 } | |
1356 return(task_tab); | |
1357 } | |
1358 | |
1359 /*-------------------------------------------------------*/ | |
1360 /* l1s_swap_iq_ul() */ | |
1361 /*-------------------------------------------------------*/ | |
1362 /* Parameters : */ | |
1363 /* Return : */ | |
1364 /* Functionality : */ | |
1365 /*-------------------------------------------------------*/ | |
1366 UWORD32 l1s_swap_iq_ul(UWORD16 radio_freq, UWORD8 task) | |
1367 { | |
1368 UWORD8 swap_iq; | |
1369 UWORD32 task_tab = 0; //omaps00090550 | |
1370 | |
1371 #if (L1_FF_MULTIBAND == 0) | |
1372 | |
1373 if(((l1_config.std.id == DUAL) || (l1_config.std.id == DUALEXT) || (l1_config.std.id == DUAL_US)) && | |
1374 (radio_freq >= l1_config.std.first_radio_freq_band2)) | |
1375 { | |
1376 swap_iq = l1_config.std.swap_iq_band2; | |
1377 } | |
1378 else | |
1379 { | |
1380 swap_iq = l1_config.std.swap_iq_band1; | |
1381 } | |
1382 #else // L1_FF_MULTIBAND = 1 below | |
1383 | |
1384 UWORD16 physical_band_id = 0; | |
1385 physical_band_id = | |
1386 l1_multiband_radio_freq_convert_into_physical_band_id(radio_freq); | |
1387 swap_iq = rf_band[physical_band_id].swap_iq; | |
1388 | |
1389 #endif // #if (L1_FF_MULTIBAND == 0) else | |
1390 | |
1391 switch(swap_iq) | |
1392 { | |
1393 case 0: /* No swap at all. */ | |
1394 case 1: /* UL, no swap. */ | |
1395 task_tab = (UWORD32)DSP_TASK_CODE[task]; | |
1396 break; | |
1397 case 2: /* UL I/Q swap. */ | |
1398 case 3: /* UL I/Q swap. */ | |
1399 task_tab = (UWORD32)DSP_TASK_CODE[task]; | |
1400 task_tab |= 0x8000L; | |
1401 break; | |
1402 } | |
1403 return(task_tab); | |
1404 } | |
1405 | |
1406 | |
1407 /*-------------------------------------------------------*/ | |
1408 /* l1s_ADC_decision_on_NP() */ | |
1409 /*-------------------------------------------------------*/ | |
1410 /* Parameters : */ | |
1411 /* Return : */ | |
1412 /* Functionality : */ | |
1413 /*-------------------------------------------------------*/ | |
1414 UWORD8 l1s_ADC_decision_on_NP(void) | |
1415 { | |
1416 UWORD8 adc_active = INACTIVE; | |
1417 | |
1418 if (l1a_l1s_com.l1s_en_task[ALLC] == TASK_DISABLED) // no reorg mode | |
1419 { | |
1420 if (l1a_l1s_com.adc_mode & ADC_NEXT_NORM_PAGING) // perform ADC only one time | |
1421 { | |
1422 adc_active = ACTIVE; | |
1423 l1a_l1s_com.adc_mode &= ADC_MASK_RESET_IDLE; // reset in order to have only one ADC measurement in Idle | |
1424 } | |
1425 else | |
1426 { | |
1427 if (l1a_l1s_com.adc_mode & ADC_EACH_NORM_PAGING) // perform ADC on each "period" x bloc | |
1428 if ((++l1a_l1s_com.adc_cpt)>=l1a_l1s_com.adc_idle_period) // wait for the period | |
1429 { | |
1430 adc_active = ACTIVE; | |
1431 l1a_l1s_com.adc_cpt = 0; | |
1432 } | |
1433 } | |
1434 } | |
1435 else // ADC measurement in reorg mode | |
1436 { | |
1437 if (l1a_l1s_com.adc_mode & ADC_NEXT_NORM_PAGING_REORG) // perform ADC only one time | |
1438 { | |
1439 adc_active = ACTIVE; | |
1440 l1a_l1s_com.adc_mode &= ADC_MASK_RESET_IDLE; // reset in order to have only one ADC measurement in Idle | |
1441 } | |
1442 else | |
1443 { | |
1444 if (l1a_l1s_com.adc_mode & ADC_EACH_NORM_PAGING_REORG) // perform ADC on each "period" x bloc | |
1445 if ((++l1a_l1s_com.adc_cpt)>=l1a_l1s_com.adc_idle_period) // wait for the period | |
1446 { | |
1447 adc_active = ACTIVE; | |
1448 l1a_l1s_com.adc_cpt = 0; | |
1449 } | |
1450 } | |
1451 } | |
1452 return(adc_active); | |
1453 } | |
1454 | |
1455 | |
1456 #if (AMR == 1) | |
1457 /*-------------------------------------------------------*/ | |
1458 /* l1s_amr_get_ratscch_type() */ | |
1459 /*-------------------------------------------------------*/ | |
1460 /* */ | |
1461 /* Description: */ | |
1462 /* ------------ */ | |
1463 /* This function returns the type of a RATSCCH block */ | |
1464 /* Decoding is done according to ETSI spec 05.09 */ | |
1465 /* */ | |
1466 /* Input parameter: */ | |
1467 /* --------------- */ | |
1468 /* "a_ratscch" */ | |
1469 /* pointer to the RATSCCH block */ | |
1470 /* */ | |
1471 /* Output parameter: */ | |
1472 /* ---------------- */ | |
1473 /* Type of RATSCCH block. */ | |
1474 /* Can be: C_RATSCCH_UNKNOWN */ | |
1475 /* C_RATSCCH_CMI_PHASE_REQ */ | |
1476 /* C_RATSCCH_AMR_CONFIG_REQ_MAIN */ | |
1477 /* C_RATSCCH_AMR_CONFIG_REQ_ALT */ | |
1478 /* C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE */ | |
1479 /* C_RATSCCH_THRES_REQ */ | |
1480 /* */ | |
1481 /*-------------------------------------------------------*/ | |
1482 UWORD8 l1s_amr_get_ratscch_type(API *a_ratscch) | |
1483 { | |
1484 // Check if the RATSCCH block is a CMI_PHASE_REQ block | |
1485 // -> if and only if bits 1, 3 through 34 are cleared and bit 2 is set | |
1486 if(((UWORD16)(a_ratscch[3] & 0xFFFE) == 0x0004) && // bits 1, 3-15 are cleared, bit 2 is set | |
1487 ((UWORD16)(a_ratscch[4]) == 0x0000) && // bits 16-31 are cleared | |
1488 ((UWORD16)(a_ratscch[5] & 0x0007) == 0x0000)) // bits 32-34 are cleared | |
1489 { | |
1490 return C_RATSCCH_CMI_PHASE_REQ; | |
1491 } | |
1492 | |
1493 // Check if the RATSCCH block is a THRES_REQ block | |
1494 // -> if and only if bits 31 through 34 are cleared and bit 30 is set | |
1495 if(((UWORD16)(a_ratscch[4] & 0xC000) == 0x4000) && // bit 30 is set, bit 31 is cleared | |
1496 ((UWORD16)(a_ratscch[5] & 0x0007) == 0x0000)) // bits 32-34 are cleared | |
1497 { | |
1498 return C_RATSCCH_THRES_REQ; | |
1499 } | |
1500 | |
1501 // Check if the RATSCCH block is a AMR_CONFIG_REQ block | |
1502 // -> if and only if bits 33-34 are cleared and bits 30-32 are set | |
1503 if(((UWORD16)(a_ratscch[4] & 0xC000) == 0xC000) && // bits 30-31 are set | |
1504 ((UWORD16)(a_ratscch[5] & 0x0007) == 0x0001)) // bit 32 is set, bits 33-34 are cleared | |
1505 { | |
1506 // Check if it's a main AMR_CONFIG_REQ block or an alternative AMR_CONFIG_REQ block | |
1507 UWORD16 ratscch_acs = (a_ratscch[4] & 0x0FF0) >> 4; // get bits 20-27 | |
1508 UWORD8 nb_coders,i; | |
1509 | |
1510 // Count number of active coders | |
1511 for(i=0, nb_coders=0; i<8; i++) | |
1512 { | |
1513 if((ratscch_acs & 1)==1) nb_coders++; | |
1514 ratscch_acs >>= 1; | |
1515 } | |
1516 | |
1517 // If the number of coders is 1, 2 or 3, it is a main AMR_CONFIG_REQ block | |
1518 if(nb_coders<=3) | |
1519 return C_RATSCCH_AMR_CONFIG_REQ_MAIN; | |
1520 | |
1521 // If the number of coders is more than 4, it is an alternate AMR_CONFIG_REQ block | |
1522 // Check if it must be ignored (block THRES_REQ pending) or not | |
1523 // -> if and only if bits 0 through 19 are set | |
1524 if(((UWORD16)(a_ratscch[3]) == 0xFFFF) && // bits 0-15 are set | |
1525 ((UWORD16)(a_ratscch[4] & 0x000F) == 0x000F)) // bits 16-19 are set | |
1526 return C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE; | |
1527 else | |
1528 return C_RATSCCH_AMR_CONFIG_REQ_ALT; | |
1529 } | |
1530 | |
1531 // Block is not recognized | |
1532 return C_RATSCCH_UNKNOWN; | |
1533 } | |
1534 | |
1535 | |
1536 /*--------------------------------------------------------*/ | |
1537 /* l1s_amr_update_from_ratscch() */ | |
1538 /*--------------------------------------------------------*/ | |
1539 /* */ | |
1540 /* Description: */ | |
1541 /* ------------ */ | |
1542 /* This function updates the AMR parameters modified by */ | |
1543 /* the RATSCCH block received. This updates is done both */ | |
1544 /* in the NDB and in the L1A/L1S communication structure */ | |
1545 /* (aset pointer). */ | |
1546 /* Data manipulation is done according to ETSI spec 05.08 */ | |
1547 /* */ | |
1548 /* Input parameter: */ | |
1549 /* --------------- */ | |
1550 /* "a_ratscch_dl" */ | |
1551 /* pointer to the RATSCCH block */ | |
1552 /* */ | |
1553 /* Output parameter: */ | |
1554 /* ---------------- */ | |
1555 /* n/a */ | |
1556 /* */ | |
1557 /*--------------------------------------------------------*/ | |
1558 void l1s_amr_update_from_ratscch(API *a_ratscch_dl) | |
1559 { | |
1560 UWORD16 acs,hysteresis1,hysteresis2,hysteresis3,threshold1,threshold2,threshold3,icm,cmip; | |
1561 UWORD16 amr_change_bitmap=0; | |
1562 UWORD8 ratscch_type; | |
1563 BOOL ratscch_unknown=TRUE; // No AMR parameters update | |
1564 | |
1565 // Get the RATSCCH block's type | |
1566 ratscch_type = l1s_amr_get_ratscch_type(a_ratscch_dl); | |
1567 | |
1568 // Check the RATSCCH block's type | |
1569 switch(ratscch_type) | |
1570 { | |
1571 case C_RATSCCH_CMI_PHASE_REQ: | |
1572 { | |
1573 // Copy CMIP to L1 structure | |
1574 cmip = a_ratscch_dl[3] & 0x0001; // bit 0 | |
1575 l1a_l1s_com.dedic_set.aset->cmip=(UWORD8)cmip; | |
1576 amr_change_bitmap |= 1 << C_AMR_CHANGE_CMIP; | |
1577 // AMR parameters update flag | |
1578 ratscch_unknown=FALSE; | |
1579 } | |
1580 break; | |
1581 case C_RATSCCH_AMR_CONFIG_REQ_MAIN: | |
1582 { | |
1583 // Copy ACS to L1 structure | |
1584 acs = (a_ratscch_dl[4] & 0x0FF0) >> 4; // bits 20-27 | |
1585 l1a_l1s_com.dedic_set.aset->amr_configuration.active_codec_set=(UWORD8)acs; | |
1586 amr_change_bitmap |= 1 << C_AMR_CHANGE_ACS; | |
1587 | |
1588 // Copy ICM to L1 structure | |
1589 icm = (a_ratscch_dl[4] & 0x3000) >> 12; // bits 28-29 | |
1590 l1a_l1s_com.dedic_set.aset->amr_configuration.initial_codec_mode=(UWORD8)icm; | |
1591 amr_change_bitmap |= 1 << C_AMR_CHANGE_ICM; | |
1592 | |
1593 // Copy hysteresis 1 to L1 structure | |
1594 hysteresis1 = (a_ratscch_dl[3] & 0x03C0) >> 6; // bits 6-9 | |
1595 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[0]=(UWORD8)hysteresis1; | |
1596 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST1; | |
1597 | |
1598 // Copy threshold 1 to L1 structure | |
1599 threshold1 = a_ratscch_dl[3] & 0x003F; // bits 0-5 | |
1600 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[0]=(UWORD8)threshold1; | |
1601 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR1; | |
1602 | |
1603 // Copy hysteresis 2 to L1 structure | |
1604 hysteresis2 = a_ratscch_dl[4] & 0x000F; // bits 16-19 | |
1605 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[1]=(UWORD8)hysteresis2; | |
1606 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST2; | |
1607 | |
1608 // Copy threshold 2 to L1 structure | |
1609 threshold2 = (a_ratscch_dl[3] & 0xFC00) >> 10; // bits 10-15 | |
1610 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[1]=(UWORD8)threshold2; | |
1611 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR2; | |
1612 // AMR parameters update flag | |
1613 ratscch_unknown=FALSE; | |
1614 } | |
1615 break; | |
1616 case C_RATSCCH_AMR_CONFIG_REQ_ALT: | |
1617 { | |
1618 // Copy ACS to L1 structure | |
1619 acs = (a_ratscch_dl[4] & 0x0FF0) >> 4; // bits 20-27 | |
1620 l1a_l1s_com.dedic_set.aset->amr_configuration.active_codec_set=(UWORD8)acs; | |
1621 amr_change_bitmap |= 1 << C_AMR_CHANGE_ACS; | |
1622 | |
1623 // Copy ICM to L1 structure | |
1624 icm = (a_ratscch_dl[4] & 0x3000) >> 12; // bits 28-29 | |
1625 l1a_l1s_com.dedic_set.aset->amr_configuration.initial_codec_mode=(UWORD8)icm; | |
1626 amr_change_bitmap |= 1 << C_AMR_CHANGE_ICM; | |
1627 | |
1628 // Copy threshold 1 to L1 structure | |
1629 threshold1 = a_ratscch_dl[3] & 0x003F; // bits 0-5 | |
1630 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[0]=(UWORD8)threshold1; | |
1631 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR1; | |
1632 | |
1633 // Copy threshold 2 to L1 structure | |
1634 threshold2 = (a_ratscch_dl[3] & 0x0FC0) >> 6; // bits 6-11 | |
1635 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[1]=(UWORD8)threshold2; | |
1636 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR2; | |
1637 | |
1638 // Copy threshold 3 to L1 structure | |
1639 threshold3 = ((a_ratscch_dl[3] & 0xF000) >> 12) | // bits 12-15 | |
1640 ((a_ratscch_dl[4] & 0x0003) << 4); // bits 16-17 | |
1641 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[2]=(UWORD8)threshold3; | |
1642 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR3; | |
1643 | |
1644 // Copy hysteresis 1, 2 and 3 (common hysteresis) to L1 structure | |
1645 hysteresis1 = (a_ratscch_dl[4] & 0x000C) >> 2; // bits 18-19 | |
1646 hysteresis2 = hysteresis3 = hysteresis1; | |
1647 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[0]= | |
1648 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[1]= | |
1649 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[2]=(UWORD8)hysteresis1; | |
1650 amr_change_bitmap |= (1 << C_AMR_CHANGE_HYST1) | (1 << C_AMR_CHANGE_HYST2) | (1 << C_AMR_CHANGE_HYST3); | |
1651 // AMR parameters update flag | |
1652 ratscch_unknown=FALSE; | |
1653 } | |
1654 break; | |
1655 case C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE: | |
1656 { | |
1657 // Copy ACS to L1 structure | |
1658 acs = (a_ratscch_dl[4] & 0x0FF0) >> 4; // bits 20-27 | |
1659 l1a_l1s_com.dedic_set.aset->amr_configuration.active_codec_set=(UWORD8)acs; | |
1660 amr_change_bitmap |= 1 << C_AMR_CHANGE_ACS; | |
1661 | |
1662 // Copy ICM to L1 structure | |
1663 icm = (a_ratscch_dl[4] & 0x3000) >> 12; // bits 28-29 | |
1664 l1a_l1s_com.dedic_set.aset->amr_configuration.initial_codec_mode=(UWORD8)icm; | |
1665 amr_change_bitmap |= 1 << C_AMR_CHANGE_ICM; | |
1666 // AMR parameters update flag | |
1667 ratscch_unknown=FALSE; | |
1668 } | |
1669 break; | |
1670 case C_RATSCCH_THRES_REQ: | |
1671 { | |
1672 // Copy hysteresis 1 to L1 structure | |
1673 hysteresis1 = (a_ratscch_dl[3] & 0x03C0) >> 6; // bits 6-9 | |
1674 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[0]=(UWORD8)hysteresis1; | |
1675 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST1; | |
1676 | |
1677 // Copy threshold 1 to L1 structure | |
1678 threshold1 = a_ratscch_dl[3] & 0x003F; // bits 0-5 | |
1679 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[0]=(UWORD8)threshold1; | |
1680 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR1; | |
1681 | |
1682 // Copy hysteresis 2 to L1 structure | |
1683 hysteresis2 = a_ratscch_dl[4] & 0x000F; // bits 16-19 | |
1684 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[1]=(UWORD8)hysteresis2; | |
1685 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST2; | |
1686 | |
1687 // Copy threshold 2 to L1 structure | |
1688 threshold2 = (a_ratscch_dl[3] & 0xFC00) >> 10; // bits 10-15 | |
1689 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[1]=(UWORD8)threshold2; | |
1690 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR2; | |
1691 | |
1692 // Copy hysteresis 3 to L1 structure | |
1693 hysteresis3 = (a_ratscch_dl[4] & 0x3C00) >> 10; // bits 26-29 | |
1694 l1a_l1s_com.dedic_set.aset->amr_configuration.hysteresis[2]=(UWORD8)hysteresis3; | |
1695 amr_change_bitmap |= 1 << C_AMR_CHANGE_HYST3; | |
1696 | |
1697 // Copy threshold 3 to L1 structure | |
1698 threshold3 = (a_ratscch_dl[4] & 0x03F0) >> 4; // bits 20-25 | |
1699 l1a_l1s_com.dedic_set.aset->amr_configuration.threshold[2]=(UWORD8)threshold3; | |
1700 amr_change_bitmap |= 1 << C_AMR_CHANGE_THR3; | |
1701 // AMR parameters update flag | |
1702 ratscch_unknown=FALSE; | |
1703 } | |
1704 break; | |
1705 case C_RATSCCH_UNKNOWN: | |
1706 { | |
1707 // No AMR parameters update | |
1708 ratscch_unknown=TRUE; | |
1709 } | |
1710 break; | |
1711 } | |
1712 // AMR parameters update only if valid RATSCCH | |
1713 if(ratscch_unknown==FALSE) | |
1714 { | |
1715 // Update NDB with new AMR parameters | |
1716 l1ddsp_load_amr_param(l1a_l1s_com.dedic_set.aset->amr_configuration,l1a_l1s_com.dedic_set.aset->cmip); | |
1717 | |
1718 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) | |
1719 l1_trace_ratscch(l1s.actual_time.fn_mod42432,amr_change_bitmap); | |
1720 #endif | |
1721 } | |
1722 } | |
1723 | |
1724 #endif // AMR | |
1725 | |
1726 | |
1727 | |
1728 /*--------------------------------------------------------*/ | |
1729 /* l1_memcpy_16bit() */ | |
1730 /*--------------------------------------------------------*/ | |
1731 /* */ | |
1732 /* Description: */ | |
1733 /* ------------ */ | |
1734 /* This function is equivalemt of memcopy. Thid function */ | |
1735 /* does only 8/16 bit accessed to both source and */ | |
1736 /* destination */ | |
1737 /* */ | |
1738 /* Input parameter: */ | |
1739 /* --------------- */ | |
1740 /* "src" - input pointer */ | |
1741 /* "len" - number of bytes to copy */ | |
1742 /* */ | |
1743 /* Output parameter: */ | |
1744 /* ---------------- */ | |
1745 /* "dst" - output pointer */ | |
1746 /* */ | |
1747 /*--------------------------------------------------------*/ | |
1748 void l1_memcpy_16bit(void *dst,void* src,unsigned int len) | |
1749 { | |
1750 unsigned int i; | |
1751 unsigned int tempLen; | |
1752 unsigned char *cdst,*csrc; | |
1753 unsigned short *ssrc,*sdst; | |
1754 | |
1755 cdst=dst; | |
1756 csrc=src; | |
1757 sdst=dst; | |
1758 ssrc=src; | |
1759 | |
1760 if(((unsigned int)src&0x01) || ((unsigned int)dst&0x01)){ | |
1761 // if either source or destination is not 16-bit aligned do the entire memcopy | |
1762 // in 8-bit | |
1763 for(i=0;i<len;i++){ | |
1764 *cdst++=*csrc++; | |
1765 } | |
1766 } | |
1767 else{ | |
1768 // if both the source and destination are 16-bit aligned do the memcopy | |
1769 // in 16-bits | |
1770 tempLen = len>>1; | |
1771 for(i=0;i<tempLen;i++){ | |
1772 *sdst++ = *ssrc++; | |
1773 } | |
1774 if(len & 0x1){ | |
1775 // if the caller wanted to copy odd number of bytes do a last 8-bit copy | |
1776 cdst=(unsigned char*)sdst; | |
1777 csrc=(unsigned char*)ssrc; | |
1778 *cdst++ = *csrc++; | |
1779 } | |
1780 } | |
1781 return; | |
1782 } | |
1783 | |
1784 /*-----------------------------------------------------------------*/ | |
1785 /* l1s_restore_synchro */ | |
1786 /*-----------------------------------------------------------------*/ | |
1787 /* Description: */ | |
1788 /* ------------ */ | |
1789 /* This function restores TPU synchro after an actiity */ | |
1790 /* using synchro/synchro back scheme. */ | |
1791 /* */ | |
1792 /* Input parameters: */ | |
1793 /* ----------------- */ | |
1794 /* None */ | |
1795 /* */ | |
1796 /* Input parameters from globals: */ | |
1797 /* ------------------------------ */ | |
1798 /* l1s.tpu_offset */ | |
1799 /* l1s.next_time */ | |
1800 /* l1s.next_plus_time */ | |
1801 /* */ | |
1802 /* Output parameters: */ | |
1803 /* ------------------ */ | |
1804 /* None */ | |
1805 /* */ | |
1806 /* Modified parameters from globals: */ | |
1807 /* --------------------------------- */ | |
1808 /* l1s.actual_time */ | |
1809 /* l1s.next_time */ | |
1810 /* l1s.next_plus_time */ | |
1811 /* l1s.tpu_ctrl_reg */ | |
1812 /* l1s.dsp_ctrl_reg */ | |
1813 /*-----------------------------------------------------------------*/ | |
1814 void l1s_restore_synchro(void) | |
1815 { | |
1816 // Slide synchro back to mach current serving timeslot. | |
1817 l1dmacro_synchro(SWITCH_TIME, l1s.tpu_offset); | |
1818 | |
1819 // Increment frame number. | |
1820 #if L1_GPRS | |
1821 l1s.actual_time = l1s.next_time; | |
1822 l1s.next_time = l1s.next_plus_time; | |
1823 l1s_increment_time(&(l1s.next_plus_time), 1); // Increment "next_plus time". | |
1824 #else | |
1825 l1s.actual_time = l1s.next_time; | |
1826 l1s_increment_time(&(l1s.next_time), 1); // Increment "next time". | |
1827 #endif | |
1828 | |
1829 l1s.tpu_ctrl_reg |= CTRL_SYCB; | |
1830 l1s.dsp_ctrl_reg |= CTRL_SYNC; | |
1831 | |
1832 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) | |
1833 trace_fct(CST_L1S_ADJUST_TIME, (UWORD32)(-1)); | |
1834 #endif | |
1835 } | |
1836 | |
1837 #if (FF_L1_FAST_DECODING == 1) | |
1838 BOOL l1s_check_deferred_control(UWORD8 task, UWORD8 burst_id) | |
1839 { | |
1840 /* Control activities are performed only if: | |
1841 - Fast decoding is not authorized | |
1842 - Fast decoding authorized, control running inside the fast HISR context and not first burst | |
1843 - Fast decoding authorized, control running inside L1S context and first burst */ | |
1844 | |
1845 /* Running from fast API HISR? */ | |
1846 BOOL fast_decoding_hisr = (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_PROCESSING); | |
1847 | |
1848 if (fast_decoding_hisr && (burst_id == BURST_1)) | |
1849 { | |
1850 /* Error this case shouldn't happen */ | |
1851 return TRUE; | |
1852 } | |
1853 else if (!fast_decoding_hisr && (burst_id != BURST_1)) | |
1854 { | |
1855 /* Currently running from L1S, control must be performed on the upcoming fast HISR */ | |
1856 l1a_apihisr_com.fast_decoding.task = task; | |
1857 l1a_apihisr_com.fast_decoding.burst_id = burst_id; | |
1858 /* If a tasks semaphore get SET do not do deferred control */ | |
1859 if(!(l1a_l1s_com.task_param[task] == SEMAPHORE_SET)) | |
1860 { | |
1861 l1a_apihisr_com.fast_decoding.deferred_control_req = TRUE; | |
1862 return TRUE; | |
1863 } | |
1864 } | |
1865 else if (!fast_decoding_hisr && (burst_id == BURST_1)) | |
1866 { | |
1867 /* Control running from L1S for the first burst => Control must be performed now. */ | |
1868 /* As a result, a fast API IT will be triggered on the next frame */ | |
1869 | |
1870 if (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_AWAITED) | |
1871 { | |
1872 /* A fast API IT was already awaited. It means that we are starting the fast decoding */ | |
1873 /* of a new block before the previous one is finished. */ | |
1874 /* This case is signaled through the variable below so the status can stay as awaited */ | |
1875 /* for the first fast API IT of the new block. */ | |
1876 l1a_apihisr_com.fast_decoding.contiguous_decoding = TRUE; | |
1877 } | |
1878 else | |
1879 { | |
1880 l1a_apihisr_com.fast_decoding.status = C_FAST_DECODING_AWAITED; | |
1881 } | |
1882 l1a_apihisr_com.fast_decoding.task = task; | |
1883 return FALSE; | |
1884 } | |
1885 /* In other cases do control now. */ | |
1886 return FALSE; | |
1887 } /* end function l1s_check_deferred_control */ | |
1888 | |
1889 BOOL l1s_check_fast_decoding_authorized(UWORD8 task) | |
1890 { | |
1891 BOOL result = FALSE; | |
1892 | |
1893 /* Is a fast decoding already in progress (AWAITED or PROCESSING states)? */ | |
1894 /* Is a fast decoding complete but waiting for the read activity (COMPLETE state)? */ | |
1895 /* In that case, it will continue, even if a mode change has occured. */ | |
1896 BOOL already_in_progress = ( (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_AWAITED) | |
1897 || (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_PROCESSING) | |
1898 || (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_COMPLETE) ); | |
1899 | |
1900 /* One variable used later that contains the status of several tasks */ | |
1901 BOOL no_serving_audio_and_neighbour_tasks = ( | |
1902 (l1a_l1s_com.l1s_en_task[EP] == TASK_DISABLED) | |
1903 && (l1a_l1s_com.l1s_en_task[ALLC] == TASK_DISABLED) | |
1904 && (l1a_l1s_com.l1s_en_task[NSYNC] == TASK_DISABLED) | |
1905 && (l1a_l1s_com.l1s_en_task[FBNEW] == TASK_DISABLED) | |
1906 && (l1a_l1s_com.l1s_en_task[SBCONF] == TASK_DISABLED) | |
1907 && (l1a_l1s_com.l1s_en_task[BCCHN] == TASK_DISABLED) | |
1908 && (l1a_l1s_com.l1s_en_task[EBCCHS] == TASK_DISABLED) | |
1909 //&& (l1a_l1s_com.l1s_en_task[NBCCHS] == TASK_DISABLED) | |
1910 && (l1a_l1s_com.l1s_en_task[BCCHN_TOP] == TASK_DISABLED) | |
1911 #if (L1_GPRS) | |
1912 && (l1a_l1s_com.l1s_en_task[PBCCHS] == TASK_DISABLED) | |
1913 && (l1a_l1s_com.l1s_en_task[PEP] == TASK_DISABLED) | |
1914 && (l1a_l1s_com.l1s_en_task[PALLC] == TASK_DISABLED) | |
1915 && (l1a_l1s_com.l1s_en_task[PBCCHN_IDLE] == TASK_DISABLED) | |
1916 #endif /* L1_GPRS */ | |
1917 //&& (l1a_l1s_com.l1s_en_task[SMSCB] == TASK_DISABLED) | |
1918 #if (L1_MP3 == 1) | |
1919 && (l1a_apihisr_com.mp3.running == FALSE) | |
1920 #endif | |
1921 #if (L1_AAC == 1) | |
1922 && (l1a_apihisr_com.aac.running == FALSE) | |
1923 #endif | |
1924 ); | |
1925 | |
1926 /* If fast decoding is already forbidden, do not enable it until the end of the block. */ | |
1927 /* The forbidden status is reset at the first control of the block */ | |
1928 if (l1a_apihisr_com.fast_decoding.status == C_FAST_DECODING_FORBIDDEN) | |
1929 { | |
1930 return FALSE; | |
1931 } | |
1932 | |
1933 switch(task) | |
1934 { | |
1935 case NP: | |
1936 { | |
1937 /* Enable Fast Paging (NP) except if CCCH reorg*/ | |
1938 if ( ( already_in_progress == TRUE ) | |
1939 || | |
1940 ( (l1a_l1s_com.mode == I_MODE) | |
1941 && (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED) | |
1942 && (no_serving_audio_and_neighbour_tasks == TRUE) ) | |
1943 ) | |
1944 { | |
1945 result = TRUE; | |
1946 } | |
1947 break; | |
1948 } /* case NP */ | |
1949 | |
1950 case NBCCHS: | |
1951 { | |
1952 /* Enable Fast Paging (NP) except if CCCH reorg*/ | |
1953 if ( ( already_in_progress == TRUE ) | |
1954 || | |
1955 ( (l1a_l1s_com.mode == I_MODE) | |
1956 && (l1a_l1s_com.l1s_en_task[NBCCHS] == TASK_ENABLED) | |
1957 && (no_serving_audio_and_neighbour_tasks == TRUE) ) | |
1958 ) | |
1959 { | |
1960 result = TRUE; | |
1961 } | |
1962 break; | |
1963 } /* case NBCCHS */ | |
1964 | |
1965 #if (L1_GPRS) | |
1966 case PNP: | |
1967 { | |
1968 /* Enable Fast Paging (PNP) except if PCCCH reorg*/ | |
1969 if ( ( already_in_progress == TRUE ) | |
1970 || | |
1971 ( (l1a_l1s_com.mode == I_MODE) | |
1972 && (l1a_l1s_com.l1s_en_task[PNP] == TASK_ENABLED) | |
1973 && (no_serving_audio_and_neighbour_tasks == TRUE) | |
1974 ) | |
1975 ) | |
1976 { | |
1977 result = TRUE; | |
1978 } | |
1979 break; | |
1980 } /* case PNP */ | |
1981 #endif /* L1_GPRS*/ | |
1982 | |
1983 } /* switch(task) */ | |
1984 | |
1985 #if (L1_GPRS) | |
1986 if ((result == FALSE) && ((task == NP) || (task == PNP) || (task == NBCCHS))) | |
1987 #else /* NO_GPRS*/ | |
1988 if ((result == FALSE) && ((task == NP) || (task == NBCCHS))) | |
1989 #endif /* L1_GPRS */ | |
1990 { | |
1991 l1a_apihisr_com.fast_decoding.status = C_FAST_DECODING_FORBIDDEN; | |
1992 } | |
1993 | |
1994 return result; | |
1995 } /* end function l1s_check_fast_decoding_authorized */ | |
1996 | |
1997 #endif /* FF_L1_FAST_DECODING */ | |
1998 /*-----------------------------------------------------------------*/ | |
1999 /* l1s_check_sacch_dl_block */ | |
2000 /*-----------------------------------------------------------------*/ | |
2001 /* Description: */ | |
2002 /* ------------ */ | |
2003 /* Downlink SACCH buffer comparison function for FER Traces */ | |
2004 /* This is called only when there is a successfully decoded */ | |
2005 /* block. The count of no of successfully decoded SACCH blocks */ | |
2006 /* is updated. */ | |
2007 /* */ | |
2008 /* Input parameters: */ | |
2009 /* ----------------- */ | |
2010 /* sacch_dl_block "Downlink SACCH BLOCK" */ | |
2011 /* */ | |
2012 /* Output parameters: */ | |
2013 /* ------------------ */ | |
2014 /* None */ | |
2015 /* */ | |
2016 /*-----------------------------------------------------------------*/ | |
2017 #if ((FF_REPEATED_SACCH) && (TRACE_TYPE ==1 || TRACE_TYPE == 4)) | |
2018 | |
2019 void l1s_check_sacch_dl_block(API *sacch_dl_block) | |
2020 { | |
2021 int i,j,repeat=1; | |
2022 if( trace_info.repeat_sacch.dl_buffer_empty == FALSE ) | |
2023 { | |
2024 for(i=3,j=0;i<15;i++,j++) | |
2025 { | |
2026 if(trace_info.repeat_sacch.dl_buffer[j] != sacch_dl_block[i]) | |
2027 { | |
2028 break; | |
2029 } | |
2030 } | |
2031 if( i != 15 ) | |
2032 { | |
2033 repeat=0; | |
2034 } | |
2035 } | |
2036 else /* if( trace_info.repeat_sacch.dl_buffer_empty == FALSE ) */ | |
2037 { | |
2038 repeat=0; | |
2039 } /* end else empty DL SACCH buffer*/ | |
2040 if(repeat == 0) | |
2041 { | |
2042 trace_info.repeat_sacch.dl_good_norep++; | |
2043 for ( i=3 ; i<15 ; i++ ) | |
2044 { | |
2045 trace_info.repeat_sacch.dl_buffer[i] = sacch_dl_block[i];// info_address[i]; | |
2046 } | |
2047 trace_info.repeat_sacch.dl_buffer_empty = FALSE; | |
2048 } /* end if repeat = 0*/ | |
2049 else | |
2050 { | |
2051 trace_info.repeat_sacch.dl_buffer_empty = TRUE; | |
2052 } /* end else repeat = 1*/ | |
2053 } /* end function void l1s_check_sacch_dl_block */ | |
2054 #endif /* ((FF_REPEATED_SACCH) && (TRACE_TYPE ==1 || TRACE_TYPE == 4)) */ | |
2055 | |
2056 | |
2057 /*-----------------------------------------------------------------*/ | |
2058 /* l1s_store_sacch_buffer */ | |
2059 /*-----------------------------------------------------------------*/ | |
2060 /* Description: */ | |
2061 /* ------------ */ | |
2062 /* Function to store data in case of a retransmission. */ | |
2063 /* */ | |
2064 /* */ | |
2065 /* Input parameters: */ | |
2066 /* ----------------- */ | |
2067 /* sacch_ul_block "SACCH Uplink block to be stored" */ | |
2068 /* repeat_sacch "The buffer tocontain the stored block" */ | |
2069 /* */ | |
2070 /* Output parameters: */ | |
2071 /* ------------------ */ | |
2072 /* None */ | |
2073 /* */ | |
2074 /*-----------------------------------------------------------------*/ | |
2075 | |
2076 #if (FF_REPEATED_SACCH == 1 ) | |
2077 void l1s_store_sacch_buffer(T_REPEAT_SACCH *repeat_sacch, UWORD8 *sacch_ul_block) | |
2078 { | |
2079 int i=0; | |
2080 /* Store the first 11 words after header in the first 22 bytes. */ | |
2081 for(i=0;i<23;i++) | |
2082 { | |
2083 repeat_sacch->buffer[i] = sacch_ul_block[i] ; | |
2084 } | |
2085 repeat_sacch->buffer_empty = FALSE; | |
2086 } | |
2087 #endif /* (FF_REPEATED_SACCH == 1 ) */ | |
2088 | |
2089 | |
2090 /*-----------------------------------------------------------------*/ | |
2091 /* l1s_repeated_facch_check */ | |
2092 /*-----------------------------------------------------------------*/ | |
2093 /* Description: */ | |
2094 /* ------------ */ | |
2095 /* If two successfully decoded blocks (separated by 8 or 9 frames) are */ | |
2096 /* identical then it returns a NULL buffer otherwise a pointer to the last block */ | |
2097 /* data. */ | |
2098 /* */ | |
2099 /* */ | |
2100 /* Input parameters: */ | |
2101 /* ----------------- */ | |
2102 /* "FACCH block to be stored" */ | |
2103 /* */ | |
2104 /* Output parameters: */ | |
2105 /* ------------------ */ | |
2106 /* None */ | |
2107 /* */ | |
2108 /*-----------------------------------------------------------------*/ | |
2109 | |
2110 | |
2111 #if ( FF_REPEATED_DL_FACCH == 1 ) | |
2112 API * l1s_repeated_facch_check(API *info_address) | |
2113 { | |
2114 unsigned int repeat=1; | |
2115 unsigned int i,j; | |
2116 UWORD8 counter_candidate; | |
2117 | |
2118 counter_candidate=l1s.repeated_facch.counter_candidate; | |
2119 if( l1s.repeated_facch.pipeline[counter_candidate].buffer_empty == FALSE ) | |
2120 { | |
2121 for(i=3,j=0;i<15;j++,i++) | |
2122 { | |
2123 if(l1s.repeated_facch.pipeline[counter_candidate].buffer[j] != info_address[i]) | |
2124 { | |
2125 break; | |
2126 } | |
2127 } | |
2128 if( i != 15 ) | |
2129 { | |
2130 repeat=0; | |
2131 } | |
2132 } | |
2133 else | |
2134 { | |
2135 repeat=0; | |
2136 } /* end else buffer empty*/ | |
2137 #if TESTMODE | |
2138 if(l1_config.repeat_facch_dl_enable != REPEATED_FACCHDL_ENABLE) // repeated FACCH mode is disabled | |
2139 { | |
2140 repeat = 0; | |
2141 } | |
2142 #endif | |
2143 if(repeat == 0) | |
2144 { | |
2145 return &info_address[0]; | |
2146 } | |
2147 else | |
2148 { | |
2149 #if (TRACE_TYPE==1) || (TRACE_TYPE==4) | |
2150 trace_info.facch_dl_repetition_block_count++; | |
2151 #endif | |
2152 if (((l1s.actual_time.fn - fn_prev ) == 8) || ((l1s.actual_time.fn - fn_prev ) == 9 )) // added debug | |
2153 return (API)NULL; | |
2154 else | |
2155 return &info_address[0]; | |
2156 } | |
2157 } | |
2158 #endif /* FF_REPEATED_DL_FACCH == 1 */ | |
2159 | |
2160 | |
2161 | |
2162 #if ( FF_REPEATED_DL_FACCH == 1 ) | |
2163 void l1s_store_facch_buffer(T_REPEAT_FACCH *repeated_facch, API *facch_block) | |
2164 { | |
2165 int i; | |
2166 UWORD8 counter_candidate; | |
2167 fn_prev = l1s.actual_time.fn ;// added | |
2168 counter_candidate=repeated_facch->counter_candidate; | |
2169 /* Store the first 12 words after header in the first 23 bytes. */ | |
2170 for(i=0;i<13;i++) | |
2171 { | |
2172 repeated_facch->pipeline[counter_candidate].buffer[i] = facch_block[i] ; | |
2173 } | |
2174 repeated_facch->pipeline[counter_candidate].buffer_empty = FALSE; | |
2175 } | |
2176 #endif /* ( FF_REPEATED_DL_FACCH == 1 ) */ | |
2177 | |
2178 #if(L1_FF_MULTIBAND == 1) | |
2179 | |
2180 #if 0 | |
2181 | |
2182 /*-------------------------------------------------------*/ | |
2183 /* l1_multiband_radio_freq_convert_into_effective_band_id*/ | |
2184 /*-------------------------------------------------------*/ | |
2185 /* Parameters : radio_freq the frequency to convert */ | |
2186 /* */ | |
2187 /* */ | |
2188 /* */ | |
2189 /* Return : the ID of the effectiev band in which */ | |
2190 /* is located radio_freq */ | |
2191 /* Functionality : compare radio_freq with the effective */ | |
2192 /* bands ranges, return efective_band_id */ | |
2193 /* */ | |
2194 /* */ | |
2195 /*-------------------------------------------------------*/ | |
2196 UWORD8 l1_multiband_radio_freq_convert_into_effective_band_id(UWORD16 radio_freq) | |
2197 { | |
2198 UWORD8 effective_band_id = 0; | |
2199 while( effective_band_id < NB_MAX_EFFECTIVE_SUPPORTED_BANDS) | |
2200 { | |
2201 if ((radio_freq >= multiband_conversion_data[effective_band_id].first_radio_freq) | |
2202 && (radio_freq < (multiband_conversion_data[effective_band_id].first_radio_freq + multiband_conversion_data[effective_band_id].nbmax_carrier)) ) | |
2203 | |
2204 { | |
2205 return(effective_band_id); | |
2206 } | |
2207 else | |
2208 { | |
2209 effective_band_id ++; | |
2210 } | |
2211 } | |
2212 if(effective_band_id == NB_MAX_EFFECTIVE_SUPPORTED_BANDS) | |
2213 { | |
2214 l1_multiband_error_handler(radio_freq); | |
2215 } | |
2216 return(effective_band_id); | |
2217 | |
2218 } | |
2219 /*-------------------------------------------------------*/ | |
2220 /* l1_multiband_radio_freq_convert_into_physical_band_id */ | |
2221 /*-------------------------------------------------------*/ | |
2222 /* Parameters : radio_freq the frequency to convert */ | |
2223 /* */ | |
2224 /* */ | |
2225 /* */ | |
2226 /* Return : the ID of the physical_band band in which*/ | |
2227 /* radio_freq is located */ | |
2228 /* Functionality : Identify effective_band_id, the ID of */ | |
2229 /* the effective band in whicb radio_freq is located */ | |
2230 /* then derive physical_band_id from effective_band_id */ | |
2231 /*-------------------------------------------------------*/ | |
2232 | |
2233 UWORD8 l1_multiband_radio_freq_convert_into_physical_band_id(UWORD16 radio_freq) | |
2234 { | |
2235 UWORD8 effective_band_id, physical_band_id; | |
2236 effective_band_id = l1_multiband_radio_freq_convert_into_effective_band_id(radio_freq); | |
2237 physical_band_id = multiband_conversion_data[effective_band_id].physical_band_id; | |
2238 return(physical_band_id); | |
2239 } | |
2240 | |
2241 /*-------------------------------------------------------*/ | |
2242 /* l1_multiband_radio_freq_convert_into_operative_radio_freq*/ | |
2243 /*-------------------------------------------------------*/ | |
2244 /* Parameters : radio_freq the frequency to convert */ | |
2245 /* */ | |
2246 /* */ | |
2247 /* */ | |
2248 /* Return : the operative_radio_freq corresponding to radio_freq */ | |
2249 /* Functionality : identify effective_band_id, then */ | |
2250 /* based on the relationships linking the ranges of operative_radio_freq*/ | |
2251 /* and radio_freq , derive operative_radio_freq */ | |
2252 /*-------------------------------------------------------*/ | |
2253 UWORD16 l1_multiband_radio_freq_convert_into_operative_radio_freq(UWORD16 radio_freq) | |
2254 { | |
2255 UWORD8 effective_band_id; | |
2256 UWORD16 operative_radio_freq; | |
2257 effective_band_id = l1_multiband_radio_freq_convert_into_effective_band_id(radio_freq); | |
2258 operative_radio_freq = radio_freq - multiband_conversion_data[effective_band_id].first_radio_freq + multiband_conversion_data[effective_band_id].first_operative_radio_freq; | |
2259 return(operative_radio_freq); | |
2260 } | |
2261 /*--------------------------------------------------------*/ | |
2262 /* l1_multiband_map_radio_freq_into_tpu_table */ | |
2263 /*--------------------------------------------------------*/ | |
2264 /* Parameters : */ | |
2265 /* radio_freq the parameter to be converted */ | |
2266 /* */ | |
2267 /* Return : the index in table rf_band or rf_tpu_band */ | |
2268 /* corresponding to radio_freq */ | |
2269 /* Functionality :identify physical_band_id */ | |
2270 /* then derive from physical_band_id, tpu_band_index to be*/ | |
2271 /* returned a physical band having the ID physical_band_id*/ | |
2272 /* is mapped to the table rf_band[physical_band_id ] */ | |
2273 /*--------------------------------------------------------*/ | |
2274 UWORD8 l1_multiband_map_radio_freq_into_tpu_table(UWORD16 radio_freq) | |
2275 { | |
2276 UWORD8 tpu_table_index = 0; | |
2277 UWORD8 physical_band_id = 0; | |
2278 physical_band_id = l1_multiband_radio_freq_convert_into_physical_band_id(radio_freq); | |
2279 /*For Neptune a band having the ID physical_band_id is mapped to multiband_rf_data[physical_band_id], rf_band[physical_band_id]*/ | |
2280 /*Consequently the existence of this API for API is not necessary since it is redundant with l1_multiband_radio_freq_convert_into_physical_band_id*/ | |
2281 tpu_table_index = physical_band_id; | |
2282 return(tpu_table_index); | |
2283 } | |
2284 /*--------------------------------------------------------*/ | |
2285 /* l1_multiband_error_handler */ | |
2286 /*--------------------------------------------------------*/ | |
2287 /* Parameters : */ | |
2288 /* radio_freq the channel number received from the L3 */ | |
2289 /* */ | |
2290 /* Return : */ | |
2291 /* corresponding to radio_freq */ | |
2292 /* Functionality :handling error code of MULTIBAND */ | |
2293 /*--------------------------------------------------------*/ | |
2294 void l1_multiband_error_handler(UWORD16 radio_freq) | |
2295 { | |
2296 L1_MULTIBAND_TRACE_PARAMS(MULTIBAND_ERROR_TRACE_ID, 1); | |
2297 #if (OP_L1_STANDALONE == 1) | |
2298 #if(CODE_VERSION == NOT_SIMULATION) | |
2299 L1BSP_error_handler(); | |
2300 #endif /*if(CODE_VERSION == NOT_SIMULATION)*/ | |
2301 #endif | |
2302 } | |
2303 #endif // if 0 | |
2304 #endif /*if (L1_FF_MULTIBAND == 1)*/ | |
2305 | |
2306 #if (OP_L1_STANDALONE == 1) | |
2307 | |
2308 UWORD8 l1_get_pwr_mngt() | |
2309 { | |
2310 return(l1_config.pwr_mngt); | |
2311 } | |
2312 | |
2313 #endif | |
2314 | |
2315 void l1_multiband_error_handler(UWORD16 radio_freq) | |
2316 { | |
2317 while(1); | |
2318 } | |
2319 | |
2320 |