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comparison L1/cfile/l1_init.c @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
parents
children b36540edb046
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-1:000000000000 0:75a11d740a02
1 /************ Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_INIT.C
4 *
5 * Filename l1_init.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1_INIT_C
11
12 #include "config.h"
13 #include "l1_confg.h"
14
15 #if (CODE_VERSION == SIMULATION)
16 #include <string.h>
17 #include "l1_types.h"
18 #include "sys_types.h"
19 #include "l1_const.h"
20 #include "l1_time.h"
21 #include "l1_signa.h"
22
23 #if TESTMODE
24 #include "l1tm_defty.h"
25 #endif
26 #if (AUDIO_TASK == 1)
27 #include "l1audio_const.h"
28 #include "l1audio_cust.h"
29 #include "l1audio_defty.h"
30 #endif
31 #if (L1_GTT == 1)
32 #include "l1gtt_const.h"
33 #include "l1gtt_defty.h"
34 #endif
35
36 #if (L1_MP3 == 1)
37 #include "l1mp3_defty.h"
38 #endif
39
40 #if (L1_MIDI == 1)
41 #include "l1midi_defty.h"
42 #endif
43 //ADDED FOR AAC
44 #if (L1_AAC == 1)
45 #include "l1aac_defty.h"
46 #endif
47 #if (L1_DYN_DSP_DWNLD == 1)
48 #include "l1_dyn_dwl_proto.h"
49 #endif
50
51 #include "l1_defty.h"
52 #include "cust_os.h"
53 #include "l1_msgty.h"
54 #include "l1_varex.h"
55 #include "l1_proto.h"
56 #include "l1_mftab.h"
57 #include "l1_tabs.h"
58 #include "l1_ver.h"
59 #include "ulpd.h"
60
61 #include "l1_proto.h"
62
63 #if L1_GPRS
64 #include "l1p_cons.h"
65 #include "l1p_msgt.h"
66 #include "l1p_deft.h"
67 #include "l1p_vare.h"
68 #include "l1p_tabs.h"
69 #include "l1p_macr.h"
70 #include "l1p_ver.h"
71 #endif
72
73 #if TESTMODE
74 #include "l1tm_ver.h"
75 #endif
76
77 #include <stdio.h>
78 #include "sim_cfg.h"
79 #include "sim_cons.h"
80 #include "sim_def.h"
81 #include "sim_var.h"
82
83 #else // NO SIMULATION
84
85 #include <string.h>
86 /* #include "tm_defs.h" */
87 #include "l1_types.h"
88 #include "sys_types.h"
89 #include "../dsp/leadapi.h"
90 #include "l1_const.h"
91 #include "l1_macro.h"
92 #include "l1_time.h"
93 #include "l1_signa.h"
94 #if (AUDIO_TASK == 1)
95 #include "l1audio_const.h"
96 #include "l1audio_cust.h"
97 #include "l1audio_defty.h"
98 #endif
99
100
101 #include "../../bsp/abb+spi/spi_drv.h"
102 #include "../../bsp/abb+spi/abb.h"
103 #if (ANALOG != 11)
104 #include "../../bsp/abb+spi/abb_core_inth.h"
105 #endif
106
107 #if TESTMODE
108 #include "l1tm_defty.h"
109 #endif
110
111 #if (L1_GTT == 1)
112 #include "l1gtt_const.h"
113 #include "l1gtt_defty.h"
114 #endif
115
116 #if (L1_MP3 == 1)
117 #include "l1mp3_defty.h"
118 #endif
119
120 #if (L1_MIDI == 1)
121 #include "l1midi_defty.h"
122 #endif
123 //ADDED FOR AAC
124 #if (L1_AAC == 1)
125 #include "l1aac_defty.h"
126 #endif
127 #if (L1_DYN_DSP_DWNLD == 1)
128 #include "l1_dyn_dwl_proto.h"
129 #endif
130
131 #include "l1_defty.h"
132 #include "../../gpf/inc/cust_os.h"
133 #include "l1_msgty.h"
134 #include "l1_varex.h"
135 #include "l1_proto.h"
136 #include "l1_mftab.h"
137 #include "l1_tabs.h"
138 #include "l1_ver.h"
139 #include "tpudrv.h"
140
141 #if (CHIPSET == 12) || (CHIPSET == 15)
142 #include "sys_inth.h"
143 #else
144 #include "../../bsp/mem.h"
145 #include "../../bsp/inth.h"
146 #include "../../bsp/dma.h"
147 #include "../../bsp/iq.h"
148 #endif
149
150 #include "../../bsp/clkm.h"
151 #include "../../bsp/rhea_arm.h"
152 #include "../../bsp/ulpd.h"
153
154 #include "l1_proto.h"
155
156 #if L1_GPRS
157 #include "l1p_cons.h"
158 #include "l1p_msgt.h"
159 #include "l1p_deft.h"
160 #include "l1p_vare.h"
161 #include "l1p_tabs.h"
162 #include "l1p_macr.h"
163 #include "l1p_ver.h"
164 #endif
165
166 #if TESTMODE
167 #include "l1tm_ver.h"
168 #endif
169
170 #endif // NOT SIMULATION
171
172
173
174 #if (RF_FAM == 61)
175 #if (DRP_FW_EXT==0)
176 #include "drp_drive.h"
177 #include "drp_api.h"
178 #include "l1_rf61.h"
179 #include "apc.h"
180 #else
181 #include "l1_rf61.h"
182 #include "l1_drp_inc.h"
183 #endif
184 #endif
185
186
187 #if (RF_FAM == 60)
188 #include "drp_drive.h"
189 #include "drp_api.h"
190 #include "l1_rf60.h"
191 #endif
192
193 #if (TRACE_TYPE == 1)||(TRACE_TYPE == 4)
194 #include "l1_trace.h"
195 #endif
196
197 #include <string.h>
198 #include <stdio.h>
199
200 #if (ANALOG == 11)
201 #include "bspTwl3029_I2c.h"
202 #include "bspTwl3029_Aud_Map.h"
203 #include "bspTwl3029_Madc.h"
204 #endif
205
206 #if (RF_FAM == 61)
207 //OMAPS148175
208 #include "l1_drp_if.h"
209 #include "drp_main.h"
210 #endif
211
212 #if (ANALOG == 11)
213 #if (L1_MADC_ON == 1)
214 extern BspTwl3029_MadcResults l1_madc_results;
215 extern void l1a_madc_callback(void);
216 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC
217 extern UWORD32 Cust_navc_ctrl_status(UWORD8 d_navc_start_stop_read);//NAVC
218 #endif
219 #endif
220
221 #if (AUDIO_DEBUG == 1)
222 extern UWORD8 audio_reg_read_status;
223 #endif
224
225 #endif
226
227 #if (AUDIO_TASK == 1)
228 /**************************************/
229 /* External audio prototypes */
230 /**************************************/
231 extern void l1audio_initialize_var (void);
232 #endif
233
234 extern void l1audio_dsp_init (void);
235 extern void initialize_wait_loop(void);
236
237 #if (L1_GPRS)
238 // external functions from GPRS implementation
239 void initialize_l1pvar(void);
240 void l1pa_reset_cr_freq_list(void);
241 #endif // L1_GPRS
242 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38)|| (DSP == 39))&& (CODE_VERSION != SIMULATION))
243 extern void l1_api_dump(void);
244 #endif
245
246 #if (TRACE_TYPE==3)
247 void reset_stats();
248 #endif // TRACE_TYPE
249
250 #if (L1_GTT == 1)
251 extern void l1gtt_initialize_var(void);
252 #endif
253
254 #if (L1_MP3 == 1)
255 extern void l1mp3_initialize_var(void);
256 #endif
257
258 #if (L1_MIDI == 1)
259 extern void l1midi_initialize_var(void);
260 #endif
261 //ADDED FOR AAC
262 #if (L1_AAC == 1)
263 extern void l1aac_initialize_var(void);
264 #endif
265
266 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7))
267 extern void L1_trace_string(char *s);
268 #endif
269
270 #if (RF_FAM == 60 || RF_FAM == 61)
271 extern const UWORD8 drp_ref_sw[] ;
272 extern T_DRP_REGS_STR *drp_regs;
273 extern T_DRP_SRM_API* drp_srm_api;
274
275 extern T_DRP_SW_DATA drp_sw_data_calib;
276 extern T_DRP_SW_DATA drp_sw_data_init;
277
278 #endif
279
280 /*-------------------------------------------------------*/
281 /* l1_dsp_init() */
282 /*-------------------------------------------------------*/
283 /* Parameters : */
284 /* Return : */
285 /* Functionality : */
286 /*-------------------------------------------------------*/
287 void l1_dsp_init(void)
288 {
289 //int i;-OMAPS90550- new
290 #if (CODE_VERSION == SIMULATION)
291 // L1S <-> DSP communication...
292 //====================================================
293 l1s_dsp_com.dsp_ndb_ptr = &(buf.ndb);
294 l1s_dsp_com.dsp_db_r_ptr = &(buf.mcu_rd[0]);
295 l1s_dsp_com.dsp_db_w_ptr = &(buf.mcu_wr[0]);
296 l1s_dsp_com.dsp_param_ptr = &(buf.param);
297 l1s_dsp_com.dsp_w_page = 0;
298 l1s_dsp_com.dsp_r_page = 0;
299 l1s_dsp_com.dsp_r_page_used = 0;
300
301 #if (L1_GPRS)
302 l1ps_dsp_com.pdsp_ndb_ptr = &(buf.ndb_gprs);
303 l1ps_dsp_com.pdsp_db_r_ptr = &(buf.mcu_rd_gprs[0]);
304 l1ps_dsp_com.pdsp_db_w_ptr = &(buf.mcu_wr_gprs[0]);
305 l1ps_dsp_com.pdsp_param_ptr = &(buf.param_gprs);
306 #endif
307
308 // Reset DSP page bit and DSP enable bit...
309 //====================================================
310 l1s_tpu_com.reg_cmd->dsp_enb_bit = OFF;
311 l1s_tpu_com.reg_cmd->dsp_pag_bit = 0;
312
313 // Set EOTD bit if required
314 //====================================================
315 #if (L1_EOTD ==1)
316 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
317 #endif
318
319
320 #else // NO SIMULATION
321
322 // L1S <-> DSP communication...
323 //====================================================
324 l1s_dsp_com.dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR;
325 l1s_dsp_com.dsp_db_r_ptr = (T_DB_DSP_TO_MCU *) DB_R_PAGE_0;
326 l1s_dsp_com.dsp_db_w_ptr = (T_DB_MCU_TO_DSP *) DB_W_PAGE_0;
327 l1s_dsp_com.dsp_param_ptr = (T_PARAM_MCU_DSP *) PARAM_ADR;
328 l1s_dsp_com.dsp_w_page = 0;
329 l1s_dsp_com.dsp_r_page = 0;
330 l1s_dsp_com.dsp_r_page_used = 0;
331
332 #if (DSP == 38) || (DSP == 39)
333 l1s_dsp_com.dsp_db_common_w_ptr = (T_DB_COMMON_MCU_TO_DSP *)DB_COMMON_W_PAGE_0;
334 #endif
335
336 /* DSP CPU load measurement */
337 #if (DSP == 38) || (DSP == 39)
338 l1s_dsp_com.dsp_cpu_load_db_w_ptr = (T_DB_MCU_TO_DSP_CPU_LOAD *)DSP_CPU_LOAD_DB_W_PAGE_0;
339 (*((volatile UWORD16 *)(DSP_CPU_LOAD_MCU_W_CTRL))) = (API)0x0001; // enable DSP CPU load measurement
340 #endif
341
342 #if (L1_GPRS)
343 l1ps_dsp_com.pdsp_ndb_ptr = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS;
344 l1ps_dsp_com.pdsp_db_r_ptr = (T_DB_DSP_TO_MCU_GPRS *) DB_R_PAGE_0_GPRS;
345 l1ps_dsp_com.pdsp_db_w_ptr = (T_DB_MCU_TO_DSP_GPRS *) DB_W_PAGE_0_GPRS;
346 l1ps_dsp_com.pdsp_param_ptr = (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS;
347 #endif
348
349 #if (DSP_DEBUG_TRACE_ENABLE == 1)
350 l1s_dsp_com.dsp_db2_current_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_0;
351 l1s_dsp_com.dsp_db2_other_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_1;
352 #endif
353
354 // Reset DSP page bit and DSP enable bit...
355 //====================================================
356
357 (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) &= ~TPU_CTRL_D_ENBL;
358
359 #if (DSP >= 33)
360 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
361 #else
362 l1s_dsp_com.dsp_param_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
363 #endif
364
365 // NDB init : Reset buffers and set flags...
366 //====================================================
367 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = FB_MODE_1;
368 l1s_dsp_com.dsp_ndb_ptr->d_fb_det = FALSE; // D_FB_DET =0
369 l1s_dsp_com.dsp_ndb_ptr->a_cd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0
370 l1s_dsp_com.dsp_ndb_ptr->a_dd_0[0] = 0; // BLUD = 0
371 l1s_dsp_com.dsp_ndb_ptr->a_dd_0[2] = 0xffff; // NERR = 0xffff
372 l1s_dsp_com.dsp_ndb_ptr->a_dd_1[0] = 0; // BLUD = 0
373 l1s_dsp_com.dsp_ndb_ptr->a_dd_1[2] = 0xffff; // NERR = 0xffff
374 l1s_dsp_com.dsp_ndb_ptr->a_du_0[0] = 0; // BLUD = 0
375 l1s_dsp_com.dsp_ndb_ptr->a_du_0[2] = 0xffff; // NERR = 0xffff
376 l1s_dsp_com.dsp_ndb_ptr->a_du_1[0] = 0; // BLUD = 0
377 l1s_dsp_com.dsp_ndb_ptr->a_du_1[2] = 0xffff; // NERR = 0xffff
378 l1s_dsp_com.dsp_ndb_ptr->a_fd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0
379 l1s_dsp_com.dsp_ndb_ptr->a_fd[2] = 0xffff; // NERR = 0xffff
380 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = 0;
381
382 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
383 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = 0x0800; // Analog base band selected = Nausica, Iota, Syren (bit 11)
384 #endif
385
386 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
387 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits - 4) & 0x000F) << 7); //Bit 7..10: guard bits
388 #endif
389 #if (ANALOG == 11)
390 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits) & 0x000F) << 7); //Bit 7..10: guard bits
391 #endif
392
393 #if (DSP == 32)
394 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= 0x2;
395 #endif // OP_WCP
396
397 l1s_dsp_com.dsp_ndb_ptr->a_sch26[0] = (1<<B_SCH_CRC);// B_SCH_CRC =1, BLUD =0
398 l1audio_dsp_init();
399
400 #if IDS
401 l1s_dsp_com.dsp_ndb_ptr->d_ra_conf = 0; // IDS
402 l1s_dsp_com.dsp_ndb_ptr->d_ra_act = 0; // IDS
403 l1s_dsp_com.dsp_ndb_ptr->d_ra_test = 0; // IDS
404 l1s_dsp_com.dsp_ndb_ptr->d_ra_statu = 0; // IDS
405 l1s_dsp_com.dsp_ndb_ptr->d_ra_statd = 0; // IDS
406 l1s_dsp_com.dsp_ndb_ptr->d_fax = 0; // IDS
407 #endif
408
409 #if(RF_FAM != 61)
410 // interrupt rif TX on FIFO <= threshold with threshold = 0
411 l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179;
412 #else
413 // l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179; TBD put hte replacement here... Danny
414
415 #endif
416
417 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
418 // Initialize V42b variables
419 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego0 = 0;
420 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego1 = 0;
421 l1s_dsp_com.dsp_ndb_ptr->d_v42b_control = 0;
422 l1s_dsp_com.dsp_ndb_ptr->d_v42b_ratio_ind = 0;
423 l1s_dsp_com.dsp_ndb_ptr->d_mcu_control = 0;
424 l1s_dsp_com.dsp_ndb_ptr->d_mcu_control_sema = 0;
425
426 #if !(W_A_DSP_SR_BGD)
427 // Initialize background control variable to No background. Background tasks can be launch in GPRS
428 // as in GSM.
429 l1s_dsp_com.dsp_ndb_ptr->d_max_background = 0;
430 #endif
431
432 #if (L1_GPRS)
433 #if (DSP == 36) || (DSP == 37)
434 // Initialize GEA module
435 l1ps_dsp_com.pdsp_ndb_ptr->d_gea_mode = 0;
436 #endif
437 #endif
438
439 #else
440 #if (L1_GPRS)
441 // Initialize background control variable to No background
442 l1ps_dsp_com.pdsp_ndb_ptr->d_max_background = 0;
443 #endif
444 #endif
445
446 #if (L1_GPRS)
447 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = GSM_SCHEDULER;
448
449 // Initialize the poll response buffer to "no poll request"
450 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS_NONE_TYPE;
451 #else // L1_GPRS
452 #if ((DSP == 31) || (DSP == 32) || (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39))
453 l1s_dsp_com.dsp_ndb_ptr->d_sched_mode_gprs_ovly = GSM_SCHEDULER;
454 #endif
455 #endif // L1_GPRS
456
457 // Set EOTD bit if required
458 //=============================================
459 #if (L1_EOTD ==1)
460 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
461 #endif // L1_EOTD
462
463 #if (DSP == 33)
464 #if DCO_ALGO
465 // Set DCO bit
466 if (l1_config.params.dco_enabled == TRUE)
467 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON;
468 #endif
469 #endif
470
471 // DCO algo in case of DSP 17/32
472 #if (DCO_ALGO == 1)
473 #if ((DSP == 17)||(DSP == 32))
474 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON;
475 #endif // DSP
476 #endif // DCO_ALGO
477
478 #if ((DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38)) || (DSP == 39)
479 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = 0;
480 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = 0;
481 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = 0;
482 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = 0;
483 #endif
484
485 #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
486 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_afs = 400; // thresh detection ONSET AFS
487 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_first_afs = 150; // thresh detection SID_FIRST AFS
488 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_afs = 450; // thresh detection RATSCCH AFS
489 l1s_dsp_com.dsp_ndb_ptr->d_thr_update_afs = 300; // thresh detection SID_UPDATE AFS
490 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_ahs = 200; // thresh detection ONSET AHS
491 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_ahs = 150; // thresh detection SID frames AHS
492 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_marker = 500; // thresh detection RATSCCH MARKER
493 l1s_dsp_com.dsp_ndb_ptr->d_thr_sp_dgr = 3; // thresh detection SPEECH DEGRADED/NO_DATA
494 l1s_dsp_com.dsp_ndb_ptr->d_thr_soft_bits = 0; // thresh detection SPEECH DEGRADED/NO_DATA
495 #endif
496
497 #if ((DSP==36 || (DSP == 37) || (DSP == 38) || (DSP == 39))&&(W_A_AMR_THRESHOLDS==1))
498 // init of the afs thresholds parameters
499 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[0]=0;
500 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[1]=0;
501 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[2]=0;
502 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[3]=0;
503 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[4]=0;
504 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[5]=0;
505 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[6]=0;
506 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[7]=1950;
507
508 // init of the ahs thresholds parameters
509 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[0]=1500;
510 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[1]=1500;
511 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[2]=1500;
512 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[3]=1500;
513 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[4]=1500;
514 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[5]=1500;
515 #endif
516
517 // init of of the threshold for USF detection
518 #if (L1_FALSE_USF_DETECTION == 1)
519 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2300;
520 #else
521 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 0;
522 #endif
523
524 #if (CHIPSET == 12) || (CHIPSET == 15)
525 #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
526 l1s_dsp_com.dsp_ndb_ptr->d_cport_init = 0;
527 #endif
528 #endif
529
530 #if ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 or locosto
531 #if (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
532 // Note: for locosto there is only one MCSI port
533 l1s_dsp_com.dsp_ndb_ptr->d_mcsi_select = MCSI_PORT1;
534 #endif
535
536 #if(DSP == 36) || (DSP == 37)
537 l1s_dsp_com.dsp_ndb_ptr->d_vol_ul_level = 0x1000;
538 l1s_dsp_com.dsp_ndb_ptr->d_vol_dl_level = 0x1000;
539 l1s_dsp_com.dsp_ndb_ptr->d_vol_speed = 0x68;
540 l1s_dsp_com.dsp_ndb_ptr->d_sidetone_level = 0;
541 #endif
542 #endif // ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1)))
543
544 // DB Init DB : Reset all pages, set TX power and reset SCH buffer...
545 //====================================================
546 l1s_reset_db_mcu_to_dsp((T_DB_MCU_TO_DSP *) DB_W_PAGE_0);
547 l1s_reset_db_mcu_to_dsp((T_DB_MCU_TO_DSP *) DB_W_PAGE_1);
548 l1s_reset_db_dsp_to_mcu((T_DB_DSP_TO_MCU *) DB_R_PAGE_0);
549 l1s_reset_db_dsp_to_mcu((T_DB_DSP_TO_MCU *) DB_R_PAGE_1);
550 #if (DSP == 38) || (DSP == 39)
551 l1s_reset_db_common_mcu_to_dsp((T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_0);
552 l1s_reset_db_common_mcu_to_dsp((T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_1);
553 #endif
554
555 #endif // NO_SIMULATION
556
557 #if ((DSP==17)||(DSP == 32))
558 // init the DC offset values
559 l1s_dsp_com.dsp_ndb_ptr->d_dco_type = 0x0000; // Tide off
560 l1s_dsp_com.dsp_ndb_ptr->p_start_IQ = 0x0000;
561 l1s_dsp_com.dsp_ndb_ptr->d_level_off = 0x0000;
562 l1s_dsp_com.dsp_ndb_ptr->d_dco_dbg = 0x0000;
563 l1s_dsp_com.dsp_ndb_ptr->d_tide_resa = 0x0000;
564 #endif
565
566 //Initialize DSP DCO
567 #if (((DSP == 38) || (DSP == 39)) && (RF_FAM == 61))
568 l1s_dsp_com.dsp_ndb_ptr->d_dco_samples_per_symbol = C_DCO_SAMPLES_PER_SYMBOL;
569 l1s_dsp_com.dsp_ndb_ptr->d_dco_fcw = C_DCO_FCW;
570
571 // APCDEL1 will be initialized on rach only ....
572 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1 = l1_config.params.apcdel1;
573 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
574 // APCCTRL2 alone initialize on the next TDMA frame possible
575 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2);
576
577 l1dapc_init_ramp_tables();
578
579 #if ((FF_REPEATED_SACCH == 1) || (FF_REPEATED_DL_FACCH == 1 ))
580
581 /* Chase combining feature flag Initialise */
582 l1s_dsp_com.dsp_ndb_ptr->d_chase_comb_ctrl |= 0x0001;
583 #endif /* FF_REPEATED_SACCH or FF_REPEATED_DL_FACCH */
584
585 #endif // DSP == 38
586
587 // Intialize the AFC
588 #if (DSP == 38) || (DSP == 39)
589 #if (CODE_VERSION != SIMULATION)
590 l1s_dsp_com.dsp_ndb_ptr->d_drp_afc_add_api = C_DRP_DCXO_XTAL_DSP_ADDRESS;
591 #endif
592
593 #if (L1_DRP_IQ_SCALING == 1)
594 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 1;
595 #else
596 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 0;
597 #endif
598 #endif
599
600 }
601
602 /*-------------------------------------------------------*/
603 /* l1_tpu_init() */
604 /*-------------------------------------------------------*/
605 /* Parameters : */
606 /* Return : */
607 /* Functionality : */
608 /*-------------------------------------------------------*/
609 void l1_tpu_init(void)
610 {
611 #if (CODE_VERSION == SIMULATION)
612 // L1S -> TPU communication...
613 //=============================
614 l1s_tpu_com.tpu_w_page = 0;
615 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
616 l1s_tpu_com.reg_cmd = (T_reg_cmd*) &(hw.reg_cmd);
617 l1s_tpu_com.reg_com_int = &(hw.reg_com_int);
618 l1s_tpu_com.offset = &(hw.offset);
619
620 // Reset TPU.
621 //=============================
622 *(l1s_tpu_com.offset) = 0;
623 *(l1s_tpu_com.reg_com_int) = 0;
624 l1s_tpu_com.reg_cmd->tpu_idle_bit = OFF;
625 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
626 l1s_tpu_com.reg_cmd->tpu_stat_bit = OFF;
627 l1s_tpu_com.reg_cmd->tpu_reset_bit = OFF;
628 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
629
630 // Init. OFFSET and SYNC registers
631 //================================
632 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // bit TPU_RESET active
633 l1dmacro_synchro(IMM, 0); // OFFSET=SYNCHRO=0 without any AT
634 l1dtpu_end_scenario(); // Close TPU scenario
635
636 #else
637 // bit TPU_RESET set
638 // OFFSET and SYNCHRO initialized at 0
639 // TSP_ACT bits reset
640 // Sleep added and TPU_ENABLE set...
641 l1dmacro_init_hw();
642
643 l1s_tpu_com.reg_cmd = (UWORD16 *) TPU_CTRL;
644 #endif
645 }
646
647 void l1_tpu_init_light(void)
648 {
649 #if (CODE_VERSION == SIMULATION)
650 // L1S -> TPU communication...
651 //=============================
652 l1s_tpu_com.tpu_w_page = 0;
653 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
654 l1s_tpu_com.reg_cmd = (T_reg_cmd*) &(hw.reg_cmd);
655 l1s_tpu_com.reg_com_int = &(hw.reg_com_int);
656 l1s_tpu_com.offset = &(hw.offset);
657
658 // Reset TPU.
659 //=============================
660 *(l1s_tpu_com.offset) = 0;
661 *(l1s_tpu_com.reg_com_int) = 0;
662 l1s_tpu_com.reg_cmd->tpu_idle_bit = OFF;
663 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
664 l1s_tpu_com.reg_cmd->tpu_stat_bit = OFF;
665 l1s_tpu_com.reg_cmd->tpu_reset_bit = OFF;
666 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
667
668 // Init. OFFSET and SYNC registers
669 //================================
670 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // bit TPU_RESET active
671 l1dmacro_synchro(IMM, 0); // OFFSET=SYNCHRO=0 without any AT
672 l1dtpu_end_scenario(); // Close TPU scenario
673
674 #else
675 // bit TPU_RESET set
676 // OFFSET and SYNCHRO initialized at 0
677 // TSP_ACT bits reset
678 // Sleep added and TPU_ENABLE set...
679 l1dmacro_init_hw_light();
680
681 l1s_tpu_com.reg_cmd = (UWORD16 *) TPU_CTRL;
682 #endif
683 }
684
685 /*-------------------------------------------------------*/
686 /* l1_abb_power_on() */
687 /*-------------------------------------------------------*/
688 /* Parameters : */
689 /* Return : */
690 /* Functionality : */
691 /* Initialize the global structure for spi communication */
692 /* with ABB. */
693 /* Set up ABB connection (CLK 13M free) */
694 /* Aknowledge the ABB status register */
695 /* Configure ABB modules */
696 /* Program the ramp parameters into the NDB */
697 /* Load in the NDB registers' value to be programmed in */
698 /* ABB at first communication it */
699 /*-------------------------------------------------------*/
700
701 //Locosto This funciton would change drastically due to Triton introduction and instead of SPI we have i2c
702 void l1_abb_power_on(void)
703 {
704 #if (CODE_VERSION != SIMULATION)
705 #if (CHIPSET != 15)
706 T_SPI_DEV *Abb;
707 T_SPI_DEV init_spi_device;
708 UWORD16 Abb_Status;
709 T_NDB_MCU_DSP * dsp_ndb_ptr;
710
711 Abb = &init_spi_device; /* Pointer initialization to device communication structure */
712 Abb->PrescVal = SPI_CLOCK_DIV_1; /* ABB transmission parameters initialization */
713 Abb->DataTrLength = SPI_WNB_15;
714 Abb->DevAddLength = 5;
715 Abb->DevId = ABB;
716 Abb->ClkEdge = SPI_CLK_EDG_RISE;
717 Abb->TspEnLevel = SPI_NTSPEN_NEG_LEV;
718 Abb->TspEnForm = SPI_NTSPEN_LEV_TRIG;
719
720 SPI_InitDev(Abb); /* Initialize the spi to work with ABB */
721
722 ABB_free_13M(); /* Set up Abb connection (CLK 13M free).*/
723 Abb_Status = ABB_Read_Status(); /* Aknowledge the Abb status register. */
724
725 /*------------------------------------------------------------------*/
726 /* Add here SW to manage Abb VRPCSTS status register informations */
727 /*------------------------------------------------------------------*/
728
729 ABB_Read_Register_on_page(PAGE0,ITSTATREG); /* Aknowledge the interrupt status register */
730 /* to clear any pending interrupt */
731
732 ABB_on(AFC | MADC, l1a_l1s_com.recovery_flag);
733
734 // ADC init: Configuration of the channels to be converted and enable the ADC Interrupt
735 ABB_Conf_ADC(ALL,EOC_INTENA);
736
737 //in case of reset due to a recovery process do not create the HISR
738 if (l1a_l1s_com.recovery_flag == FALSE)
739 {
740 Create_ABB_HISR();
741 }
742
743 // Load RAMP up/down in NDB memory...
744 dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR;
745
746 if (l1_config.tx_pwr_code == 0)
747 {
748 Cust_get_ramp_tab(dsp_ndb_ptr->a_ramp,
749 0 /* not used */,
750 0 /* not used */,
751 1 /* arbitrary value for arfcn*/);
752 }
753 else
754 {
755 Cust_get_ramp_tab(dsp_ndb_ptr->a_ramp,
756 5 /* arbitrary value working in any case */,
757 5 /* arbitrary value working in any case */,
758 1 /* arbitrary value for arfcn*/);
759 }
760 #endif
761
762
763 #if (ANALOG == 1)
764 // Omega registers values will be programmed at 1st DSP communication interrupt
765
766 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
767 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
768 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
769 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
770 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
771 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
772 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
773 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
774 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
775 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
776 dsp_ndb_ptr->d_vbctrl = l1_config.params.vbctrl; // VULSWITCH=0, VDLAUX=1, VDLEAR=1.
777
778 // APCDEL1 will be initialized on rach only ....
779 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
780
781 #if (DSP >= 33)
782 // To increase the robustness the IOTA register are reseted to 0
783 // if OMEGA, NAUSICA is used
784 dsp_ndb_ptr->d_bulgcal = 0x0000;
785 dsp_ndb_ptr->d_vbctrl2 = 0x0000;
786 dsp_ndb_ptr->d_apcdel2 = 0x0000;
787 #endif
788 #endif
789 #if (ANALOG == 2)
790 // Iota registers values will be programmed at 1st DSP communication interrupt
791
792 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
793 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
794 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
795 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
796 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
797 dsp_ndb_ptr->d_bulgcal = l1_config.params.bulgcal; // value at reset
798 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
799 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
800 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
801 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
802 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
803 dsp_ndb_ptr->d_vbctrl1 = l1_config.params.vbctrl1; // VULSWITCH=0, VDLAUX=1, VDLEAR=1.
804 dsp_ndb_ptr->d_vbctrl2 = l1_config.params.vbctrl2; // MICBIASEL=0, VDLHSO=0, MICAUX=0
805
806 // APCDEL1 will be initialized on rach only ....
807 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
808 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
809 #endif
810 #if (ANALOG == 3)
811 // Syren registers values will be programmed at 1st DSP communication interrupt
812
813 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
814 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
815 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
816 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
817 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
818 dsp_ndb_ptr->d_bulgcal = l1_config.params.bulgcal; // value at reset
819 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
820 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
821 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
822 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
823 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
824 dsp_ndb_ptr->d_vbctrl1 = l1_config.params.vbctrl1; // VULSWITCH=0
825 dsp_ndb_ptr->d_vbctrl2 = l1_config.params.vbctrl2; // MICBIASEL=0, VDLHSO=0, MICAUX=0
826
827 // APCDEL1 will be initialized on rach only ....
828 dsp_ndb_ptr->d_apcdel1 = l1_config.params.apcdel1;
829 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
830
831 // Additional registers management brought by SYREN
832 dsp_ndb_ptr->d_vbpop = l1_config.params.vbpop; // HSOAUTO enabled only
833 dsp_ndb_ptr->d_vau_delay_init = l1_config.params.vau_delay_init; // vaud_init_delay init 2 frames
834 dsp_ndb_ptr->d_vaud_cfg = l1_config.params.vaud_cfg; // Init to zero
835 dsp_ndb_ptr->d_vauo_onoff = l1_config.params.vauo_onoff; // Init to zero
836 #if ((L1_AUDIO_MCU_ONOFF == 1)&&(OP_L1_STANDALONE == 1)&&(CHIPSET == 12))
837 ABB_Write_Register_on_page(PAGE1, VAUOCTRL, 0x0015A);
838 #endif // E Sample testing of audio on off
839 dsp_ndb_ptr->d_vaus_vol = l1_config.params.vaus_vol; // Init to zero
840 dsp_ndb_ptr->d_vaud_pll = l1_config.params.vaud_pll; // Init to zero
841 dsp_ndb_ptr->d_togbr2 = 0; // TOGBR2 initial value handled by the DSP (this value doesn't nake any sense)
842
843 #endif
844
845 #if (ANALOG == 11)
846 // The following settings need to be done only in L1 StandALoen as PSP would
847 // do in the case of full PS Build...
848
849 //Set the CTRL3 register
850 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,
851 l1_config.params.ctrl3,NULL);
852
853 #if (OP_L1_STANDALONE == 1)
854 // THESE REGISTERS ARE INITIALIZED IN STANDALONE AND PS BUILDS FOR AUDIO PATH
855
856 // ************ START REG INIT FOR PS build/STANDALONE *************
857 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_TOGB_OFFSET,
858 0x15,NULL);
859 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_VULGAIN_OFFSET,
860 l1_config.params.vulgain,NULL);
861 //Set the VDLGAIN register
862 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_VDLGAIN_OFFSET,
863 l1_config.params.vdlgain,NULL);
864 //Set the SIDETONE register
865 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_SIDETONE_OFFSET,
866 l1_config.params.sidetone,NULL);
867 //Set the CTRL1 register
868 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL1_OFFSET,
869 l1_config.params.ctrl1,NULL);
870 //Set the CTRL2 register
871 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL2_OFFSET,
872 l1_config.params.ctrl2,NULL);
873
874 //Set the CTRL4 register
875 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL4_OFFSET,
876 l1_config.params.ctrl4,NULL);
877 //Set the CTRL5 register
878 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL5_OFFSET,
879 l1_config.params.ctrl5,NULL);
880 //Set the CTRL6 register
881 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL6_OFFSET,
882 l1_config.params.ctrl6,NULL);
883 //Set the POPAUTO register
884 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_POPAUTO_OFFSET,
885 l1_config.params.popauto,NULL);
886
887 // ************ END REG INIT FOR PS build/STANDALONE ****************
888
889
890
891 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
892 l1_config.params.outen1,NULL);
893 //Set the OUTEN2 register
894 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
895 l1_config.params.outen2,NULL);
896 //Set the OUTEN3 register
897 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
898 l1_config.params.outen3,NULL);
899
900
901
902 //Set the AUDLGAIN register
903 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_AUDLGAIN_OFFSET,
904 l1_config.params.aulga,NULL);
905 //Set the AUDRGAIN register
906 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_AUDRGAIN_OFFSET,
907 l1_config.params.aurga,NULL);
908 #endif
909
910
911 #if (OP_L1_STANDALONE == 1)
912 #if (L1_MADC_ON == 1)
913 //MADC Real time initialization for all the 11 ADCs
914 bspTwl3029_Madc_enableRt( NULL, 0x7ff, l1a_madc_callback, &l1_madc_results);
915 #endif
916 #endif
917
918 #endif
919 #endif //CODE_VERSION != SIMULATION
920 }
921
922 /*-------------------------------------------------------*/
923 /* l1_pwr_mgt_init() */
924 /*-------------------------------------------------------*/
925 /* Parameters : */
926 /* ------------- */
927 /* Return : */
928 /* ------------- */
929 /* Description : */
930 /* ------------- */
931 /* This routine is used to initialize the gauging */
932 /* related variables. */
933 /*-------------------------------------------------------*/
934 void l1_pwr_mgt_init(void)
935 {
936
937 //++++++++++++++++++++++++++++++++++++++++++
938 // Power management variables
939 //++++++++++++++++++++++++++++++++++++++++++
940
941 // flags for wake-up ....
942 l1s.pw_mgr.Os_ticks_required = FALSE;
943 l1s.pw_mgr.frame_adjust = FALSE;
944 l1s.pw_mgr.wakeup_time = 0;
945
946 // variables for sleep ....
947 l1s.pw_mgr.sleep_duration = 0;
948 l1s.pw_mgr.sleep_performed = DO_NOT_SLEEP;
949 l1s.pw_mgr.modules_status = 0; // all clocks ON
950 l1s.pw_mgr.paging_scheduled = FALSE;
951
952 #if 0 /* removed in FreeCalypso */
953 // variable for afc bypass mode
954 l1s.pw_mgr.afc_bypass_mode = AFC_BYPASS_MODE;
955 #endif
956
957 // 32 Khz gauging ....
958 l1s.pw_mgr.gaug_count = 0;
959 l1s.pw_mgr.enough_gaug = FALSE;
960 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
961 l1s.force_gauging_next_paging_due_to_CCHR = 0;
962 l1s.pw_mgr.gauging_task = INACTIVE;
963
964 // GAUGING duration
965 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
966 if (l1_config.dpll <8 )
967 l1s.pw_mgr.gaug_duration = 9; // 9 frames (no more CTRL with DSP)
968 else // with a dpll >= 104Mhz the HF counter is too small: gauging limitation to 6 frames.
969 #if(CHIPSET == 15)
970 // Gauging duration could be reduced to 4 frames (from 5 frames) as fast paging (FF_L1_FAST_DECODING) is available
971 l1s.pw_mgr.gaug_duration = 4; // 4 frames
972 #else
973 l1s.pw_mgr.gaug_duration = 6; // 6 frames
974 #endif
975 #else
976 l1s.pw_mgr.gaug_duration = 11; // 1CTRL + 9 frames +1CTRL
977 #endif
978
979
980 //-------------------------------------------------
981 // INIT state:
982 // 32.768Khz is in the range [-500 ppm,+100 ppm]
983 // due to temperature variation.
984 // LF_100PPM = 32.7712768 Khz
985 // LF_500PPM = 32.751616 Khz
986 //
987 // ACQUIS STATE :
988 // 32.768Khz variations allowed from INIT value
989 // are [-50 ppm,+50ppm]. Same delta on ideal 32khz
990 // during 9 frames (gauging duration) represents 1348*T32.
991 // LF_50PPM = 32.7696384 Khz
992 // 1348/32.768 - 1348/32.7696384 = 0.002056632 ms
993 // At 78 Mhz it means : 0.002056632ms/0.000012820513ms= 160 T
994 //
995 // UPDATE state :
996 // allowed variations are [-6 ppm,+6ppm] jitter
997 // LF_6PPM = 32.76819661 Khz
998 // 1348/32.768 - 1348/32.76819661 = 0.00024691 ms
999 // At 78 Mhz it means : 0.00024691 / 0.000012820513ms= 19 T
1000 //
1001 // 78 Mhz 65 Mhz 84.5 Mhz
1002 // ===========================
1003 // C_CLK_MIN 2380 1983 2578
1004 // C_CLK_INIT_MIN 8721 29113 31293
1005 // C_CLK_MAX 2381 1984 2580
1006 // C_CLK_INIT_MAX 36823 41608 1662
1007 // C_DELTA_HF_ACQUIS 160 130 173
1008 // C_DELTA_HF_UPDATE 19 15 20
1009 //-------------------------------------------------
1010 #if ((CHIPSET == 2) || (CHIPSET == 3) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
1011 l1s.pw_mgr.c_clk_min = C_CLK_MIN;
1012 l1s.pw_mgr.c_clk_init_min = C_CLK_INIT_MIN;
1013 l1s.pw_mgr.c_clk_max = C_CLK_MAX;
1014 l1s.pw_mgr.c_clk_init_max = C_CLK_INIT_MAX;
1015 l1s.pw_mgr.c_delta_hf_acquis = C_DELTA_HF_ACQUIS;
1016 l1s.pw_mgr.c_delta_hf_update = C_DELTA_HF_UPDATE;
1017 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
1018 // 78000/32.7712768 = 2380.13308
1019 l1s.pw_mgr.c_clk_min = (UWORD32)((l1_config.dpll*MCUCLK)/LF_100PPM);
1020 // 0.13308*2^16
1021 l1s.pw_mgr.c_clk_init_min =(UWORD32) ((UWORD32)((UWORD32)(((UWORD32)(l1_config.dpll*MCUCLK))-
1022 (l1s.pw_mgr.c_clk_min*LF_100PPM))*
1023 65536)/LF_100PPM); //omaps00090550
1024
1025 // 78000/32.751616 = 2381.561875
1026 l1s.pw_mgr.c_clk_max = (UWORD32)((l1_config.dpll*MCUCLK)/LF_500PPM); //omaps00090550
1027 // 0.561875*2^16
1028 l1s.pw_mgr.c_clk_init_max =(UWORD32)((UWORD32)(((double)(l1_config.dpll*MCUCLK)-
1029 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))*
1030 65536)/LF_500PPM);//omaps00090550
1031
1032 // remember hf is expressed in nbr of clock in hz (ex 65Mhz,104Mhz)
1033 l1s.pw_mgr.c_delta_hf_acquis =(UWORD32) (((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_50PPM))*(l1_config.dpll*MCUCLK));//omaps00090550
1034 l1s.pw_mgr.c_delta_hf_update =(UWORD32)( ((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_6PPM ))*(l1_config.dpll*MCUCLK));//omaps00090550
1035 #endif
1036
1037 } /* l1_pwr_mgt_init() */
1038
1039 /*-------------------------------------------------------*/
1040 /* l1_initialize_var() */
1041 /*-------------------------------------------------------*/
1042 /* Parameters : */
1043 /* ------------- */
1044 /* Return : */
1045 /* ------------- */
1046 /* Description : */
1047 /* ------------- */
1048 /* This routine is used to initialize the l1a, l1s and */
1049 /* l1a_l1s_com global structures. */
1050 /*-------------------------------------------------------*/
1051 void l1_initialize_var(void)
1052 {
1053 UWORD32 i;
1054 UWORD8 task_id;
1055
1056 //++++++++++++++++++++++++++++++++++++++++++
1057 // Power management variables
1058 //++++++++++++++++++++++++++++++++++++++++++
1059 l1_pwr_mgt_init();
1060
1061 //++++++++++++++++++++++++++++++++++++++++++
1062 // Reset "l1s" structure.
1063 //++++++++++++++++++++++++++++++++++++++++++
1064
1065 // time counter used for debug and by L3 scenario...
1066 l1s.debug_time = 0;
1067
1068 // L1S tasks management...
1069 //-----------------------------------------
1070 for(task_id=0; task_id<NBR_DL_L1S_TASKS; task_id++)
1071 {
1072 if (!((task_id == ADC_CSMODE0) && (l1a_l1s_com.recovery_flag != FALSE)))
1073 {
1074 l1s.task_status[task_id].new_status = NOT_PENDING;
1075 l1s.task_status[task_id].current_status = INACTIVE;
1076 }
1077 }
1078 l1s.frame_count = 0;
1079 l1s.forbid_meas = 0;
1080 #if L1_GPRS
1081 l1s.tcr_prog_done=0;
1082 #endif
1083 #if (AUDIO_DEBUG == 1)
1084 audio_reg_read_status=0;
1085 #endif
1086 // MFTAB management variables...
1087 //-----------------------------------------
1088 l1s.afrm = 0;
1089 l1s_clear_mftab(l1s.mftab.frmlst);
1090
1091 // Controle parameters... (miscellaneous)
1092 //-----------------------------------------
1093 #if (RF_FAM != 61)
1094 l1s.afc = ((WORD16)l1_config.params.eeprom_afc>>3); //F13.3 -> F16.0
1095 #endif
1096 #if (RF_FAM == 61)
1097 l1s.afc = ((WORD16)l1_config.params.eeprom_afc>>2); //F13.3 -> F14.0
1098 #endif
1099
1100
1101 l1s.afc_frame_count = 0;
1102
1103 #if (TOA_ALGO == 2)
1104 l1s.toa_var.toa_shift = ISH_INVALID;
1105 l1s.toa_var.toa_snr_mask = 0;
1106 l1s.toa_var.toa_frames_counter = 0;
1107 l1s.toa_var.toa_accumul_counter = 0;
1108 l1s.toa_var.toa_accumul_value = 0;
1109 l1s.toa_var.toa_update_fn = 0;
1110 l1s.toa_var.toa_update_flag = FALSE;
1111 #else
1112 l1s.toa_shift = ISH_INVALID;
1113 l1s.toa_snr_mask = 0;
1114 #if L1_GPRS
1115 l1s.toa_period_count = 0;
1116 l1s.toa_update = FALSE;
1117 #endif
1118 #endif
1119
1120 #if (L1_GPRS == 1)
1121 l1s.algo_change_synchro_active = FALSE;
1122 #endif
1123
1124 #if (L1_RF_KBD_FIX == 1)
1125 l1s.total_kbd_on_time = 5000;
1126 l1s.correction_ratio = 1;
1127 #endif
1128 /* Initialising the repeated SACCH variables */
1129 #if (FF_REPEATED_SACCH == 1 )
1130 l1s.repeated_sacch.srr = 0;/* SACCH Repetiton Request */
1131 l1s.repeated_sacch.sro = 0;/* SACCH Repetiton Order */
1132 l1s.repeated_sacch.buffer_empty = TRUE;
1133 #endif /* FF_REPEATED_SACCH ==1*/
1134
1135 #if (FF_REPEATED_DL_FACCH == 1)
1136 l1s.repeated_facch.pipeline[0].buffer_empty=l1s.repeated_facch.pipeline[1].buffer_empty=TRUE;
1137 l1s.repeated_facch.counter_candidate=0;
1138 l1s.repeated_facch.counter=1;
1139 #endif/* (FF_REPEATED_DL_FACCH == 1) */
1140
1141 // Init the spurious_fb_detected flag
1142 l1s.spurious_fb_detected = FALSE;
1143
1144 // Flag registers for RF task controle...
1145 //-----------------------------------------
1146 l1s.tpu_ctrl_reg = 0;
1147 l1s.dsp_ctrl_reg = 0;
1148
1149 // Serving...
1150 //============
1151
1152 // Serving frame number management.
1153 //---------------------------------
1154 if (l1a_l1s_com.recovery_flag == FALSE)
1155 {
1156 l1s.actual_time.tc = 0;
1157 l1s.actual_time.fn = 0;
1158 l1s.actual_time.t1 = 0;
1159 l1s.actual_time.t2 = 0;
1160 l1s.actual_time.t3 = 0;
1161 l1s.actual_time.fn_in_report = 0;
1162 l1s.actual_time.fn_mod42432 = 0;
1163
1164 l1s.next_time.tc = 0;
1165 l1s.next_time.fn = 0;
1166 l1s.next_time.t1 = 0;
1167 l1s.next_time.t2 = 0;
1168 l1s.next_time.t3 = 0;
1169 l1s.next_time.fn_in_report = 0;
1170 l1s.next_time.fn_mod42432 = 0;
1171
1172 #if L1_GPRS
1173 l1s.actual_time.block_id = 0;
1174 l1s.next_time.block_id = 0;
1175 l1s.next_plus_time = l1s.next_time;
1176 l1s_increment_time(&(l1s.next_plus_time),1);
1177 l1s.ctrl_synch_before = FALSE;
1178 l1s.next_gauging_scheduled_for_PNP= 0;
1179 #endif
1180 }
1181
1182 // TXPWR management.
1183 //-------------------
1184 l1s.reported_txpwr = 0;
1185 l1s.applied_txpwr = 0;
1186
1187 // Last RXQUAL value.
1188 //-------------------
1189 l1s.rxqual = 0;
1190
1191 // Hardware info.
1192 //---------------
1193 l1s.tpu_offset = 0;
1194 l1s.tpu_offset_hw = 0;
1195
1196 l1s.tpu_win = 0;
1197
1198 // Initialize TXPWR info.
1199 l1s.last_used_txpwr = NO_TXPWR;
1200
1201 #if (AMR == 1)
1202 // Reset DTX AMR status
1203 //---------------------
1204 l1s.dtx_amr_dl_on=FALSE;
1205 #endif
1206
1207 // Code version structure
1208 //-------------------------
1209
1210 // DSP versions & checksum
1211 l1s.version.dsp_code_version = 0;
1212 l1s.version.dsp_patch_version = 0;
1213 l1s.version.dsp_checksum = 0; // checksum patch+code DSP
1214
1215 l1s.version.mcu_tcs_program_release = PROGRAM_RELEASE_VERSION;
1216 l1s.version.mcu_tcs_internal = INTERNAL_VERSION;
1217 l1s.version.mcu_tcs_official = MAINTENANCE_VERSION;
1218
1219 #if TESTMODE
1220 l1s.version.mcu_tm_version = TESTMODEVERSION;
1221 #else
1222 l1s.version.mcu_tm_version = 0;
1223 #endif
1224
1225 //++++++++++++++++++++++++++++++++++++++++++
1226 // Reset "l1a" structure.
1227 //++++++++++++++++++++++++++++++++++++++++++
1228
1229 // Downlink tasks management...
1230 // Uplink tasks management...
1231 // Measurement tasks management...
1232 //-----------------------------------------
1233
1234 if (l1a_l1s_com.recovery_flag == FALSE)
1235 {
1236 for(i=0; i<NBR_L1A_PROCESSES; i++)
1237 {
1238 l1a.l1a_en_meas[i] = 0;
1239 l1a.state[i] = 0; // RESET state.
1240 }
1241 }
1242 else
1243 {
1244 // L1A state for full list meas has to be maintained in case of recovery
1245 for(i=0; i<NBR_L1A_PROCESSES; i++)
1246 {
1247 if ((i != FULL_MEAS) && (i!= I_ADC))
1248 {
1249 l1a.l1a_en_meas[i] = 0;
1250 l1a.state[i] = 0; // RESET state.
1251 }
1252 }
1253 }
1254
1255 l1a.confirm_SignalCode = 0;
1256
1257 // Flag for forward/delete message management.
1258 //---------------------------------------------
1259 if (l1a_l1s_com.recovery_flag == FALSE)
1260 {
1261 l1a.l1_msg_forwarded = 0;
1262 }
1263
1264 #if (L1_VOCODER_IF_CHANGE == 1)
1265 // Reset new vocoder interface L1A global variables: automatic disabling and vocoder enabling flag.
1266 l1a.vocoder_state.automatic_disable = FALSE;
1267 l1a.vocoder_state.enabled = FALSE;
1268 #endif // if L1_VOCODER_IF_CHANGE == 1
1269 //++++++++++++++++++++++++++++++++++++++++++
1270 // Reset "l1a_l1s_com" structure.
1271 //++++++++++++++++++++++++++++++++++++++++++
1272
1273 l1a_l1s_com.l1a_activity_flag = TRUE;
1274 l1a_l1s_com.time_to_next_l1s_task = 0;
1275
1276 // Serving Cell...
1277 //=================
1278
1279 // Serving Cell identity and information.
1280 //---------------------------------------
1281 l1a_reset_cell_info(&(l1a_l1s_com.Scell_info));
1282
1283 l1a_l1s_com.Smeas_dedic.acc_sub = 0;
1284 l1a_l1s_com.Smeas_dedic.nbr_meas_sub = 0;
1285 l1a_l1s_com.Smeas_dedic.qual_acc_full = 0;
1286 l1a_l1s_com.Smeas_dedic.qual_acc_sub = 0;
1287 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_full = 0;
1288 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_sub = 0;
1289 l1a_l1s_com.Smeas_dedic.dtx_used = 0;
1290
1291 #if REL99
1292 #if FF_EMR
1293 // Serving Cell identity EMR information.
1294 //---------------------------------------
1295 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_acc = 0;
1296 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_nbr_meas = 0;
1297 l1a_l1s_com.Smeas_dedic_emr.nbr_rcvd_blocks = 0;
1298 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_acc = 0;
1299 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_acc = 0;
1300 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_num = 0;
1301 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_num = 0;
1302
1303 #endif
1304 #endif
1305
1306
1307 l1a_l1s_com.Scell_used_IL.input_level = l1_config.params.il_min;
1308 l1a_l1s_com.Scell_used_IL_d.input_level = l1_config.params.il_min;
1309 l1a_l1s_com.Scell_used_IL_dd.input_level = l1_config.params.il_min;
1310
1311 l1a_l1s_com.Scell_used_IL.lna_off = FALSE;
1312 l1a_l1s_com.Scell_used_IL_d.lna_off = FALSE;
1313 l1a_l1s_com.Scell_used_IL_dd.lna_off = FALSE;
1314
1315 // Synchro information.
1316 //---------------------------------------
1317 l1a_l1s_com.tn_difference = 0;
1318 l1a_l1s_com.dl_tn = 0;
1319 #if L1_FF_WA_OMAPS00099442
1320 l1a_l1s_com.change_tpu_offset_flag = FALSE;
1321 #endif
1322
1323 #if L1_GPRS
1324 l1a_l1s_com.dsp_scheduler_mode = GSM_SCHEDULER;
1325 #endif
1326
1327 // Idle parameters.
1328 //-----------------
1329 l1a_l1s_com.nbcchs.schedule_array_size=0;
1330 l1a_l1s_com.ebcchs.schedule_array_size=0;
1331 l1a_l1s_com.bcchn.current_list_size=0;
1332 l1a_l1s_com.nsync.current_list_size=0;
1333
1334 #if (GSM_IDLE_RAM != 0)
1335 l1s.gsm_idle_ram_ctl.l1s_full_exec = TRUE;
1336
1337 #if GSM_IDLE_RAM_DEBUG
1338 #if (CHIPSET == 10) && (OP_WCP == 1)
1339 l1s.gsm_idle_ram_ctl.TC_true_control=0;
1340 #endif // CHIPSET && OP_WCP
1341 #endif // GSM_IDLE_RAM_DEBUG
1342 #endif // GSM_IDLE_RAM
1343
1344 #if (L1_12NEIGH ==1)
1345 for (i=0;i<NBR_NEIGHBOURS+1;i++)
1346 #else
1347 for (i=0;i<6;i++)
1348 #endif
1349 {
1350 l1a_l1s_com.nsync.list[i].status=NSYNC_FREE;
1351 }
1352 for (i=0;i<6;i++)
1353 {
1354 l1a_l1s_com.bcchn.list[i].status=NSYNC_FREE;
1355 }
1356
1357 // EOTD variables
1358 #if (L1_EOTD==1)
1359 l1a_l1s_com.nsync.eotd_meas_session=FALSE;
1360 l1a_l1s_com.nsync.fn_sb_serv;
1361 l1a_l1s_com.nsync.ta_sb_serv;
1362 #endif
1363
1364 // CBCH parameters.
1365 // ----------------
1366 // nothing to reset.
1367
1368 // Random Access information.
1369 // ----------------------------
1370 // nothing to reset.
1371
1372 // ADC management
1373 //---------------
1374 if (l1a_l1s_com.recovery_flag == FALSE)
1375 l1a_l1s_com.adc_mode = ADC_DISABLED;
1376
1377 // TXPWR management.
1378 //-------------------
1379 #if(L1_FF_MULTIBAND == 0)
1380 l1a_l1s_com.powerclass_band1 = 0;
1381 l1a_l1s_com.powerclass_band2 = 0;
1382 #else
1383 for( i = 0; i< (NB_MAX_SUPPORTED_BANDS); i++)
1384 {
1385 l1a_l1s_com.powerclass[i] = 0;
1386 }
1387 #endif
1388
1389 // Dedicated parameters.
1390 //----------------------
1391 l1a_l1s_com.dedic_set.aset = NULL;
1392 l1a_l1s_com.dedic_set.fset = NULL;
1393 l1a_l1s_com.dedic_set.SignalCode = 0;
1394 l1a_l1s_com.dedic_set.sync_tch = 0;
1395 l1a_l1s_com.dedic_set.stop_tch = 0;
1396 l1a_l1s_com.dedic_set.reset_facch = FALSE;
1397 #if (FF_L1_TCH_VOCODER_CONTROL)
1398 l1a_l1s_com.dedic_set.reset_sacch = FALSE;
1399 #if (L1_VOCODER_IF_CHANGE == 0)
1400 l1a_l1s_com.dedic_set.vocoder_on = TRUE;
1401 #if (W_A_DSP_PR20037 == 1)
1402 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ;
1403 #else // W_A_DSP_PR20037 == 0
1404 l1a_l1s_com.dedic_set.start_vocoder = FALSE;
1405 #endif // W_A_DSP_PR20037
1406 #else // L1_VOCODER_IF_CHANGE
1407 l1a_l1s_com.dedic_set.vocoder_on = FALSE;
1408 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_RESET_COMMAND;
1409 #endif // L1_VOCODER_IF_CHANGE
1410 #endif // FF_L1_TCH_VOCODER_CONTROL
1411
1412 l1a_l1s_com.dedic_set.radio_freq = 0;
1413 l1a_l1s_com.dedic_set.radio_freq_d = 0;
1414 l1a_l1s_com.dedic_set.radio_freq_dd = 0;
1415 #if ((REL99 == 1) && (FF_BHO == 1))
1416 // blind handover params in dedic set
1417 // Initialize the handover type to default value that is Normal Handover.
1418 l1a_l1s_com.dedic_set.handover_type = 0;
1419 l1a_l1s_com.dedic_set.long_rem_handover_type = 0;
1420 l1a_l1s_com.dedic_set.bcch_carrier_of_nbr_cell = 0;
1421 l1a_l1s_com.dedic_set.fn_offset = 0;
1422 l1a_l1s_com.dedic_set.time_alignment = 0;
1423 #endif
1424
1425 #if (L1_12NEIGH ==1)
1426 for (i=0;i<NBR_NEIGHBOURS+1;i++)
1427 #else
1428 for (i=0;i<6;i++)
1429 #endif
1430 {
1431 l1a_l1s_com.nsync.list[i].sb26_offset = 0;
1432 }
1433
1434 l1a_l1s_com.dedic_set.pwrc = 0;
1435 l1a_l1s_com.dedic_set.handover_fail_mode = FALSE;
1436 #if (AMR == 1)
1437 l1a_l1s_com.dedic_set.sync_amr = FALSE;
1438 #endif
1439
1440 // Handover parameters.
1441 //---------------------
1442 // nothing to reset.
1443
1444 // Neighbour Cells...
1445 //====================
1446
1447 // FULL list.
1448 //-----------
1449 l1a_reset_full_list();
1450
1451 // BA list.
1452 //---------
1453 l1a_reset_ba_list();
1454 l1a_l1s_com.ba_list.new_list_present = FALSE;
1455
1456 #if L1_GPRS
1457 // Packet measurement: Reset of the frequency list.
1458 //-------------------------------------------------
1459 l1pa_reset_cr_freq_list();
1460 #endif
1461
1462 // L1S scheduler...
1463 //====================
1464
1465 // L1S tasks management...
1466 //-----------------------------------------
1467 {
1468 UWORD8 mem;
1469 mem = l1a_l1s_com.l1s_en_task[ADC_CSMODE0];
1470
1471 for(i=0; i<NBR_DL_L1S_TASKS; i++)
1472 {
1473 l1a_l1s_com.task_param[i] = SEMAPHORE_RESET;
1474 l1a_l1s_com.l1s_en_task[i] = TASK_DISABLED;
1475 }
1476
1477 // in case of recovery do not change the ADC initialization
1478 if (l1a_l1s_com.recovery_flag != FALSE)
1479 l1a_l1s_com.l1s_en_task[ADC_CSMODE0] = mem;
1480 }
1481
1482 // Measurement tasks management...
1483 //-----------------------------------------
1484 l1a_l1s_com.meas_param = 0;
1485 l1a_l1s_com.l1s_en_meas = 0;
1486
1487 // L1 mode...
1488 //-----------------------------------------
1489 if (l1a_l1s_com.recovery_flag == FALSE) // do not restart from CS_MODE0 after a recovery
1490 l1a_l1s_com.mode = CS_MODE0;
1491
1492 // Control algo variables.
1493 //-----------------------------------------
1494 l1a_l1s_com.fb_mode = 0;
1495 l1a_l1s_com.toa_reset = FALSE;
1496
1497 #if(L1_FF_MULTIBAND == 0)
1498 for(i=0; i<=l1_config.std.nbmax_carrier; i++)
1499 #else
1500 for(i=0; i<= NBMAX_CARRIER; i++)
1501 #endif
1502 {
1503 l1a_l1s_com.last_input_level[i].input_level = l1_config.params.il_min;
1504 l1a_l1s_com.last_input_level[i].lna_off = FALSE;
1505 }
1506
1507 #if FF_L1_IT_DSP_DTX
1508 // Fast DTX variables.
1509 //-----------------------------------------
1510 // Clear DTX interrupt condition
1511 l1a_apihisr_com.dtx.pending = FALSE;
1512 // Enable TX activity
1513 l1a_apihisr_com.dtx.tx_active = TRUE;
1514 // No DTX status awaited
1515 l1a_apihisr_com.dtx.dtx_status = DTX_AVAILABLE;
1516 // Fast DTX service latency timer
1517 l1a_apihisr_com.dtx.fast_dtx_ready_timer = 0;
1518 // Fast DTX service available
1519 l1a_apihisr_com.dtx.fast_dtx_ready = FALSE;
1520 #endif
1521 #if L1_RECOVERY
1522 l1s.recovery.frame_count = 0;
1523 #endif
1524
1525 #if (AUDIO_TASK == 1)
1526 l1audio_initialize_var();
1527 #endif
1528
1529 #if (L1_GTT == 1)
1530 l1gtt_initialize_var();
1531 #endif
1532
1533 #if (L1_MP3 == 1)
1534 l1mp3_initialize_var();
1535 #endif
1536
1537 #if (L1_MIDI == 1)
1538 l1midi_initialize_var();
1539 #endif
1540 //ADDED FOR AAC
1541 #if (L1_AAC == 1)
1542 l1aac_initialize_var();
1543 #endif
1544 #if (L1_DYN_DSP_DWNLD == 1)
1545 l1_dyn_dwnld_initialize_var();
1546 #endif
1547 #if (FF_L1_FAST_DECODING == 1)
1548 l1a_apihisr_com.fast_decoding.pending = FALSE;
1549 l1a_apihisr_com.fast_decoding.crc_error = FALSE;
1550 l1a_apihisr_com.fast_decoding.status = 0;
1551 l1a_apihisr_com.fast_decoding.deferred_control_req = FALSE;
1552 l1a_apihisr_com.fast_decoding.task = 0;
1553 l1a_apihisr_com.fast_decoding.burst_id = 0;
1554 l1a_apihisr_com.fast_decoding.contiguous_decoding = FALSE;
1555 #endif /* FF_L1_FAST_DECODING */
1556
1557
1558 #if(L1_CHECK_COMPATIBLE == 1)
1559 l1a.vcr_wait = FALSE;
1560 l1a.stop_req = FALSE;
1561 l1a.vcr_msg_param = TRUE;
1562 l1a.vch_auto_disable = FALSE;
1563
1564 #endif
1565
1566
1567 }
1568
1569
1570 /*---------------------------------------------------------*/
1571 /* l1_dpll_init_var() */
1572 /*---------------------------------------------------------*/
1573 /* Parameters : None */
1574 /* Return : None */
1575 /* Functionality : Initialize L1 DPLL variable for gauging */
1576 /* processing */
1577 /*---------------------------------------------------------*/
1578 void l1_dpll_init_var(void) {
1579
1580 #if (CODE_VERSION != SIMULATION)
1581 // Init DPLL variable
1582 //===================
1583 #if (CHIPSET == 2 || CHIPSET == 3 || CHIPSET == 5 || CHIPSET == 6 || CHIPSET == 9)
1584 l1_config.dpll=PLL;
1585 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
1586 {
1587 UWORD16 dpll_div;
1588 UWORD16 dpll_mul;
1589 #if (CHIPSET == 12)
1590 // not required for Locosto: There is NO CNTL_CLK_DSP in Locosto
1591 double dsp_div = CLKM_GET_DSP_DIV_VALUE;
1592 #endif
1593
1594 dpll_div=DPLL_READ_DPLL_DIV;
1595 dpll_mul=DPLL_READ_DPLL_MUL;
1596
1597 #if (CHIPSET == 12)
1598 // Not required for locsto due to the reason mentioned above.
1599 l1_config.dpll= ((double)(dpll_mul)/(double)(dpll_div+1))/(double)(dsp_div);
1600 #else
1601 l1_config.dpll= (double)(dpll_mul)/(double)(dpll_div+1);
1602 #endif
1603 }
1604 #endif
1605 #endif
1606
1607 } /* l1_dpll_init_var() */
1608
1609 /*-------------------------------------------------------------*/
1610 /* FUNCTION: l1_drp_wrapper_init */
1611
1612 /*-------------------------------------------------------------*/
1613
1614 void l1_drp_wrapper_init (void)
1615 {
1616 #if(RF_FAM == 61)
1617 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2);
1618 #endif
1619
1620 }
1621
1622 /*-------------------------------------------------------------*/
1623 /* FUNCTION: l1_drp_init */
1624 /* Params: Void */
1625 /*
1626 Functionality: This function does the following
1627 1. Initialize Misc variables wrt DRP
1628 2a Copy the RAMP Tables into the DSP MCU API
1629 2b. Initialize other APIs wrt DCO
1630 3. Download Reference Software
1631 4. Call the function to : Start the REG_ON Script in the DRP
1632 */
1633 /*-------------------------------------------------------------*/
1634
1635 #if (L1_DRP == 1)
1636 #if (DRP_FW_EXT==1)
1637 #pragma DATA_SECTION(l1_drp_int_mem, ".drp_ptr")
1638 void * l1_drp_int_mem;
1639 #pragma DATA_SECTION(l1_drp_ext_mem, ".drp_ptr")
1640 void *l1_drp_ext_mem;
1641 #endif
1642 void l1_drp_init()
1643 {
1644 //int i;- OMAPS90550-new
1645 #if (DRP_FW_EXT==1)
1646 uint32 size_int=0;
1647 uint32 size_ext=0;
1648 #endif
1649 #if (RF_FAM == 61)
1650 volatile UWORD16 *ptr_drp_init16;
1651 UWORD16 drp_maj_version;
1652 UWORD16 drp_min_version;
1653
1654 //Initialize the following SRM_API, REG related address drp_srm_data = DRP_SRM_DATA_ADD,
1655 //drp_regs = DRP_REGS_BASE_ADD;, drp_srm_api = DRP_SRM_API_ADD
1656
1657 drp_api_addr_init();
1658
1659 #if (DRP_FW_EXT==1)
1660 drp_maj_version = (drp_ref_sw_ver >> 8) & 0xFF;
1661 drp_min_version = (drp_ref_sw_ver & 0xFF);
1662 #endif
1663
1664 //Initialize the following variables... TBD Danny
1665 //SRM_CW = 0x00000040, IRQ_CNT= 0x00000040 , TX_PTR_START_END_ADDR = 0X00200025,
1666 //RX_PTR_START_END_ADDR = 0X0000001F , 0XFFFE0806= 16
1667 //The registers are 32 bit since its a RHEA peripheral has to be writtin in 16 bit writes
1668 // This is done by the DRP script download
1669
1670 // The counter for # of DRP_DBB_RX_IRQs (in the wrapper) to be masked
1671 ptr_drp_init16 = (UWORD16 *) (DRP_DBB_RX_IRQ_MASK);
1672 (*ptr_drp_init16) = DRP_DBB_RX_IRQ_COUNT;
1673
1674 #endif //RF_FAM == 61
1675 l1s.boot_result=0;
1676 #if (DRP_FW_EXT==1)
1677 if(!((drp_min_version >= L1_DRP_COMPAT_MINOR_VER) && (drp_maj_version == L1_DRP_COMPAT_MAJOR_VER))) {
1678 l1s.boot_result = 1;
1679 return;
1680 }
1681 drp_get_memory_size(&size_int,&size_ext);
1682 /* FIXME FIXME ERROR handling for memory allocation failure */
1683 if(size_int)
1684 {
1685 l1_drp_int_mem=os_alloc_sig(size_int);
1686 if(l1_drp_int_mem==NULL)
1687 {
1688 /*FIXME Error Handling Here */
1689 l1s.boot_result = 1;
1690 return;
1691 }
1692 }
1693 if(size_ext)
1694 {
1695 l1_drp_ext_mem=os_alloc_sig(size_ext);
1696
1697 if(l1_drp_ext_mem==NULL)
1698 {
1699 /*FIXME Error Handling Here */
1700 l1s.boot_result = 1;
1701 return;
1702 }
1703 }
1704
1705 // Populate pointers
1706 if(drpfw_init(&modem_func_jump_table,&modem_var_jump_table))
1707 {
1708 // This condition should not be reached in phase 1 of DRP FW
1709 // Extraction. DRP and L1 software should always be compatible
1710 l1s.boot_result = 1;
1711 return;
1712 }
1713
1714 ((T_DRP_ENV_INT_BLK *)l1_drp_int_mem)->g_pcb_config = RF_BAND_SYSTEM_INDEX; //OMAPS148175
1715
1716 #endif // DRP_FW_EXT==1
1717 // This function would takes care of drp_ref_sw download till that is in place this would be a dummy function
1718 // Testing PLD_WriteRegister(0x0440, 0x165c);
1719 #if (RF_FAM == 60) // PLD board
1720 // for PLD board script downloading will happen through USP driver
1721 // load ref_sw_main
1722 // drp_ref_sw_upload(drp_ref_sw);
1723 drp_copy_ref_sw_to_drpsrm( (unsigned char *) drp_ref_sw);
1724 #elif (RF_FAM == 61) // Locosto based board
1725 // load ref_sw_main
1726 // drp_ref_sw_upload(drp_ref_sw); // TBD replace with DRP Copy function...
1727 drp_copy_ref_sw_to_drpsrm( (unsigned char *) drp_ref_sw);
1728 #endif
1729
1730 #if (L1_DRP_DITHERING == 1)
1731 (*(volatile UINT8 *)CONF_MUX_VIEW8) = 0x01;
1732 (*(volatile UINT8 *)CONF_DEBUG_SEL_TST_8) = 0x07;
1733 (*(volatile UINT8 *)CONF_GPIO_17) = 0x02;
1734 (*(volatile UINT8 *)CONF_LOCOSTO_DEBUG) = 0x00;
1735 #endif
1736
1737 }
1738 #endif // L1_DRP
1739
1740 /*-------------------------------------------------------*/
1741 /* l1_initialize() */
1742 /*-------------------------------------------------------*/
1743 /* Parameters : */
1744 /* Return : */
1745 /* Functionality : */
1746 /*-------------------------------------------------------*/
1747 void l1_initialize(T_MMI_L1_CONFIG *mmi_l1_config)
1748 {
1749 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) || (TRACE_TYPE == 5)
1750 l1_trace_init();
1751 #endif
1752
1753 // this is not a recovery initialization .
1754 l1a_l1s_com.recovery_flag = FALSE;
1755
1756 // initialize the ratio of the wait loop
1757 // must be initialized before using the wait_ARM_cycles() function !!!
1758 #if (CODE_VERSION != SIMULATION)
1759 initialize_wait_loop();
1760 #endif
1761
1762 // Init Layer 1 configuration
1763 //===========================
1764 #if(L1_FF_MULTIBAND == 0)
1765 l1_config.std.id = mmi_l1_config->std;
1766 #endif
1767
1768 l1_config.tx_pwr_code = mmi_l1_config->tx_pwr_code;
1769 #if IDS
1770 l1_config.ids_enable = mmi_l1_config->ids_enable;
1771 #endif
1772 l1_config.facch_test.enable = mmi_l1_config->facch_test.enable;
1773 l1_config.facch_test.period = mmi_l1_config->facch_test.period;
1774 l1_config.dwnld = mmi_l1_config->dwnld;
1775
1776 #if TESTMODE
1777 // Initialize TestMode params: must be done after Omega power-on
1778 l1_config.TestMode = FALSE;
1779 // Enable control algos and ADC
1780 l1_config.agc_enable = 1;
1781 l1_config.afc_enable = 1;
1782 l1_config.adc_enable = 1;
1783 #if (FF_REPEATED_SACCH == 1)
1784 l1_config.repeat_sacch_enable = 1; /* Repeated SACCH mode enabled */
1785 #endif /* (FF_REPEATED_SACCH == 1) */
1786 #if (FF_REPEATED_DL_FACCH == 1)
1787 l1_config.repeat_facch_dl_enable = 1; /* Repeated SACCH mode enabled */
1788 #endif /* ( FF_REPEATED_DL_FACCH == 1) */
1789 #endif
1790
1791 // sleep management configuration
1792 //===============================
1793 l1s.pw_mgr.mode_authorized = mmi_l1_config->pwr_mngt_mode_authorized;
1794 l1s.pw_mgr.clocks = mmi_l1_config->pwr_mngt_clocks;
1795 l1_config.pwr_mngt = mmi_l1_config->pwr_mngt;
1796
1797 Cust_init_std();
1798 Cust_init_params();
1799
1800
1801
1802 // Init DPLL variable
1803 //===================
1804 l1_dpll_init_var();
1805
1806 // Reset hardware (DSP,Analog Baseband device , TPU) ....
1807 //========================================================
1808 #if (CODE_VERSION != SIMULATION)
1809 dsp_power_on();
1810 l1_abb_power_on();
1811 #if (L1_DRP == 1)
1812 l1_drp_init();
1813 //required for interworking with Isample 2.1 and Isample 2.5
1814 #if (DRP_FW_EXT == 1)
1815 if (!l1s.boot_result)
1816 {
1817 #endif
1818 //for DRP Calibration
1819 Cust_init_params_drp();
1820 drp_efuse_init();
1821 #if (DRP_FW_EXT == 1)
1822 } /* end if boot_result != 0 */
1823 #endif
1824
1825 #endif
1826
1827 #endif
1828
1829 // Initialize hardware....(DSP, TPU)....
1830 //=================================================
1831 l1_tpu_init();
1832 l1_dsp_init();
1833
1834 // Initialize L1 variables (l1a, l1s, l1a_l1s_com).
1835 //=================================================
1836 l1_initialize_var();
1837
1838 // API check function
1839 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38) || (DSP == 39)) && (CODE_VERSION != SIMULATION))
1840 l1_api_dump();
1841 #endif
1842
1843 #if (L1_GPRS)
1844 // Initialize L1 variables used in packet mode (l1pa, l1ps, l1pa_l1ps_com).
1845 //========================================================================
1846 initialize_l1pvar();
1847 #endif
1848
1849 // Initialize statistics mode.......
1850 //=================================================
1851 #if TRACE_TYPE==3
1852 reset_stats();
1853 #endif
1854 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC
1855 Cust_navc_ctrl_status(1);//start - NAVC
1856 #endif//end of (OP_L1_STANDALONE == 1 || L1_NAVC == 1 )
1857
1858 #if FEATURE_TCH_REROUTE
1859 feature_tch_reroute_init();
1860 #endif
1861 }
1862
1863 /*-------------------------------------------------------*/
1864 /* l1_initialize_for_recovery */
1865 /*-------------------------------------------------------*/
1866 /* Parameters : */
1867 /* Return : */
1868 /* Functionality : This function is called for L1 */
1869 /* recovery after a Crash. When there are 100 COM error */
1870 /* or if ther are 100 PM =0 from the DSP Successively. */
1871 /* The Layer 1 Crashes. The next time the Protocol stack */
1872 /* requests for Full Rx Measurement (viz Cell selection) */
1873 /* This function gets called and the L1 recovery is */
1874 /* initiated. */
1875 /*-------------------------------------------------------*/
1876 #if L1_RECOVERY
1877 void l1_initialize_for_recovery(void)
1878 {
1879 LA_ResetLead(); // set DSP in reset mode
1880 initialize_wait_loop();
1881
1882 dsp_power_on(); // the reset mode is disabled here
1883 l1_abb_power_on();
1884 #if (L1_DRP == 1)
1885 l1_drp_init();
1886 //Required for interworking with Isample 2.1 and Isample 2.5
1887 Cust_init_params_drp();
1888 drp_efuse_init();
1889 #endif
1890 l1_tpu_init();
1891 wait_ARM_cycles(convert_nanosec_to_cycles(11000000)); // wait of 5.5 msec
1892 l1_dsp_init();
1893 l1_initialize_var();
1894
1895 #if L1_GPRS
1896 initialize_l1pvar();
1897 #endif
1898
1899 l1a_l1s_com.recovery_flag = FALSE;
1900
1901 // clear pending IQ_FRAME it and enable it
1902 #if (CHIPSET >= 4 )
1903 #if (CHIPSET == 12) || (CHIPSET == 15)
1904 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
1905 #else
1906 * (volatile UWORD16 *) INTH_IT_REG1 &= ~(1 << IQ_FRAME); // clear TDMA IRQ
1907 #endif
1908 #else
1909 * (volatile UWORD16 *) INTH_IT_REG &= ~(1 << IQ_FRAME); // clear TDMA IRQ
1910 #endif
1911
1912 }
1913 #endif
1914
1915
1916