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comparison L1/cfile/l1_pwmgr.c @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
parents
children b36540edb046
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-1:000000000000 0:75a11d740a02
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_PWMGR.C
4 *
5 * Filename l1_pwmgr.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 // pinghua add these programe code section to put some sleep code into internal ram.
11 /*
12 * FreeCalypso: the Leonardo binary object version puts all of l1_pwmgr
13 * into the regular run-from-flash text section, so we'll do the same
14 * for now.
15 */
16 #if 0
17 #pragma CODE_SECTION(l1s_sleep_manager,".emifconf")
18 #pragma CODE_SECTION(EMIF_SetConfReg,".emifconf")
19 #pragma CODE_SECTION(audio_madc_sleep,".emifconf")
20 #pragma CODE_SECTION(Check_Peripheral_App,".emifconf")
21 #pragma CODE_SECTION(DBB_Configure_DS,".emifconf")
22 #pragma CODE_SECTION(DBB_Wakeup_DS,".emifconf")
23 #pragma CODE_SECTION(l1ctl_pgm_clk32,".emifconf")
24 #pragma CODE_SECTION(l1ctl_gauging,".emifconf")
25 #pragma CODE_SECTION(GAUGING_Handler,".emifconf")
26 #pragma CODE_SECTION(l1s_get_HWTimers_ticks,".emifconf")
27 #pragma CODE_SECTION(l1s_adapt_traffic_controller,".emifconf")
28 #pragma CODE_SECTION(l1s_wakeup,".emifconf")
29 #pragma CODE_SECTION(l1s_wakeup_adjust,".emifconf")
30 #pragma CODE_SECTION(l1s_compute_wakeup_ticks,".emifconf")
31 #pragma CODE_SECTION(l1s_recover_Frame,".emifconf")
32 #pragma CODE_SECTION(l1s_recover_HWTimers,".emifconf")
33 #pragma CODE_SECTION(l1s_get_next_gauging_in_Packet_Idle,".emifconf")
34 #pragma CODE_SECTION(l1s_gauging_decision_with_PNP,".emifconf")
35 #pragma CODE_SECTION(l1s_gauging_decision_with_NP,".emifconf")
36 #pragma CODE_SECTION(l1s_gauging_task,".emifconf")
37 #pragma CODE_SECTION(l1s_gauging_task_end,".emifconf")
38 // 2-03-2007 pinghua added end
39 #endif
40
41 #define L1_PWMGR_C
42 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
43
44 #include "config.h"
45 #include "l1_confg.h"
46
47 //sajal added .....................................
48 #if (CODE_VERSION == SIMULATION)
49 //#include "l1_pwmgr.h"
50 //omaps00090550 #303 warning removal typedef unsigned char UWORD_8;
51
52 // typedef volatile unsigned short REG_UWORD16; //omaps00090550
53 // #define REG16(A) (*(REG_UWORD16*)(A)) //omaps00090550
54 // typedef volatile unsigned short REGISTER_UWORD16; //omaps00090550
55
56 #define MAP_ULPD_REG 0xFFFE2000 //ULPD registers start address (CS4)
57 #define ULPD_SETUP_CLK13_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 14))
58 #define ULPD_SETUP_SLICER_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 15))
59 #define ULPD_SETUP_VTCXO_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 16))
60
61 #define MAP_CLKM_REG 0xFFFFFD00 //CLOCKM registers start address (CS31)
62 #define CLKM_CNTL_CLK_OFFSET 0x02
63 #define CLKM_CNTL_CLK_REG REG16 (MAP_CLKM_REG + CLKM_CNTL_CLK_OFFSET)
64
65 #define EMIF_CONFIG_PWD_POS 0
66 #define EMIF_CONFIG_PDE_POS 1
67 #define EMIF_CONFIG_PREFETCH_POS 3
68 #define EMIF_CONFIG_FLUSH_PREFETCH_POS 5
69 #define EMIF_CONFIG_WP_POS 6
70
71 #define EMIF_CONFIG REG16(EMIF_CONFIG_BASE_ADDR+EMIF_CONFIG_REG_OFFSET)
72 #define EMIF_CONFIG_BASE_ADDR 0xFFFFFB00 //External Memory inter registers address (CS31) (NEW)
73 #define EMIF_CONFIG_REG_OFFSET 0x02 // Emif configuration register
74
75 #endif
76 //sajal added till here......
77
78
79
80 #include "../../bsp/timer2.h"
81 #include "../../bsp/armio.h"
82 #include "../../serial/serialswitch.h"
83
84 #if 0 //(OP_L1_STANDALONE == 0)
85 #include "sim/sim.h"
86 #include "rv_swe.h"
87 #endif
88
89
90 #if (CODE_VERSION == SIMULATION)
91 #include "l1_types.h"
92 #include "l1_const.h"
93
94 #if (CHIPSET == 12) || (CHIPSET == 15)
95 #include "inth/sys_inth.h"
96 #include "sys_dma.h"
97 #include "ulpd.h"
98 #include "clkm.h"
99
100 // typedef volatile unsigned short REG_UWORD16; //omaps00090550
101 #define REG16(A) (*(REG_UWORD16*)(A))
102
103 #else
104 #include "inth/iq.h"
105 #endif
106
107 #if TESTMODE
108 #include "l1tm_defty.h"
109 #endif // TESTMODE
110
111 #if (AUDIO_TASK == 1)
112 #include "l1audio_const.h"
113 #include "l1audio_cust.h"
114 #include "l1audio_defty.h"
115 #endif // AUDIO_TASK
116
117 #if (L1_GTT == 1)
118 #include "l1gtt_const.h"
119 #include "l1gtt_defty.h"
120 #endif
121
122 #if (L1_MP3 == 1)
123 #include "l1mp3_defty.h"
124 #endif
125
126 #if (L1_MIDI == 1)
127 #include "l1midi_defty.h"
128 #endif
129 //ADDED FOR AAC
130 #if (L1_AAC == 1)
131 #include "l1aac_defty.h"
132 #endif
133 #include "l1_defty.h"
134 #include "l1_varex.h"
135 #include "l1_tabs.h"
136 #include "cust_os.h"
137 #include "l1_msgty.h"
138 #include "l1_proto.h"
139 #include "ulpd.h"
140 #include "l1_trace.h"
141
142 #if L1_GPRS
143 #include "l1p_cons.h"
144 #include "l1p_msgt.h"
145 #include "l1p_deft.h"
146 #include "l1p_vare.h"
147 #endif // L1_GPRS
148
149 #include <stdio.h>
150 #include "sim_cfg.h"
151 #include "sim_cons.h"
152 #include "sim_def.h"
153 #include "sim_var.h"
154 //omaps00090550
155 #include "nucleus.h"
156
157 extern NU_TASK L1S_task;
158 STATUS status;
159
160
161
162 #else // NO SIMULATION
163
164
165
166 #include "l1_types.h"
167 #include "l1_const.h"
168
169 #include "../../bsp/abb+spi/abb.h"
170 /* #include "dma/sys_dma.h" */
171
172 #if (OP_BT == 1)
173 #include "hci_ll_simul.h"
174 #endif
175
176 #if TESTMODE
177 #include "l1tm_defty.h"
178 #endif // TESTMODE
179
180 #if (AUDIO_TASK == 1)
181 #include "l1audio_const.h"
182 #include "l1audio_cust.h"
183 #include "l1audio_defty.h"
184 #endif // AUDIO_TASK
185
186 #if (L1_GTT == 1)
187 #include "l1gtt_const.h"
188 #include "l1gtt_defty.h"
189 #endif
190
191 #if (L1_MP3 == 1)
192 #include "l1mp3_defty.h"
193 #endif
194
195 #if (L1_MIDI == 1)
196 #include "l1midi_defty.h"
197 #endif
198 //ADDED FOR AAC
199 #if (L1_AAC == 1)
200 #include "l1aac_defty.h"
201 #endif
202 #include "l1_defty.h"
203 #include "l1_varex.h"
204 #include "l1_tabs.h"
205 #include "sys_types.h"
206 #include "tpudrv.h"
207 #include "../../gpf/inc/cust_os.h"
208 #include "l1_msgty.h"
209 #include "l1_proto.h"
210 #include "l1_trace.h"
211 #include "../../bsp/timer.h"
212
213 #include "l1_pwmgr.h"
214
215 #if (CHIPSET == 12) || (CHIPSET == 15)
216 #include "timer/timer_sec.h"
217 #include "inth/sys_inth.h"
218
219
220
221 #if(CHIPSET == 15)
222 #include "l1_pwmgr.h"
223 #if (OP_L1_STANDALONE == 0)
224 #include "lcc/lcc_api.h"
225 #endif
226
227 /* If NAND is enabled */
228 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE)
229 unsigned int temp_NAND_Reg1;
230 unsigned int temp_NAND_Reg2;
231 unsigned int temp_NAND_Reg3;
232 #endif
233
234
235
236
237
238 #if (OP_L1_STANDALONE == 1)
239
240 const t_peripheral_interface Peripheral_interface [MAX_PERIPHERAL]=
241 {
242 f_peripheral_interface_dummy,
243 f_peripheral_interface_dummy,
244 f_peripheral_interface_dummy,
245 f_peripheral_interface_dummy,
246 f_peripheral_interface_dummy,
247 f_peripheral_interface_dummy,
248 f_peripheral_interface_dummy,
249 f_peripheral_interface_dummy,
250 madc_outen_check, /* MADC_AS_ID = 8 */
251 f_peripheral_interface_dummy,
252 f_peripheral_interface_dummy,
253 f_peripheral_interface_dummy,
254 f_peripheral_interface_dummy,
255 f_peripheral_interface_dummy,
256 f_peripheral_interface_dummy,
257 f_peripheral_interface_dummy,
258 };
259
260 const t_application_interface Application_interface [MAX_APPLICATIONS] =
261 {
262 f_application_interface_dummy,
263 f_application_interface_dummy,
264 f_application_interface_dummy,
265 f_application_interface_dummy,
266 f_application_interface_dummy,
267 f_application_interface_dummy,
268 f_application_interface_dummy,
269 f_application_interface_dummy,
270 f_application_interface_dummy,
271 f_application_interface_dummy,
272 f_application_interface_dummy,
273 f_application_interface_dummy,
274 f_application_interface_dummy,
275 f_application_interface_dummy,
276 f_application_interface_dummy,
277 f_application_interface_dummy,
278 };
279 #else // For integrated Build
280 const t_peripheral_interface Peripheral_interface [MAX_PERIPHERAL]=
281 {
282 uart_pwr_interface,
283 #ifdef RVM_USB_SWE
284 usb_pwr_interface,
285 #else
286 f_peripheral_interface_dummy,
287 #endif
288 usim_pwr_interface,
289 i2c_pwr_interface,
290 lcd_pwr_interface,
291 #ifdef RVM_CAMD_SWE
292 #if (OP_L1_STANDALONE == 0)
293 camera_pwr_interface,
294 #endif
295 #else
296 f_peripheral_interface_dummy,
297 #endif
298 backlight_pwr_interface,
299 f_peripheral_interface_dummy,
300 audio_madc_sleep, /* MADC_AS_ID = 8 */
301 lcc_pwr_interface,
302 f_peripheral_interface_dummy,
303 f_peripheral_interface_dummy,
304 f_peripheral_interface_dummy,
305 f_peripheral_interface_dummy,
306 f_peripheral_interface_dummy,
307 f_peripheral_interface_dummy,
308 };
309
310 const t_application_interface Application_interface [MAX_APPLICATIONS] =
311 {
312 #ifdef BTS
313
314 BTHAL_PM_HandleSleepManagerReq,
315 #else
316 f_application_interface_dummy,
317 #endif
318 f_application_interface_dummy,
319 f_application_interface_dummy,
320 f_application_interface_dummy,
321 f_application_interface_dummy,
322 f_application_interface_dummy,
323 f_application_interface_dummy,
324 f_application_interface_dummy,
325 f_application_interface_dummy,
326 f_application_interface_dummy,
327 f_application_interface_dummy,
328 f_application_interface_dummy,
329 f_application_interface_dummy,
330 f_application_interface_dummy,
331 f_application_interface_dummy,
332 f_application_interface_dummy,
333 };
334
335
336 #endif // (OP_L1_STANDALONE == 1)
337
338 #endif // omaps00090550 #14 -d removal (CHIPSET = 15)
339
340
341 #else //(CHIPSET == 12) || (CHIPSET == 15)
342 #include "../../bsp/iq.h"
343 #include "../../bsp/inth.h"
344 #endif
345 // #include "timer1.h"
346 #include "../../bsp/ulpd.h"
347 #include "../../bsp/clkm.h"
348 #include "../../bsp/mem.h"
349 #if L2_L3_SIMUL
350 #include "hw_debug.h"
351 #endif
352
353 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
354 #include "csmi/sleep.h"
355 #endif // OP_WCP
356 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
357 #include "sys_memif.h"
358 #endif
359
360 #if (GSM_IDLE_RAM != 0)
361 #if (OP_L1_STANDALONE == 1)
362 #include "csmi_simul.h"
363 #else
364 #include "csmi/csmi.h"
365 #endif
366 #endif
367
368 #if (CHIPSET == 15)
369 #include "drp_api.h"
370 #endif
371
372 #endif // NO SIMULATION
373
374 #if (CODE_VERSION != SIMULATION)
375 // for PTOOL compatibility
376 extern void INT_DisableIRQ(void);
377 extern void INT_EnableIRQ(void);
378 extern void l1dmacro_RF_sleep(void);
379 extern void l1dmacro_RF_wakeup(void);
380 WORD32 l1s_get_HWTimers_ticks(void);
381
382 // file timer1.h
383 SYS_UWORD16 Dtimer1_Get_cntlreg(void);
384 void Dtimer1_AR(unsigned short Ar);
385 void Dtimer1_PTV(unsigned short Ptv);
386 void Dtimer1_Clken(unsigned short En);
387 void Dtimer1_Start (unsigned short startStop);
388 void Dtimer1_Init_cntl (SYS_UWORD16 St, SYS_UWORD16 Reload, SYS_UWORD16 clockScale, SYS_UWORD16 clkon);
389 SYS_UWORD16 Dtimer1_WriteValue (SYS_UWORD16 value);
390 SYS_UWORD16 Dtimer1_ReadValue (void);
391 #endif
392
393 void l1s_wakeup(void);
394 BOOL l1s_compute_wakeup_ticks(void);
395 void l1s_recover_Frame(void);
396 UWORD8 Cust_recover_Os(void);
397 void l1s_recover_HWTimers(void);
398 UWORD8 Cust_check_system(void);
399 void f_arm_sleep_cmd(UWORD8 d_sleep_mode);
400
401 //#if (TRACE_TYPE == 2) || (TRACE_TYPE == 3)
402 extern void L1_trace_string(char *s);
403 extern void L1_trace_char (char s);
404 //#endif
405 extern UWORD16 slp_debug_flag;
406
407 #if (GSM_IDLE_RAM != 0)
408 extern void l1s_trace_mftab(void);
409 #endif
410
411 #if (CODE_VERSION != SIMULATION) && (CHIPSET == 15)
412 extern T_DRP_REGS_STR *drp_regs;
413 #endif
414
415 #if L1_GPRS
416 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void);
417 #endif
418 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
419
420 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled
421 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise
422
423 /************************************************************/
424 /* Macros for power management */
425 /************************************************************/
426 #define MIN(min, operand1) \
427 if (operand1 <= min) min = operand1;
428
429 // ex: RATIO T32khz/T4.33Mhz = 132.2428385417
430 // => root = integer part of the ratio
431 // = 132
432 // => frac = fractionnal part of the ratio multiplied by 65536 rounded to make it integer
433 // = 0.2428385417 * 65536 (Cf. ULPD specification)
434 // = 0.2428385417 * 2^16
435 // = 15914.66666689 = 15914
436
437 #define RATIO(HF,LF, root, frac) \
438 root = (UWORD32)(HF/LF); \
439 frac = (UWORD32)(((HF - (root*LF)) << 16) / LF);
440
441 // previous ratio with frac + 0.5
442 #define RATIO2(HF,LF, root, frac) \
443 if(LF){ \
444 root = (UWORD32)(HF/LF); \
445 frac = (UWORD32)((((HF - (root*LF)) << 16) + 0.5*LF) / LF);}
446
447 #define HFTHEO(LF, root, frac, hftheo) \
448 hftheo = root*LF + ((frac*LF) >>16);
449
450 #define SUM(HF, LF, nb, ind) \
451 LF=HF=0; \
452 for(ind=0; ind<nb; ind++) \
453 { \
454 LF = LF +l1s.pw_mgr.histo[ind][0]; \
455 HF = HF +l1s.pw_mgr.histo[ind][1]; \
456 }
457
458
459
460 #if (CODE_VERSION!=SIMULATION)
461 T_PWMGR_DEBUG l1_pwmgr_debug;
462 #endif // NOT SIMULATION
463
464 #if(CHIPSET == 15)
465
466 /************************************************************/
467 /* Configure EMIF for optimal consumption */
468 /************************************************************/
469
470
471 void EMIF_SetConfReg(const UWORD8 wp,const UWORD8 flush_prefetch,const UWORD8 Prefetch_mode,const UWORD8 pde,const UWORD8 pwd_en)
472 {
473 UWORD16 Emif_config_Reg;
474 Emif_config_Reg = (pwd_en << EMIF_CONFIG_PWD_POS | pde << EMIF_CONFIG_PDE_POS | Prefetch_mode << EMIF_CONFIG_PREFETCH_POS | flush_prefetch << EMIF_CONFIG_FLUSH_PREFETCH_POS | wp << EMIF_CONFIG_WP_POS);
475 /*p_Emifreg -> EMIF_Config = (Emif_config_Reg & EMIF_CONFIG_REG_MASK );*/
476 EMIF_CONFIG = Emif_config_Reg;
477 } // End of EMIF_SetConfReg
478
479
480
481 #if (OP_L1_STANDALONE == 1) // API for Audio and MADC
482
483
484
485 T_AUDIO_OUTEN_REG audio_outen_pm;
486
487 // L1 Standalone function for Configuring Audio registers.
488 // Argument CLK_MASK checks if Audio path is active
489 // Argument SLEEP_CMD configures Audio registers for optimal consumption
490 // Argument WAKE_CMD reconfigure audio registers after wakeup
491
492 Uint8 madc_outen_check(Uint8 cmd) {
493 BspTwl3029_ReturnCode returnVal = BSP_TWL3029_RETURN_CODE_FAILURE;
494 /* I2C array */
495 Bsp_Twl3029_I2cTransReqArray i2cTransArray;
496 Bsp_Twl3029_I2cTransReqArrayPtr i2cTransArrayPtr= &i2cTransArray;
497
498 /* twl3029 I2C reg info struct */
499 BspTwl3029_I2C_RegisterInfo regInfo[8] ;
500 BspTwl3029_I2C_RegisterInfo* regInfoPtr = regInfo;
501 BspTwl3029_I2C_RegData shadow_pwronstatus, ston_bit;
502 Uint8 count = 0;//OMAPS90550-new
503
504
505 switch( cmd ) {
506
507 case CLK_MASK:
508 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_PWRONSTATUS_OFFSET,
509 &shadow_pwronstatus);
510 ston_bit = (shadow_pwronstatus & (1 << BSP_TWL3029_LLIF_AUDIO_PWRONSTATUS_STON_OFFSET));
511
512 if (ston_bit == 1) return DCXO_CLOCK;
513 else return NO_CLOCK;
514 // omaps00090550 break;
515
516 case SLEEP_CMD:
517 /* store the output enable 1 register */
518 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
519 &audio_outen_pm.outen1);
520
521 /* store the output enable 2 register */
522 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
523 &audio_outen_pm.outen2);
524
525 /* store the output enable 3 register */
526 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
527 &audio_outen_pm.outen3);
528
529
530 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
531 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
532 BSP_TWL_3029_MAP_AUDIO_OUTEN1_DEFAULT,regInfoPtr++);
533 count++;
534
535 /* store the output enable 2 register */
536 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
537 BSP_TWL_3029_MAP_AUDIO_OUTEN2_DEFAULT,regInfoPtr++);
538 count++;
539
540 /* store the output enable 3 register */
541 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
542 BSP_TWL_3029_MAP_AUDIO_OUTEN3_DEFAULT,regInfoPtr++);
543 count++;
544
545
546 /* now request to I2C manager to write to Triton registers */
547 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
548 {
549 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
550 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
551 }
552
553 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
554 else return FAILURE;
555
556 // omaps00090550 break;
557
558 case WAKE_CMD:
559 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
560 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
561 audio_outen_pm.outen1,regInfoPtr++);
562 count++;
563
564 /* store the output enable 2 register */
565 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
566 audio_outen_pm.outen2,regInfoPtr++);
567 count++;
568
569 /* store the output enable 3 register */
570 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
571 audio_outen_pm.outen3,regInfoPtr++);
572 count++;
573
574
575
576 /* now request to I2C manager to write to Triton registers */
577 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
578 {
579 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
580 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
581 }
582
583 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
584 else return FAILURE;
585 // omaps00090550 break;
586 }
587 return SUCCESS;//omaps00090550
588 }
589 #else // Integrated build API for Audio and MADC
590
591 // Full PS build function for Configuring Audio registers.
592 // Argument CLK_MASK checks if Audio path is active
593 // Argument SLEEP_CMD configures Audio registers for optimal consumption
594 // Argument WAKE_CMD reconfigure audio registers after wakeup
595
596
597 T_AUDIO_OUTEN_REG audio_outen_pm;
598 BspTwl3029_I2C_RegData audio_ctrl3;
599
600 Uint8 audio_madc_sleep(Uint8 cmd) {
601 BspTwl3029_ReturnCode returnVal = BSP_TWL3029_RETURN_CODE_FAILURE;
602 /* I2C array */
603 //Bsp_Twl3029_I2cTransReqArray i2cTransArray;
604 //Bsp_Twl3029_I2cTransReqArrayPtr i2cTransArrayPtr= &i2cTransArray;
605
606 /* twl3029 I2C reg info struct */
607 //BspTwl3029_I2C_RegisterInfo regInfo[8] ;
608 //BspTwl3029_I2C_RegisterInfo* regInfoPtr = regInfo;
609 BspTwl3029_I2C_RegData shadow_pwronstatus, ston_bit;
610
611
612 Uint8 count = 0;
613
614
615 switch( cmd ) {
616
617 case CLK_MASK:
618 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_PWRONSTATUS_OFFSET,
619 &shadow_pwronstatus);
620 ston_bit = (shadow_pwronstatus & (1 << BSP_TWL3029_LLIF_AUDIO_PWRONSTATUS_STON_OFFSET));
621
622 if (ston_bit == 1) return DCXO_CLOCK;
623 else return NO_CLOCK;
624 //omaps00090550 break;
625
626 case SLEEP_CMD:
627 #if 0
628 /* store the output enable 1 register */
629 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
630 &audio_outen_pm.outen1);
631
632 /* store the output enable 2 register */
633 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
634 &audio_outen_pm.outen2);
635
636 /* store the output enable 3 register */
637 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
638 &audio_outen_pm.outen3);
639
640 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
641 &audio_ctrl3);
642
643 if( audio_outen_pm.outen1 )
644 {
645 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
646 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
647 BSP_TWL_3029_MAP_AUDIO_OUTEN1_DEFAULT,regInfoPtr++);
648 count++;
649 }
650
651 if( audio_outen_pm.outen2 )
652 {
653
654 /* store the output enable 2 register */
655 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
656 BSP_TWL_3029_MAP_AUDIO_OUTEN2_DEFAULT,regInfoPtr++);
657 count++;
658 }
659
660 if( audio_outen_pm.outen3 )
661 {
662 /* store the output enable 3 register */
663 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
664 BSP_TWL_3029_MAP_AUDIO_OUTEN3_DEFAULT,regInfoPtr++);
665 count++;
666 }
667
668 /* Selectively checking if INMODE is set or not. Write is queued only when INMODE(0-3)
669 is non-zero */
670 if( audio_ctrl3 & 0xf)
671 {
672 /* store the output enable 3 register */
673 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,
674 BSP_TWL_3029_MAP_AUDIO_CTRL3_DEFAULT,regInfoPtr++);
675 count++;
676 }
677
678 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUX,BSP_TWL3029_MAP_AUX_REG_TOGGLE1_OFFSET,
679 1 << BSP_TWL3029_LLIF_AUX_REG_TOGGLE1_MADCR_OFFSET, regInfoPtr++);
680 count++;
681
682 //Turn off the USB leakage currrent
683
684 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0, BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0xb6,regInfoPtr++);
685 // count++;
686
687 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2, BSP_TWL3029_MAP_USB_PSM_EN_TEST_SET_OFFSET,0x80,regInfoPtr++);
688 //count++;
689
690 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_VBUS_EN_TEST_OFFSET,0x00,regInfoPtr++);
691 // count++;
692
693 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0, BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0x00,regInfoPtr++);
694 //count++;
695
696 // now request to I2C manager to write to Triton registers
697 //if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE && !is_i2c_bus_locked())
698 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
699 {
700 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
701 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
702 }
703
704 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
705 else return FAILURE;
706
707 #endif
708
709 //omaps00090550 break;
710
711 case WAKE_CMD:
712 #if 0
713
714 if( audio_outen_pm.outen1 )
715 {
716 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
717 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
718 audio_outen_pm.outen1,regInfoPtr++);
719 count++;
720 }
721
722 if( audio_outen_pm.outen2 )
723 {
724
725 /* store the output enable 2 register */
726 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
727 audio_outen_pm.outen2,regInfoPtr++);
728 count++;
729 }
730
731 if( audio_outen_pm.outen3 )
732 {
733 /* store the output enable 3 register */
734 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
735 audio_outen_pm.outen3,regInfoPtr++);
736 count++;
737 }
738
739 /* Selectively checking if INMODE is set or not. Write is queued only when INMODE(0-3)
740 is non-zero */
741 if( audio_ctrl3 & 0xf)
742 {
743 /* store the output enable 3 register */
744 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,
745 audio_ctrl3,regInfoPtr++);
746 count++;
747 }
748
749
750 //wake up mode: Enable MADC
751 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUX,BSP_TWL3029_MAP_AUX_REG_TOGGLE1_OFFSET,
752 1 << BSP_TWL3029_LLIF_AUX_REG_TOGGLE1_MADCS_OFFSET, regInfoPtr++);
753
754 count++; //TI_SH added to set the madc on correctly
755
756 //Enable the USB leakage current after wake up
757
758 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0,BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0xb6,regInfoPtr++);
759 // count++;
760
761 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_VBUS_EN_TEST_OFFSET,0x0F,regInfoPtr++);
762 // count++;
763
764 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_PSM_EN_TEST_CLR_OFFSET,0x80,regInfoPtr++);
765 //count++;
766
767 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0,BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0x00,regInfoPtr++);
768 // count++;
769
770 // now request to I2C manager to write to Triton registers
771 //if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE && !is_i2c_bus_locked())
772 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
773 {
774 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
775 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
776 }
777
778 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
779 else return FAILURE;
780 #endif
781 break;
782 }
783 return SUCCESS;
784 }
785 #endif // API for Audio and MADC
786
787
788
789 //Function to check status of Backlight Only Argument 0 is valid
790
791
792 Uint8 backlight_pwr_interface(Uint8 cmd)
793 {
794 BspTwl3029_I2C_RegData regData;
795
796
797 if(cmd == 0)
798 {
799 BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_PAGE0,PWDNSTATUS,&regData);
800 if((regData) & 0x70)
801 {
802 return(DCXO_CLOCK);
803 }
804 else
805 {
806 return(NO_CLOCK);
807 }
808
809 }
810 else
811 {
812 return(SUCCESS);
813 }
814 }
815
816 //Dummy Function for peripheral check to populate Function pointer table for unused APIs
817
818
819 Uint8 f_peripheral_interface_dummy(Uint8 cmd)
820 {
821 if(cmd == 0)
822 {
823 return(NO_CLOCK);
824 }
825 else
826 {
827 return(SUCCESS);
828 }
829
830 }
831
832 //Dummy Function for Application check to populate Function pointer table for unused APIs
833
834 Uint8 f_application_interface_dummy(Uint8 cmd)
835 {
836 if(cmd == 0)
837 {
838 return(PM_INACTIVE);
839 }
840 else
841 {
842 return(SUCCESS);
843 }
844 }
845
846 //Function not used as of now //OMAPS00090550
847 void Update_Sleep_Status( Uint8 ID, Uint8 state)
848 {
849 if(state)
850 {
851 SLEEP_STATE |= (state << ID); //omaps00090550 ! was present before
852 }
853 else
854 {
855 SLEEP_STATE &=((Uint8)~1 <<ID); //omaps00090550
856 }
857 }
858
859 //Function polls the status of the following peripherals to take
860 //Sleep Decision:
861 //UART, USB, I2C, LCD, Camera, Backlight, Audio Stereo path,
862 //Bluetooth and USIM.
863 //All peripherals either cause Deep Sleep or No Sleep.
864 //Only USIM can also cause Big Sleep.
865
866
867
868 UWORD32 Check_Peripheral_App(void)
869 {
870 #if (CODE_VERSION!=SIMULATION)
871 UWORD8 ret_value;
872 /* Check Peripherals */
873 ret_value = Peripheral_interface[UART_ID](CLK_MASK);
874 if(ret_value)
875 {
876 l1_pwmgr_debug.fail_id = UART_ID;
877 l1_pwmgr_debug.fail_ret_val = ret_value;
878 return(DO_NOT_SLEEP);
879 }
880 ret_value = Peripheral_interface[USB_ID](CLK_MASK);
881 if(ret_value)
882 {
883 l1_pwmgr_debug.fail_id = USB_ID;
884 l1_pwmgr_debug.fail_ret_val = ret_value;
885 return(DO_NOT_SLEEP);
886 }
887 ret_value = Peripheral_interface[I2C_ID](CLK_MASK);
888 if(ret_value)
889 {
890 l1_pwmgr_debug.fail_id = I2C_ID;
891 l1_pwmgr_debug.fail_ret_val = ret_value;
892 return(DO_NOT_SLEEP);
893 }
894 ret_value = Peripheral_interface[LCD_ID](CLK_MASK);
895 if(ret_value)
896 {
897 l1_pwmgr_debug.fail_id = LCD_ID;
898 l1_pwmgr_debug.fail_ret_val = ret_value;
899 return(DO_NOT_SLEEP);
900 }
901 ret_value = Peripheral_interface[CAMERA_ID](CLK_MASK);
902 if(ret_value)
903 {
904 l1_pwmgr_debug.fail_id = CAMERA_ID;
905 l1_pwmgr_debug.fail_ret_val = ret_value;
906 return(DO_NOT_SLEEP);
907 }
908 ret_value = Peripheral_interface[BACKLIGHT_ID](CLK_MASK);
909 if(ret_value)
910 {
911 l1_pwmgr_debug.fail_id = BACKLIGHT_ID;
912 l1_pwmgr_debug.fail_ret_val = ret_value;
913 return(DO_NOT_SLEEP);
914 }
915 ret_value = Peripheral_interface[MADC_AS_ID](CLK_MASK);
916 if(ret_value)
917 {
918 l1_pwmgr_debug.fail_id = MADC_AS_ID;
919 l1_pwmgr_debug.fail_ret_val = ret_value;
920 return(DO_NOT_SLEEP);
921 }
922 /* check battery charger */
923 ret_value = Peripheral_interface[BCI_ID](CLK_MASK);
924 if(ret_value)
925 {
926 l1_pwmgr_debug.fail_id = BCI_ID;
927 l1_pwmgr_debug.fail_ret_val = ret_value;
928 return(DO_NOT_SLEEP);
929 }
930
931 /* Check Applications */
932 ret_value = Application_interface[BT_Stack_ID](APP_ACTIVITY);
933 if(ret_value)
934 {
935 // L1_APPLICATION_OFFSET is added to distinguish Application interface
936 l1_pwmgr_debug.fail_id = BT_Stack_ID + (L1_PWMGR_APP_OFFSET);
937 l1_pwmgr_debug.fail_ret_val = ret_value;
938 return(DO_NOT_SLEEP);
939 }
940 ret_value = Peripheral_interface[USIM_ID](CLK_MASK);
941 if(ret_value)
942 {
943 l1_pwmgr_debug.fail_id = USIM_ID;
944 l1_pwmgr_debug.fail_ret_val = ret_value;
945 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_SIM;
946 return(FRAME_STOP);
947 }
948 else
949 {
950 return(CLOCK_STOP);
951 }
952 #endif //NOT SIMULATION
953 }
954
955 //This function Configures DBB for optimal Power Consumption
956 //during Deep Sleep
957
958
959
960 void DBB_Configure_DS()
961 {
962 // FDP enabling and disabling of burst configuration in flash not required in Locosto
963 // Hardware Settings as per Power Bench
964
965 // Stop RNG oscillators
966 RNG_CONFIG &= 0xF03F;
967
968
969 /* Set GPIOs 19 to 22 as outputs to avoid floating pins */
970 GPIO1_CNTL_REG &= ~0x0078;
971
972 /* Set PD on VDR and VFSRX for VSP bus to avoid floating pins */
973 CONF_VDR |= 0x0008;
974 CONF_VFSRX |= 0x0008;
975
976 /* Set HASH in auto-idle */
977 SHA_MASK = 0x0001;
978
979 /* Set DES in auto-idle */
980 DES_MASK = 0x0001;
981
982 /* Set RNG in auto-idle */
983 RNG_MASK = 0x0001;
984
985
986 /* uart_in_pull_down(); */
987
988 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE)
989
990
991 temp_NAND_Reg1 = COMMAND_REG;
992 temp_NAND_Reg2 = CONTROL_REG;
993 temp_NAND_Reg3 = STATUS_IT_REG;
994
995 COMMAND_REG = 0x06;
996 CONTROL_REG = 0x0;
997 STATUS_IT_REG = 0x0;
998
999 #endif
1000 // RANGA: All these bit fields should be replaced by macros
1001 // Set DPLL in idle mode
1002 // Cut C-PORT (new), IRQ, BRIDGE and TIMER clocks
1003 /* Set DPLL in idle mode */
1004 /* Cut C-PORT (new), IRQ, BRIDGE and TIMER clocks */
1005 CLKM_CNTL_CLK_REG &= ~0x0010 ;
1006 CLKM_CNTL_CLK_REG |= 0x000F ;
1007
1008 CNTL_APLL_DIV_CLK &= ~0x0001; /* Disable APLL */
1009
1010 // Statements below are not required for the current hardware version.
1011 // This was done to solve the problem of DCXO taking 10 frames
1012 // to wake-up from Deep Sleep in older hardware versions.
1013
1014 //DCXO_THRESH_L = 0xC040; // Setting DCXO Thresholds
1015 //DCXO_THRESH_H = 0x051F; // to solve Deep Sleep problem
1016 }
1017
1018 //This function Restores DBB after wakeup from Deep Sleep
1019
1020
1021 void DBB_Wakeup_DS()
1022 {
1023 // FDP re-enabling and burst re-configuration are not required if FDP is disabled
1024 // during deep-sleep
1025
1026 CLKM_CNTL_CLK_REG |= 0x0010 ; // Enable CPORT Clock
1027
1028 CNTL_APLL_DIV_CLK |= 0x0001; // Enable APLL clock
1029
1030 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE)
1031
1032 // Restoring NAND
1033 COMMAND_REG = temp_NAND_Reg1;
1034 CONTROL_REG = temp_NAND_Reg2;
1035 STATUS_IT_REG = temp_NAND_Reg3;
1036 // Restoring NAND
1037 #endif
1038
1039
1040 }
1041
1042
1043 //This function shuts down APC Bandgap.Cannot be used for PG 1.0 Can be used only for PG 2.0
1044
1045
1046 void Disable_APC_BG() //omaps00090550
1047 {
1048 while (RHSW_ARM_CNF & DSP_PERIPH_LOCK)
1049 RHSW_ARM_CNF |= ARM_PERIPH_LOCK;
1050 APCCTRL2 &= ~BGEN;
1051 return;
1052 }
1053
1054 //This function enables APC Bandgap.Cannot be used for PG 1.0 Can be used only for PG 2.0
1055
1056 void Enable_APC_BG() //omaps00090550
1057 {
1058 while (RHSW_ARM_CNF & DSP_PERIPH_LOCK)
1059 RHSW_ARM_CNF |= ARM_PERIPH_LOCK;
1060 APCCTRL2 |= BGEN;
1061 return;
1062 }
1063
1064 #endif //CHIPSET = 15
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075 // l1ctl_pgm_clk32()
1076 // convert ratio in 4.33Mhz and pgm INC_FRAC,INC_SIXTEEN.
1077
1078 void l1ctl_pgm_clk32(UWORD32 nb_hf, UWORD32 nb_32khz)
1079 {
1080 #if (CODE_VERSION != SIMULATION)
1081 if (l1_config.pwr_mngt == PWR_MNGT)
1082 {
1083 UWORD32 inc_sixteen= 0, inc_frac=0, lf;
1084
1085 // REM: nb_hf is the real value of the high frequency (ex in nbr of 65Mhz clock)
1086 // To compute the ratio, nb_hf must be expressed in nbr of clock 4.33 Mhz
1087 // that's why nb_hf is divided by 3*l1_config.dpll
1088 // RATIO2(nb_hf/(3*l1_config.dpll),nb_32khz,inc_sixteen,inc_frac);
1089 // this line above is equal to the ligne below:
1090 lf=(UWORD32)((UWORD32)(3*((UWORD32)((UWORD32)(l1_config.dpll)*nb_32khz)))); //OMAPS00090550
1091 RATIO2(nb_hf,lf,inc_sixteen,inc_frac);
1092
1093 // integer part
1094 ULDP_INCSIXTEEN_UPDATE(inc_sixteen);
1095
1096 // fractional part
1097 ULDP_INCFRAC_UPDATE(inc_frac);
1098 }
1099 #endif
1100 }
1101
1102
1103 // l1ctl_gauging()
1104 // Description: management of the gauging results
1105 // At RESET state reset histogram and then go to INIT.
1106 // At INIT state, go back to RESET on each */
1107 // gauging > +- 100 ppm. If NB_INIT good gauging go to ACQUIS state.
1108 // At ACQUIS state, go back to RESET on each gauging > (+- 20ppm +- 1us). If NB_ACQU good gauging */
1109 // go to UPDATE state. Allow deep sleep feature.
1110 // At UPDATE state, count consecutive gauging >+- 1 us.
1111 // If MAX_BAD_GAUGING results go back to RESET.
1112 // Otherwise re-enable deep sleep feature and reset bad results counter.
1113
1114 void l1ctl_gauging ( UWORD32 nb_32khz, UWORD32 nb_hf)
1115 {
1116 if (l1_config.pwr_mngt == PWR_MNGT)
1117 {
1118 enum states
1119 {
1120 RESET = 0,
1121 INIT = 1,
1122 ACQUIS = 2,
1123 UPDATE = 3
1124 };
1125
1126 static UWORD8 bad_count; // bad gauging values
1127 static UWORD8 gauging_state= RESET; // RESET,INIT, ACQUIS, UPDATE
1128 static UWORD8 nb_gaug; // number of gauging in ACQUIS
1129 static UWORD8 idx,i; // index
1130 static UWORD32 root, frac; // ratio of HF and LF average
1131 UWORD32 sumLF=0 , sumHF=0; // sum of HF and LF counts
1132 double nbHF_theo;
1133
1134
1135 // AFC or TEMPERATURE variation
1136
1137 //if ( (ABS( (WORD32)(l1s.pw_mgr.previous_afc-l1s.afc) ) > AFC_VARIATION) ||
1138 // (ABS( (WORD32)(l1s.pw_mgr.previous_temp-l1s.afc) > TEMP_VARIATION) )
1139 // gauging_state = RESET;
1140
1141 // reset state machine if not in IDLE mode
1142 #if L1_GPRS
1143 if ((l1a_l1s_com.l1s_en_task[NP] != TASK_ENABLED) && (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED))
1144 gauging_state = RESET;
1145 #else
1146 if ((l1a_l1s_com.l1s_en_task[NP] != TASK_ENABLED) )
1147 gauging_state = RESET;
1148
1149 #endif
1150
1151 switch (gauging_state)
1152 {
1153
1154 case RESET:
1155 {
1156 UWORD8 i;
1157
1158 // Reset Histogram
1159 for (i=0; i < SIZE_HIST; i++)
1160 {
1161 l1s.pw_mgr.histo[i][0] = 0;
1162 l1s.pw_mgr.histo[i][1] = 0;
1163 }
1164 idx = 0;
1165 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep
1166 gauging_state = INIT;
1167 nb_gaug = NB_INIT; // counter for ACQUIS state
1168 bad_count = 0; // reset count of BAD gauging
1169
1170 #if (TRACE_TYPE != 0)
1171 l1_trace_gauging_reset();
1172 #endif
1173 }
1174
1175
1176 case INIT:
1177 {
1178
1179 // Acquire NB_INIT gauging wtw +- 100 ppm
1180
1181 if (l1a_l1s_com.mode != I_MODE) return;
1182
1183 // compute clocks ratio from measurements.
1184 RATIO(nb_hf,nb_32khz,root,frac)
1185
1186
1187 // allow [-500ppm,+100ppm] derive on 32Khz at startup.
1188 // Commenting section below for OMAPS00148004
1189 /* if (
1190 (root > l1s.pw_mgr.c_clk_min ||
1191 (root == l1s.pw_mgr.c_clk_min &&
1192 frac >= l1s.pw_mgr.c_clk_init_min) ) &&
1193 (root < l1s.pw_mgr.c_clk_max ||
1194 (root == l1s.pw_mgr.c_clk_max &&
1195 frac <= l1s.pw_mgr.c_clk_init_max ) )
1196 */
1197 if (
1198 ( l1s.pw_mgr.c_clk_min == l1s.pw_mgr.c_clk_max &&
1199 frac >= l1s.pw_mgr.c_clk_init_min &&
1200 frac <= l1s.pw_mgr.c_clk_init_max )
1201 ||
1202 ( l1s.pw_mgr.c_clk_min != l1s.pw_mgr.c_clk_max &&
1203 ( (root == l1s.pw_mgr.c_clk_min &&
1204 frac >= l1s.pw_mgr.c_clk_init_min ) ||
1205 (root > l1s.pw_mgr.c_clk_min &&
1206 root < l1s.pw_mgr.c_clk_max ) ||
1207 (root == l1s.pw_mgr.c_clk_max &&
1208 frac <= l1s.pw_mgr.c_clk_init_max ) ) )
1209 )
1210 {
1211 l1s.pw_mgr.histo[idx ][0] = nb_32khz; // init histo with the number of 32kHz
1212 l1s.pw_mgr.histo[idx++][1] = nb_hf; // init histo with the number of hf (13Mhz)
1213
1214 #if (CODE_VERSION == SIMULATION)
1215 #if (TRACE_TYPE==5)
1216 trace_ULPD("Gauging INIT Case ", l1s.actual_time.fn);
1217 #endif
1218 #endif
1219
1220 }
1221 else
1222 {
1223 // out of the allowed derive -> reset
1224 idx=0;
1225 #if (TRACE_TYPE != 0)
1226 l1_trace_gauging_reset();
1227 #endif
1228 }
1229
1230 if (idx == NB_INIT)
1231 {
1232 // enough measurement -> ACQUIS state
1233 gauging_state = ACQUIS;
1234 // compute clk ratio on count average
1235 SUM(sumHF,sumLF, NB_INIT,i) // returns sumHF and sumLF
1236 RATIO(sumHF,sumLF,root, frac) // returns root and frac*2E16, computed on the average
1237 }
1238 }
1239 break;
1240
1241
1242 case ACQUIS:
1243 {
1244 // Acquire NB_ACQU gauging at +-25ppm
1245 // with jitter +- 1 us
1246 UWORD8 n;
1247
1248 // from nb_32khz "measured"
1249 // compute nbHF_theo
1250 HFTHEO(nb_32khz,root,frac,nbHF_theo)
1251
1252 if ( (nb_hf >= (nbHF_theo - l1s.pw_mgr.c_delta_hf_acquis)) &&
1253 (nb_hf <= (nbHF_theo + l1s.pw_mgr.c_delta_hf_acquis)) )
1254 {
1255 l1s.pw_mgr.histo[idx][0] = nb_32khz;
1256 l1s.pw_mgr.histo[idx++][1] = nb_hf;
1257 idx = idx % SIZE_HIST;
1258
1259 // compute clk ratio on count average
1260 if(++nb_gaug >= SIZE_HIST) n=SIZE_HIST;
1261 else n= nb_gaug;
1262 SUM(sumHF,sumLF, n,i)
1263 RATIO(sumHF,sumLF,root, frac)
1264
1265 #if (CODE_VERSION == SIMULATION)
1266 #if (TRACE_TYPE==5)
1267 trace_ULPD("Gauging ACQUIS Case ", l1s.actual_time.fn);
1268 #endif
1269 #endif
1270
1271 if ( nb_gaug == (NB_INIT+NB_ACQU)) // NB_ACQU good gauging
1272 {
1273 gauging_state = UPDATE; // UPDATE state
1274 l1s.pw_mgr.enough_gaug = TRUE; // allow Deep sleep
1275 l1ctl_pgm_clk32(sumHF,sumLF); // clocks ratio in 4.33Mhz
1276 }
1277 }
1278 else
1279 {
1280 gauging_state = RESET;
1281 }
1282 }
1283 break;
1284
1285 case UPDATE:
1286 {
1287
1288 // Update gauging histogram
1289 // compute nbHF theoric for ratio_avg
1290 HFTHEO(nb_32khz,root,frac,nbHF_theo)
1291
1292 if ( (nb_hf >= (nbHF_theo-l1s.pw_mgr.c_delta_hf_update)) &&
1293 (nb_hf <= (nbHF_theo+l1s.pw_mgr.c_delta_hf_update)) )
1294 {
1295 l1s.pw_mgr.histo[idx][0] = nb_32khz;
1296 l1s.pw_mgr.histo[idx++][1] = nb_hf;
1297
1298 // compute clk ratio on count average
1299 SUM(sumHF,sumLF, SIZE_HIST,i)
1300 l1ctl_pgm_clk32(sumHF,sumLF); // clocks ratio in 4.33Mhz
1301
1302 l1s.pw_mgr.enough_gaug = TRUE; // allow Deep sleep
1303 bad_count = 0; // reset count of BAD gauging
1304
1305 #if (CODE_VERSION == SIMULATION)
1306 #if (TRACE_TYPE==5)
1307 trace_ULPD("Gauging UPDATE Case ", l1s.actual_time.fn);
1308 #endif
1309 #endif
1310
1311 }
1312 else
1313 {
1314 bad_count ++;
1315 if (bad_count >= MAX_BAD_GAUGING) gauging_state = RESET;
1316 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep
1317 }
1318 idx = idx % SIZE_HIST;
1319 }
1320 break;
1321 }
1322 #if (TRACE_TYPE != 0) // Trace gauging
1323 // save parameters in the corresponding structure
1324 l1s.pw_mgr.state = gauging_state;
1325 l1s.pw_mgr.lf = nb_32khz ;
1326 // WARNING WARNING, this case gauging_state == UPDATE modify the algo.
1327 // In case of trace the parameter root and frac are refresh.
1328 // it is not the case if no trace and it seems there is mistake
1329 if (gauging_state == UPDATE)
1330 {
1331 RATIO2(sumHF,sumLF,root,frac);
1332 }
1333 //End of Warning.
1334 l1s.pw_mgr.hf = nb_hf ;
1335 l1s.pw_mgr.root = root ;
1336 l1s.pw_mgr.frac = frac ;
1337 #endif // End Trace gauging
1338 }
1339 }
1340
1341
1342
1343
1344 /* GAUGING_Handler() */
1345 /* Description: update increment counter for 32Khz */
1346 /* This interrupt function computes the ratio between */
1347 /* HF/32Khz gauging counters and program ULPD increment */
1348 /* values. */
1349
1350 void GAUGING_Handler(void)
1351 {
1352 #if (CODE_VERSION != SIMULATION)
1353 if (l1_config.pwr_mngt == PWR_MNGT)
1354 {
1355 UWORD32 nb_32khz, nb_hf;
1356
1357 // Gauging task is ended
1358 l1s.pw_mgr.gauging_task = INACTIVE;
1359 #if (CHIPSET == 12) || (CHIPSET == 15)
1360 F_INTH_DISABLE_ONE_IT(C_INTH_ULPD_GAUGING_IT); // Mask ULPD GAUGING int.
1361 #else
1362 INTH_DISABLEONEIT(IQ_ULPD_GAUGING); // Mask ULPD GAUGING int.
1363 #endif
1364
1365 // Number of 32 Khz clock at the end of the gauging
1366 nb_32khz = ((*( UWORD16 *)ULDP_COUNTER_32_MSB_REG) * 65536) +
1367 (*( UWORD16 *)ULDP_COUNTER_32_LSB_REG);
1368
1369 // Number of high frequency clock at the end of the gauging
1370 // Convert it in nbr of 13 Mhz clocks (5*13=65Mhz)
1371 nb_hf = ( ((*( UWORD16 *)ULDP_COUNTER_HI_FREQ_MSB_REG) * 65536) +
1372 (*( UWORD16 *)ULDP_COUNTER_HI_FREQ_LSB_REG) ); // Divide by PLL ratio
1373
1374 l1ctl_gauging(nb_32khz, nb_hf);
1375 }
1376 #else //Simulation part
1377
1378 // Gauging task is ended
1379 l1s.pw_mgr.gauging_task = INACTIVE;
1380
1381 l1ctl_gauging(DEFAULT_32KHZ_VALUE,DEFAULT_HFMHZ_VALUE);
1382 #endif
1383 }
1384
1385
1386
1387
1388 // l1s_get_HWTimers_ticks()
1389 // Description:
1390 // evaluate the loading of the HW Timers for dep sleep
1391 // BIG SLEEP: timers CLK may be stopped (user dependant)
1392 // DEEP SLEEP:timers CLK and WTCHDOG CLK are stopped
1393 // CLKS are enabled after VTCX0+SLICER+13MHZ
1394 // setup time
1395
1396 WORD32 l1s_get_HWTimers_ticks(void)
1397 {
1398 #if (CODE_VERSION != SIMULATION)
1399 if (l1_config.pwr_mngt == PWR_MNGT)
1400 {
1401 WORD32 timer1,timer2,watchdog,HWTimer;
1402 #if (CHIPSET == 12) || (CHIPSET == 15)
1403 WORD32 watchdog_sec;
1404 #endif
1405 UWORD16 cntlreg;
1406 UWORD16 modereg;
1407 WORD32 old = 0;
1408
1409 // read Hercules Timers & Watchdog
1410 //=================================================
1411 // Tint = Tclk * (LOAD_TIM+1) * 2^(PTV+1)
1412 // Tclk = 1.2308us for Fclk=13Mhz
1413 // PTV = X (pre-scaler field)
1414 //-------------------------------------------------
1415 timer1 = timer2 = watchdog = HWTimer = -1;
1416 #if (CHIPSET == 12) || (CHIPSET == 15)
1417 watchdog_sec = -1;
1418 #endif
1419
1420 cntlreg = Dtimer1_Get_cntlreg(); // AND 0x1F
1421 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
1422 {
1423 cntlreg = cntlreg&0x1F;
1424 cntlreg >>= 2; // take PTV
1425 cntlreg = 1 << (cntlreg+1);
1426 timer1 = (WORD32) ( ((Dtimer1_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 );
1427 if (timer1 <= MIN_SLEEP_TIME) return(0);
1428 old = Dtimer1_ReadValue();
1429 HWTimer = timer1;
1430 }
1431
1432 cntlreg = Dtimer2_Get_cntlreg();
1433 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
1434 {
1435 cntlreg = cntlreg&0x1F;
1436 cntlreg >>= 2; // take PTV
1437 cntlreg = 1 << (cntlreg+1);
1438 timer2 = (WORD32) ( ((Dtimer2_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 );
1439 if (timer2 <= MIN_SLEEP_TIME) return(0);
1440 if (HWTimer == -1) HWTimer = timer2;
1441 else MIN(HWTimer,timer2)
1442 }
1443
1444 cntlreg = TIMER_Read(0); // AND 0x0f80
1445 modereg = TIMER_Read(2);
1446
1447 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
1448 {
1449 // in watchdog mode PTV is forced to 7
1450 if ( modereg & TIMER_WDOG )
1451 cntlreg |= TIMER_PTV;
1452
1453 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
1454 cntlreg = 1 << (cntlreg+1);
1455 watchdog = (WORD32) ( ((TIMER_ReadValue()+1) * cntlreg * 0.001078) / 4.615 );
1456 if (watchdog <= MIN_SLEEP_TIME) return(0);
1457 if (HWTimer == -1) HWTimer = watchdog;
1458 else MIN(HWTimer,watchdog)
1459 }
1460
1461 #if (CHIPSET == 12) || (CHIPSET == 15)
1462 /*
1463 * Secure Watchdog Timer management
1464 */
1465 cntlreg = TIMER_SEC_Read(0); // AND 0x0f80
1466 modereg = TIMER_SEC_Read(2);
1467 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
1468 {
1469 // in watchdog mode PTV is forced to 7
1470 if ( modereg & TIMER_WDOG )
1471 cntlreg |= TIMER_PTV;
1472
1473 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
1474 cntlreg = 1 << (cntlreg+1);
1475 watchdog_sec = (WORD32) ( ((TIMER_SEC_ReadValue()+1) * cntlreg * 0.001078) / 4.615 );
1476 if (watchdog_sec <= MIN_SLEEP_TIME) return(0);
1477 if (HWTimer == -1) HWTimer = watchdog_sec;
1478 else MIN(HWTimer,watchdog_sec)
1479 }
1480
1481 #endif
1482
1483 return (HWTimer);
1484 }
1485 #else // simulation part
1486 return (-1); // no HW timer in simulation
1487 #endif
1488 return(-1); //omaps00090550
1489 }
1490
1491 #if (GSM_IDLE_RAM != 0) // Compile only if GSM_IDLE_RAM enabled
1492
1493 void l1s_adapt_traffic_controller(void)
1494 {
1495 BOOL l1s_extram;
1496 UWORD8 nb_bitmap;
1497 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl;
1498
1499 gsm_idle_ram_ctl = &(l1s.gsm_idle_ram_ctl);
1500
1501 l1s_extram = FALSE;
1502
1503 for(nb_bitmap=0; ((nb_bitmap < SIZE_TAB_L1S_MONITOR) && (l1s_extram == FALSE)); nb_bitmap++)
1504 {
1505 if (nb_bitmap == 1)
1506 {
1507 l1s_extram |= (((INT_RAM_GSM_IDLE_L1S_PROCESSES1 ^ gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap]) & gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap]) != 0);
1508 }else
1509 {
1510 l1s_extram |= (gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap] != 0);
1511 }
1512 }
1513
1514 if ((l1s_extram != FALSE) && (!READ_TRAFFIC_CONT_STATE))
1515 {
1516 CSMI_TrafficControllerOn();
1517 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
1518 {
1519 l1s_trace_mftab();
1520 }
1521 #endif
1522 }
1523 }
1524 #endif
1525
1526
1527 // l1s_sleep_manager()
1528 // Description:
1529 // evaluate the loading of the system
1530 // - SIM, UART, LCD ....
1531 // - Nucleus tasks, Hisrs, timers
1532 // - Timer1, Timer2, Watchdog
1533 // program Big or Deep sleep
1534
1535 void l1s_sleep_manager()
1536 {
1537 //UWORD8 temp=0; OMAPS00090550
1538
1539 UWORD16 temp_clear_intr;
1540
1541 // fn when l1s_sleep_manager function is called
1542 #if (CODE_VERSION != SIMULATION)
1543 UWORD32 sleep_time = l1s.actual_time.fn_mod42432;
1544 #else
1545 UWORD32 sleep_time = l1s.actual_time.fn;
1546 #endif
1547
1548 #if(CHIPSET == 15)
1549 Uint8 sleep_status;
1550 #endif
1551
1552 #if (GSM_IDLE_RAM != 0)
1553 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl;
1554 BOOL flag_traffic_controller_state = 0;
1555 gsm_idle_ram_ctl = &(l1s.gsm_idle_ram_ctl);
1556
1557 #if (AUDIO_TASK == 1)
1558 gsm_idle_ram_ctl->l1s_full_exec = l1s.l1_audio_it_com;
1559 #endif
1560
1561 if (gsm_idle_ram_ctl->l1s_full_exec == TRUE)
1562 return;
1563 #endif
1564
1565 if (l1_config.pwr_mngt == PWR_MNGT)
1566 {
1567 // Power management is enabled
1568 WORD32 min_time, OSload, HWtimer,wake_up_time,min_time_gauging;
1569 UWORD32 sleep_mode;
1570 #if (ANALOG != 11)
1571 WORD32 afc_fix;
1572 #endif
1573 UWORD32 uw32_store_next_time;
1574 #if (CHIPSET != 15)
1575 static UWORD32 previous_sleep = FRAME_STOP;
1576 #endif
1577 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
1578 BOOL extended_page_mode_state = 0; //Store state of extended page mode
1579 #endif
1580 #if (CHIPSET != 15)
1581 WORD32 time_from_last_wakeup=0;
1582 #endif
1583
1584 #if (OP_BT == 1)
1585 WORD32 hci_ll_status;
1586 #endif
1587
1588 // init for trace and debug
1589 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_UNDEFINED;
1590 l1s.pw_mgr.wakeup_type = WAKEUP_FOR_UNDEFINED;
1591
1592 #if (CHIPSET != 15)
1593 time_from_last_wakeup = (sleep_time - l1s.pw_mgr.wakeup_time + 42432) % 42432;
1594 #endif
1595
1596
1597 #if (CODE_VERSION != SIMULATION)
1598 //=================================================
1599 // Protect System structures
1600 // must be called BEFORE INT_DisableIRQ() while
1601 // Nucleus does not restore IRQ/FIQ bits !!!!
1602 //=================================================
1603 OS_system_protect();
1604 //=================================================
1605 // Disable IRQ
1606 //=================================================
1607 INT_DisableIRQ();
1608 #endif // NOT SIMULATION
1609 //=================================================
1610 // check System (SIM, UART, LDC ..... )
1611 //=================================================
1612 #if (CHIPSET == 15)
1613 #if (WCP_PROF == 0)
1614 sleep_mode = Check_Peripheral_App(); /* For Locosto */
1615 #else
1616 sleep_mode = DO_NOT_SLEEP; //Check_Peripheral_App(); /* For Locosto */
1617 #endif
1618 #else
1619 sleep_mode = Cust_check_system();
1620 #endif
1621
1622 #if (GSM_IDLE_RAM != 0)
1623 //=================================================
1624 // check System (SIM, UART, LDC ..... )
1625 //=================================================
1626 gsm_idle_ram_ctl->sleep_mode = sleep_mode;
1627 #endif
1628
1629 if (sleep_mode == DO_NOT_SLEEP)
1630 {
1631 OS_system_Unprotect();
1632 // free System structure
1633 // Enable all IRQ
1634 //l1_pwmgr_irq_dis_flag = 0;
1635 #if (CODE_VERSION!=SIMULATION)
1636 INT_EnableIRQ();
1637 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_CHECK, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1638 #endif
1639 #if (GSM_IDLE_RAM != 0)
1640 gsm_idle_ram_ctl->os_load = 0;
1641 gsm_idle_ram_ctl->hw_timer = 0;
1642 #endif // GSM_IDLE_RAM
1643 return;
1644 }
1645
1646
1647 #if (OP_L1_STANDALONE == 0)
1648 /*GC_Sleep(); OMAPS00134004*/
1649 #endif
1650 //=================================================
1651 // check OS loading
1652 //=================================================
1653 OSload = OS_get_inactivity_ticks();
1654 #if (CODE_VERSION!=SIMULATION)
1655 if ((OSload >= 0) && (OSload <= MIN_SLEEP_TIME)){
1656 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_OSLOAD;
1657 l1_pwmgr_debug.fail_ret_val = OSload;
1658 }
1659 #endif //NOT SIMULATION
1660
1661 //=================================================
1662 // check HW Timers loading
1663 //=================================================
1664 HWtimer= l1s_get_HWTimers_ticks();
1665 #if (CODE_VERSION!=SIMULATION)
1666 if (HWtimer == 0){
1667 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_HWTIMER;
1668 l1_pwmgr_debug.fail_ret_val = 0;
1669 }
1670 #endif //NOT SIMULATION
1671
1672 #if (GSM_IDLE_RAM != 0)
1673 //=================================================
1674 // check OS loading
1675 //=================================================
1676 gsm_idle_ram_ctl->os_load = OSload;
1677
1678 //=================================================
1679 // check HW Timers loading
1680 //=================================================
1681 gsm_idle_ram_ctl->hw_timer = HWtimer;
1682 #endif // GSM_IDLE_RAM
1683
1684 if ((OSload > 0) && (OSload <= MIN_SLEEP_TIME))
1685 OSload =0;
1686
1687 //=================================================
1688 // check next gauging task for Packet Idle
1689 //=================================================
1690 #if L1_GPRS
1691 min_time_gauging = l1s_get_next_gauging_in_Packet_Idle();
1692 #else
1693 min_time_gauging = -1; // not used
1694 #endif
1695 #if (CODE_VERSION!=SIMULATION)
1696 if (min_time_gauging == 0){
1697 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_MINTIMEGAUGING;
1698 l1_pwmgr_debug.fail_ret_val = 0;
1699 }
1700 #endif // NOT SIMULATION
1701
1702
1703 #if (OP_BT == 1)
1704 hci_ll_status = hci_ll_ok_for_sleep();
1705 #endif
1706 // check if immediate activity planned
1707 // 0 means immediate activity
1708 // in case big sleep is choosen (sleep mode == FRAME_STOP) because of UART or SIM,
1709 // return and wait end of this activity (few TDMA frames) then check on next TDMA frames
1710 // if MS can go in deep sleep
1711 if ( !OSload
1712 || !HWtimer
1713 || !min_time_gauging
1714 #if (CHIPSET != 15)
1715 || ((sleep_mode != CLOCK_STOP) && ((l1s.pw_mgr.why_big_sleep == BIG_SLEEP_DUE_TO_UART) || (l1s.pw_mgr.why_big_sleep == BIG_SLEEP_DUE_TO_SIM)))
1716 #endif
1717 #if (OP_BT == 1)
1718 || !hci_ll_status
1719 #endif
1720 )
1721 {
1722
1723
1724
1725 #if (OP_L1_STANDALONE == 0)
1726 /*GC_Wakeup(); OMAPS00134004*/
1727 #endif
1728
1729 #if (CODE_VERSION != SIMULATION)
1730 OS_system_Unprotect();
1731 // free System structure
1732 // Enable all IRQ
1733 INT_EnableIRQ();
1734 // Wake up UART
1735 #if (GSM_IDLE_RAM != 0)
1736 // Traffic controller has to be enabled before calling SER_WakeUpUarts
1737 // as this function can access the external RAM.
1738 // Reset the flag that will indicates if an interrup will put the traffic
1739 // controller ON during that time.
1740 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE;
1741 if (!READ_TRAFFIC_CONT_STATE)
1742 {
1743 flag_traffic_controller_state = 1;
1744 CSMI_TrafficControllerOn();
1745 }
1746 #endif
1747
1748 #if (CHIPSET != 15)
1749 SER_WakeUpUarts(); // Wake up Uarts
1750 #else
1751 // To be checked if this needs a change
1752 #endif
1753
1754 #if (GSM_IDLE_RAM != 0)
1755 // The traffic controller state shall be restored as it was before
1756 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
1757 // in between and activated the traffic controller.
1758 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE))
1759 {
1760 CSMI_TrafficControllerOff();
1761 }
1762 flag_traffic_controller_state = 0;
1763 #endif
1764 #endif
1765 #if (CODE_VERSION!=SIMULATION)
1766 l1_trace_fail_sleep(FAIL_SLEEP_OSTIMERGAUGE, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1767 #endif
1768 return;
1769 }
1770 //=================================================
1771 // Select sleep duration ....
1772 //=================================================
1773 // remember: -1 means no activity planned
1774 min_time = OSload;
1775 //l1a_l1s_com.time_to_next_l1s_task is UW32, min_time is W32. Max value of l1a_l1s_com.time_to_next_l1s_task will be 2p31
1776 //and ,min_time max value will be 2p30. If min_time > l1a_l1s_com.time_to_next_l1s_task,
1777 //means MSB of l1a_l1s_com.time_to_next_l1s_task is zero. so, we can use- uw32_store_next_time & 0x7FFFFFFF
1778 uw32_store_next_time = l1a_l1s_com.time_to_next_l1s_task;
1779
1780 if (min_time == -1) min_time = (WORD32)uw32_store_next_time;
1781 //else MIN(min_time, (WORD32)l1a_l1s_com.time_to_next_l1s_task)
1782 else
1783 {
1784 if(min_time > l1a_l1s_com.time_to_next_l1s_task) min_time = uw32_store_next_time & 0x7FFFFFFF;
1785 //else min_time = min_time;
1786 }
1787 if (HWtimer != -1) MIN(min_time, HWtimer)
1788 if (min_time_gauging != -1) MIN(min_time, min_time_gauging)
1789
1790 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
1791 // to trace the Wake up source
1792 // depending of min_time choose the wakeup_type
1793 l1s.pw_mgr.wakeup_type = WAKEUP_FOR_L1_TASK;
1794 if (min_time == l1a_l1s_com.time_to_next_l1s_task) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_L1_TASK;
1795 if (min_time == HWtimer) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_HW_TIMER_TASK;
1796 if (min_time == min_time_gauging) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_GAUGING_TASK;
1797 if (min_time == OSload) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_OS_TASK;
1798 #endif
1799
1800 //=================================================
1801 // Choose DEEP or BIG SLEEP
1802 //=================================================
1803 if ( ((l1s.pw_mgr.mode_authorized == DEEP_SLEEP) && (sleep_mode == CLOCK_STOP)) ||
1804 ((l1s.pw_mgr.mode_authorized == ALL_SLEEP) && (sleep_mode == CLOCK_STOP)) )
1805 {
1806 // Check now gauging histogramme or if in inactive period of cell selection
1807 #if (W_A_DSP_IDLE3 == 1) && (CODE_VERSION!=SIMULATION)
1808 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) &&
1809 ( l1s_dsp_com.dsp_ndb_ptr->d_dsp_state == C_DSP_IDLE3))
1810 #else
1811 #if (CHIPSET == 12) || (CHIPSET == 15)
1812 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) &&
1813 !CLKM_READ_nIDLE3)
1814 #else
1815 if ((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0))
1816 #endif
1817 #endif
1818 l1s.pw_mgr.sleep_performed = CLOCK_STOP;
1819 else
1820 {
1821 // BIG SLEEP is chosen : check the reason
1822 l1s.pw_mgr.sleep_performed = FRAME_STOP;
1823 if ((l1s.pw_mgr.enough_gaug != TRUE) && (l1a_l1s_com.mode != CS_MODE0))
1824 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_GAUGING;
1825 else
1826 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_DSP_TRACES;
1827 }
1828 }
1829 if (l1s.pw_mgr.mode_authorized == BIG_SLEEP)
1830 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_SLEEP_MODE;
1831
1832 if ( ((l1s.pw_mgr.mode_authorized == BIG_SLEEP) && (sleep_mode >= FRAME_STOP)) ||
1833 ((l1s.pw_mgr.mode_authorized >= DEEP_SLEEP) && (sleep_mode == FRAME_STOP)) )
1834 l1s.pw_mgr.sleep_performed = FRAME_STOP;
1835
1836
1837
1838 #if (CHIPSET != 15)
1839 if ((previous_sleep == CLOCK_STOP) && (time_from_last_wakeup < 7))
1840 {
1841 #if (CODE_VERSION != SIMULATION)
1842 OS_system_Unprotect(); // free System structure
1843 INT_EnableIRQ(); // Enable all IRQ
1844 #if (GSM_IDLE_RAM != 0)
1845 // Traffic controller has to be enabled before calling SER_WakeUpUarts
1846 // as this function can access the external RAM.
1847 // Reset the flag that will indicates if an interrup will put the traffic
1848 // controller ON during that time.
1849 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE;
1850 if (!READ_TRAFFIC_CONT_STATE)
1851 {
1852 flag_traffic_controller_state = 1;
1853 CSMI_TrafficControllerOn();
1854 }
1855 #endif
1856
1857
1858 SER_WakeUpUarts(); // Wake up Uarts
1859
1860
1861
1862 #if (GSM_IDLE_RAM != 0)
1863 // The traffic controller state shall be restored as it was before
1864 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
1865 // in between and activated the traffic controller.
1866 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE))
1867 {
1868 CSMI_TrafficControllerOff();
1869 }
1870 flag_traffic_controller_state = 0;
1871 #endif
1872 #endif // NOT SIMULATION
1873 return;
1874 }
1875 #else // CHIPSET == 15
1876
1877
1878
1879 if (l1s.pw_mgr.sleep_performed == CLOCK_STOP)
1880 {
1881
1882 #if (CODE_VERSION != SIMULATION)
1883 UWORD8 local_sleep_status;
1884
1885
1886 local_sleep_status = Peripheral_interface[UART_ID](SLEEP_CMD);
1887 sleep_status = local_sleep_status;
1888 if(local_sleep_status == 0)
1889 {
1890 l1_pwmgr_debug.fail_id = UART_ID;
1891 l1_pwmgr_debug.fail_ret_val = sleep_status;
1892 }
1893
1894 OS_system_Unprotect();
1895 local_sleep_status = Peripheral_interface[MADC_AS_ID](SLEEP_CMD); /* Call MADC & Stereo Sleep before I2C */
1896 OS_system_protect();
1897 sleep_status &= local_sleep_status;
1898 if(local_sleep_status == 0)
1899 {
1900 l1_pwmgr_debug.fail_id = MADC_AS_ID;
1901 l1_pwmgr_debug.fail_ret_val = sleep_status;
1902 }
1903
1904 local_sleep_status = Peripheral_interface[USB_ID](SLEEP_CMD);
1905 sleep_status &= local_sleep_status;
1906 if(local_sleep_status == 0)
1907 {
1908 l1_pwmgr_debug.fail_id = USB_ID;
1909 l1_pwmgr_debug.fail_ret_val = sleep_status;
1910 }
1911
1912 local_sleep_status = Peripheral_interface[USIM_ID](SLEEP_CMD);
1913 sleep_status &= local_sleep_status;
1914 if(local_sleep_status == 0)
1915 {
1916 l1_pwmgr_debug.fail_id = USIM_ID;
1917 l1_pwmgr_debug.fail_ret_val = sleep_status;
1918 }
1919
1920 local_sleep_status = Peripheral_interface[I2C_ID](SLEEP_CMD);
1921 sleep_status &= local_sleep_status;
1922 if(local_sleep_status == 0)
1923 {
1924 l1_pwmgr_debug.fail_id = I2C_ID;
1925 l1_pwmgr_debug.fail_ret_val = sleep_status;
1926 }
1927
1928 local_sleep_status = Peripheral_interface[LCD_ID](SLEEP_CMD);
1929 sleep_status &= local_sleep_status;
1930 if(local_sleep_status == 0)
1931 {
1932 l1_pwmgr_debug.fail_id = LCD_ID;
1933 l1_pwmgr_debug.fail_ret_val = sleep_status;
1934 }
1935
1936 local_sleep_status = Peripheral_interface[CAMERA_ID](SLEEP_CMD);
1937 sleep_status &= local_sleep_status;
1938 if(local_sleep_status == 0)
1939 {
1940 l1_pwmgr_debug.fail_id = CAMERA_ID;
1941 l1_pwmgr_debug.fail_ret_val = sleep_status;
1942 }
1943 local_sleep_status = Peripheral_interface[BCI_ID](SLEEP_CMD);
1944 sleep_status &= local_sleep_status;
1945 if(local_sleep_status == 0)
1946 {
1947 l1_pwmgr_debug.fail_id = BCI_ID;
1948 l1_pwmgr_debug.fail_ret_val = sleep_status;
1949 }
1950
1951 #endif // NOT SIMULATION
1952 if(!sleep_status)
1953 {
1954
1955 #if (OP_L1_STANDALONE == 0)
1956 /*GC_Wakeup(); OMAPS00134004*/
1957 #endif
1958
1959 #if (CODE_VERSION != SIMULATION)
1960 OS_system_Unprotect();
1961 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_SLEEP, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1962 #endif // NOT SIMULATION
1963 local_sleep_status = Peripheral_interface[UART_ID](WAKE_CMD); //OMAPS00090550
1964 local_sleep_status = Peripheral_interface[USB_ID](WAKE_CMD); //OMAPS00090550
1965 local_sleep_status = Peripheral_interface[USIM_ID](WAKE_CMD); //OMAPS00090550
1966 local_sleep_status = Peripheral_interface[I2C_ID](WAKE_CMD);//OMAPS00090550
1967 local_sleep_status = Peripheral_interface[LCD_ID](WAKE_CMD);//OMAPS00090550
1968 local_sleep_status = Peripheral_interface[CAMERA_ID](WAKE_CMD);//OMAPS00090550
1969 local_sleep_status = Peripheral_interface[MADC_AS_ID](WAKE_CMD);//OMAPS00090550
1970 local_sleep_status = Peripheral_interface[BCI_ID](WAKE_CMD); //wake up for battery charger interface//OMAPS00090550
1971 INT_EnableIRQ();
1972 return;
1973 }
1974 }
1975
1976 #endif // CHIPSET == 15
1977
1978 #if (CHIPSET != 15)
1979 // update previous sleep
1980 previous_sleep = l1s.pw_mgr.sleep_performed;
1981 #endif
1982
1983
1984 #if (CODE_VERSION != SIMULATION)
1985
1986 #if (CHIPSET == 12) || (CHIPSET == 15)
1987 F_INTH_DISABLE_ONE_IT(C_INTH_FRAME_IT); // mask Frame int.
1988 #else
1989 INTH_DISABLEONEIT(IQ_FRAME); // mask Frame int.
1990 #endif
1991 #endif
1992
1993 //=====================================================
1994 // if CLOCK_STOP : stop RF, TPU, asleep Omega, DPLL, SPI
1995 // if FRAME_STOP : asleep Omega, SPI
1996 //=====================================================
1997 #if (CODE_VERSION != SIMULATION)
1998 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1999 {
2000 // ==== STop RF and TPU..... ===================
2001
2002 //L1_trace_string("Proceeding to Deep Sleep\n");
2003
2004
2005 l1dmacro_RF_sleep();
2006
2007 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =TPU_CTRL_RESET |
2008 // TSP_CTRL_RESET |TPU_CTRL_CLK_EN;
2009 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =0;
2010
2011 //===== SET default value for gauging =========
2012 // If we have come in here during the inactive period of cell
2013 // selection, then load the ULPD timers with default values
2014 // (used when the MS lost the network: in this case the deep sleep may be used)
2015 if (l1a_l1s_com.mode == CS_MODE0)
2016 {
2017 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE*8,DEFAULT_32KHZ_VALUE);
2018 }
2019
2020 #if (CHIPSET == 15)
2021
2022
2023 /* These APIs are to be provided by BSP */
2024 // Disable_APC_BG();
2025 gpio_sleep(); //LCD_Floating Pin Fix
2026 DBB_Configure_DS();
2027
2028 //gpio_sleep(); //LCD_Floating Pin Fix
2029
2030 #endif
2031
2032
2033 }
2034 #if (CHIPSET == 15)
2035 else
2036 {
2037 //DBB_Configure_BS(); // Not used
2038 }
2039 #endif
2040
2041
2042 #if (CHIPSET == 15)
2043 // The following command writes '0' into CKM_OCPCLK register in DRP;
2044 // This is done before disabling DPLL
2045 // CKM_OCPCLK (R/W) = Address 0xFFFF040C
2046 // Bit 0: 0 ?OCP clock is the DCXO clock.
2047 // 1 ?OCP clock is the divided DSP clock
2048 // Bit 31:1 Not Used
2049 (drp_regs->CKM_OCPCLKL) &= (~(0x1));
2050 asm(" NOP");
2051 asm(" NOP");
2052 #endif
2053
2054
2055
2056 //==============================================
2057 // disable DPLL (do not provide clk to DSP & RIF (RIF))
2058 //==============================================
2059 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
2060 // disable DPLL (do not provide clk to DSP & RIF (Bridge))
2061 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= CLKM_DPLL_DIS ; /* CLKM_BRIDGE_DIS removed by Ranga*/
2062 #endif
2063
2064 //==============================================
2065 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB)
2066 //==============================================
2067 #if (ANALOG != 11)
2068 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc);
2069 #else
2070 // Nothing to be done as it should be handled by BSP_TWL3029_Configure_DS/BS
2071 #endif
2072
2073 #if (OP_BT == 1)
2074 hci_ll_go_to_sleep();
2075 #endif
2076 //=================================================
2077 // STop SPI .....
2078 //=================================================
2079
2080 #if(CHIPSET != 15)
2081 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED
2082 #endif
2083 #endif // NOT SIMULATION
2084
2085
2086 //=================================================
2087 // CQ19599: For Calypso+ chipset, extended page mode
2088 // shall be disabled before entering deep sleep and
2089 // restored at wake up
2090 //=================================================
2091 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
2092 extended_page_mode_state = (BOOL) f_memif_extended_page_mode_read_bit();
2093 f_memif_extended_page_mode_disable();
2094 #endif
2095
2096 //=================================================
2097 // Init the timer :
2098 //
2099 // a margin of 4 frames (>MIN_SLEEP_TIME) is taken
2100 // when evaluating system loading, because 1 frame
2101 // is lost for wakeup only, and because sleep
2102 // duration less than 1 frame is not worth ....
2103 //
2104 // 1 2 3 4 5 6 7 8
2105 // SLEEP_CTRL SLEEP WAKEUP TASK (RF,Timer, ...)
2106 //
2107 //=================================================
2108 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0)
2109 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2110 {
2111 // DEEP SLEEP -> need time to setup afc and rf
2112 wake_up_time = min_time - l1_config.params.rf_wakeup_tpu_scenario_duration;
2113 #if (CODE_VERSION == NOT_SIMULATION)
2114 // Sleep one more TDMA - this is done as part of merging init and TPU control
2115 wake_up_time += 1;
2116 #endif
2117
2118 }
2119 else
2120 // BIG SLEEP
2121 wake_up_time = min_time - 1;
2122
2123
2124
2125 #if (CODE_VERSION != SIMULATION)
2126 if ( wake_up_time >= MAX_GSM_TIMER)
2127 ULDP_TIMER_INIT(MAX_GSM_TIMER);
2128 else
2129 ULDP_TIMER_INIT(wake_up_time);
2130
2131 ULDP_TIMER_LD; // Load the timer
2132
2133 // BUG3060. Clear pending IQ_TGSM from ULPD. This could happen in case ULPD was frozen
2134 // with zero into its GSM counter. In that case, the interrupt is still pending
2135 // and if it is not cleared, it wakes the board up just after switching the clock.
2136 // Clear it into the ULPD...
2137 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on
2138 //reading the register.
2139 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM;
2140 // ... and next into the INTH. (must be done in this order
2141
2142 #if (CHIPSET == 12) || (CHIPSET == 15)
2143 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT);
2144 F_INTH_ENABLE_ONE_IT(C_INTH_TGSM_IT);
2145 #else
2146 INTH_RESETONEIT(IQ_TGSM); // clear TDMA IRQ
2147 INTH_ENABLEONEIT(IQ_TGSM); // Unmask ULPD GSM int.
2148 #endif
2149
2150 #if (GSM_IDLE_RAM != 0)
2151 if (READ_TRAFFIC_CONT_STATE)
2152 {
2153 CSMI_TrafficControllerOff();
2154 }
2155 #endif
2156
2157 ULDP_TIMER_START; // start count down
2158
2159
2160 #if (GSM_IDLE_RAM_DEBUG == 1)
2161 (*( volatile unsigned short* )(0xFFFE4802)) &= ~ (1 << 2); // GPIO-2=0
2162 #endif
2163
2164 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2165 // DEEP SLEEP
2166 {
2167 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
2168 // specific sleep for WCP
2169 arm7_deep_sleep();
2170 #else // NO OP_WCP
2171 #if (W_A_CALYPSO_BUG_01435 == 1)
2172 f_arm_sleep_cmd(DEEP_SLEEP);
2173 #else
2174 //EMIF_SetConfReg ( 0, 0, 2 ,1 ,0);
2175 asm(" NOP");
2176 asm(" NOP");
2177 asm(" NOP");
2178 asm(" NOP");
2179 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_DEEP_SLEEP); // set deep sleep mode
2180 asm(" NOP");
2181 asm(" NOP");
2182 asm(" NOP");
2183 asm(" NOP");
2184 // set deep sleep mode in case it is not set back by hardware
2185 *((volatile UWORD16 *)CLKM_ARM_CLK) |= (CLKM_DEEP_SLEEP);
2186
2187 //EMIF_SetConfReg ( 0, 0, 2 ,0 ,0);
2188 // *((volatile UWORD16 *)CLKM_ARM_CLK) &= 0xFFFF; // set deep sleep mode
2189 // *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_MCLK_EN); // For Debug only
2190
2191
2192 #endif
2193 #endif // OP_WCP
2194 }
2195 else
2196 {
2197 // BIG SLEEP / l1s.pw_mgr.sleep_performed == FRAME_STOP
2198
2199 //==========================================================
2200 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized
2201 //==========================================================
2202
2203 #if(CHIPSET != 15)
2204 UWORD16 clocks_stopped; //OMAPS90550- new
2205 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
2206 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
2207 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN);
2208 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
2209 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001);
2210 #else
2211 // Nothing to be done as it is taken care by Locosto_Configure_BS
2212 #endif
2213
2214 #if (W_A_CALYPSO_BUG_01435 == 1)
2215 f_arm_sleep_cmd(BIG_SLEEP);
2216 #else
2217
2218 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_MCLK_EN); // set big sleep mode
2219 #endif
2220 }
2221 #else // Simulation part
2222 l1s.pw_mgr.sleep_duration = wake_up_time;
2223 hw.deep_sleep_en = 1;
2224 status = NU_Suspend_Task(&L1S_task);
2225 // check status value...
2226 if (status)
2227 {
2228 #if (TRACE_TYPE==5)
2229 sprintf(errormsg,"Error somewhere in the L1S application to suspend : deep sleep\n");
2230 log_sim_error(ERR);
2231 #endif
2232 EXIT;
2233 }
2234 #endif // SIMULATION
2235
2236 //=================================================
2237 // Wake-up procedure
2238 //=================================================
2239 // Restore L1 data base, Nucleus, HW Timers ....
2240 //=================================================
2241
2242 #if (GSM_IDLE_RAM_DEBUG == 1)
2243 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1
2244 #endif
2245
2246
2247 l1s_wakeup();
2248
2249 #if (CHIPSET == 15)
2250 // The following command writes '1' into CKM_OCPCLK register in DRP;
2251 // This is done after the DPLL is up
2252 // CKM_OCPCLK (R/W) = Address 0xFFFF040C
2253 // Bit 0: 0 ?OCP clock is the DCXO clock.
2254 // 1 ?OCP clock is the divided DSP clock
2255 // Bit 31:1 Not Used
2256 (drp_regs->CKM_OCPCLKL) |= (0x1);
2257 asm(" NOP");
2258 asm(" NOP");
2259 #endif
2260
2261 l1s.pw_mgr.wakeup_time = l1s.actual_time.fn_mod42432;
2262
2263 if (l1s.pw_mgr.wakeup_time == sleep_time)
2264 // sleep duration == 0 -> wakeup in the same frame as sleep
2265 l1s.pw_mgr.wakeup_type = WAKEUP_ASYNCHRONOUS_SLEEP_DURATION_0;
2266
2267 #if (GSM_IDLE_RAM != 0)
2268 // Update counters with sleep duration -> will be used case expiration in next wake up phase before traffic controller is enabled by msg sending
2269 gsm_idle_ram_ctl->os_load -= (l1s.pw_mgr.sleep_duration);
2270 gsm_idle_ram_ctl->hw_timer -= (l1s.pw_mgr.sleep_duration);
2271
2272 if (l1s.pw_mgr.wakeup_type != WAKEUP_FOR_L1_TASK)
2273 {
2274 if (!READ_TRAFFIC_CONT_STATE)
2275 {
2276 CSMI_TrafficControllerOn();
2277 }
2278 }
2279 #endif
2280 //=================================================
2281 //if CLOCK_STOP : restart TPU and RF....
2282 //=================================================
2283 #if (CODE_VERSION != SIMULATION)
2284 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2285 {
2286 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN;
2287 UWORD8 local_sleep_status;
2288
2289
2290 #if (CHIPSET == 15)
2291
2292 DBB_Wakeup_DS();
2293
2294 gpio_wakeup(); //LCD_Floating Pin Fix
2295
2296 /* These APIs to be provided by BSP */
2297 //Enable_APC_BG();
2298 //BT_Wakeup();
2299 //IRDA_Wakeup();
2300 local_sleep_status = Peripheral_interface[UART_ID](WAKE_CMD); //OMAPS00090550
2301 local_sleep_status = Peripheral_interface[USB_ID](WAKE_CMD);//OMAPS00090550
2302 local_sleep_status = Peripheral_interface[USIM_ID](WAKE_CMD);//OMAPS00090550
2303 local_sleep_status = Peripheral_interface[I2C_ID](WAKE_CMD);//OMAPS00090550
2304 local_sleep_status = Peripheral_interface[LCD_ID](WAKE_CMD);//OMAPS00090550
2305 local_sleep_status = Peripheral_interface[CAMERA_ID](WAKE_CMD);//OMAPS00090550
2306
2307 OS_system_Unprotect();
2308 local_sleep_status = Peripheral_interface[MADC_AS_ID](WAKE_CMD);//OMAPS00090550
2309 local_sleep_status = Peripheral_interface[BCI_ID](WAKE_CMD); //wake up for battery charger//OMAPS00090550
2310 OS_system_protect();
2311 //added for OMAPS00090550 warning removal
2312 if(local_sleep_status == 0)
2313 {
2314 l1_pwmgr_debug.fail_ret_val = local_sleep_status;
2315 }
2316 //upto this OMAPS00090550
2317
2318
2319 #endif
2320 l1dmacro_RF_wakeup();
2321
2322 }
2323
2324 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
2325 // enable DPLL (provide clk to DSP & RIF(Bridge) in small/big sleep)
2326 // On CALYPSO, BRIDGE clock can be cut according to the ARM sleep mode even during DMA transfer
2327 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS | CLKM_BRIDGE_DIS);
2328 #elif (CHIPSET == 12)
2329 // Nothing to be done because if DSP wants clock, it will exit from IDLE3 mode, which wakes up the DPLL
2330 #elif (CHIPSET == 15)
2331 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS);
2332 #endif
2333
2334 //=================================================
2335 //if CLOCK_STOP or FRAME-STOP : ReStart SPI
2336 //=================================================
2337 #if(CHIPSET != 15)
2338 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED
2339 #endif
2340
2341 //=================================================
2342 // Wake up ABB
2343 //=================================================
2344 #if (ANALOG != 11)
2345 ABB_wakeup(l1s.pw_mgr.sleep_performed, l1s.afc);
2346 #else
2347 // Nothing to be done here as it will be handled by BSP_TWL3029_Wakeup_DS/BS
2348 #endif
2349
2350 #if (OP_BT == 1)
2351 hci_ll_wake_up();
2352 #endif
2353 #endif //CODE VERSION
2354
2355 //=================================================
2356 // CQ19599: For Calypso+ chipset, restore the extended
2357 // page mode if it was enabled before entering in sleep
2358 //=================================================
2359 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
2360 if ( extended_page_mode_state != 0 )
2361 f_memif_extended_page_mode_enable();
2362 #endif
2363
2364 #if (OP_L1_STANDALONE == 0)
2365 /*GC_Wakeup(); OMAPS00134004*/
2366 #endif
2367
2368 #if (CODE_VERSION != SIMULATION)
2369 //=================================================
2370 // enable IRQ
2371 //=================================================
2372 OS_system_Unprotect();
2373 #endif
2374
2375 #if (TRACE_TYPE != 0)
2376 if (l1a_l1s_com.mode != CS_MODE0) // in this mode the trace prevent from going to deep sleep due to UART activity
2377 {
2378 #if (GSM_IDLE_RAM == 0)
2379 l1_trace_sleep(sleep_time,l1s.actual_time.fn_mod42432,l1s.pw_mgr.sleep_performed,l1s.pw_mgr.wakeup_type,l1s.pw_mgr.why_big_sleep, l1s.pw_mgr.wake_up_int_id);
2380 #else
2381 l1_trace_sleep_intram(sleep_time,l1s.actual_time.fn_mod42432,l1s.pw_mgr.sleep_performed,l1s.pw_mgr.wakeup_type,l1s.pw_mgr.why_big_sleep, l1s.pw_mgr.wake_up_int_id);
2382 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
2383 l1s_trace_mftab();
2384 #endif
2385 #endif
2386 }
2387 l1s.pw_mgr.wake_up_int_id = 0;
2388 #endif
2389
2390 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
2391 trace_info.sleep_performed = TRUE;
2392 #endif
2393
2394 #if (CODE_VERSION != SIMULATION)
2395
2396 //=================================================
2397 // enable IRQ
2398 //=================================================
2399 INT_EnableIRQ();
2400
2401 //=================================================
2402 // Be careful:in case of asynchronous wake-up after sleep
2403 // an IT_TDMA may be unmasked and executed just after OS_system_Unprotect().
2404 // As we already are inside an hisr(), it implies the execution of an another hisr().
2405 // In order to avoid issues with the execution of an hisr() inside the hisr()
2406 // do not add code here after !!!
2407 // if possible respect this rule !
2408 //=================================================
2409
2410 //=================================================
2411 // wake-up UARTs
2412 //this function must be call after the UART interrupt,
2413 //it means after the function INT_EnableIRQ()
2414 //=================================================
2415 {
2416 #if (GSM_IDLE_RAM != 0)
2417 // Traffic controller has to be enabled before calling SER_WakeUpUarts
2418 // as this function can access the external RAM.
2419 // Reset the flag that will indicates if an interrup will put the traffic
2420 // controller ON during that time.
2421 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE;
2422 if (!READ_TRAFFIC_CONT_STATE)
2423 {
2424 flag_traffic_controller_state = 1;
2425 CSMI_TrafficControllerOn();
2426 }
2427 #endif
2428
2429
2430
2431 #if (CHIPSET != 15)
2432 SER_WakeUpUarts(); // Wake up Uarts
2433 #else
2434 // To be checked if this needs a change
2435 #endif
2436
2437
2438 #if (GSM_IDLE_RAM != 0)
2439 // The traffic controller state shall be restored as it was before
2440 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
2441 // in between and activated the traffic controller.
2442 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE))
2443 {
2444 CSMI_TrafficControllerOff();
2445 }
2446 flag_traffic_controller_state = 0;
2447 #endif
2448 }
2449 #endif // NOT SIMULATION
2450 }
2451 }
2452
2453 // l1s_wakeup() */
2454 // Description: wake-up of the MCU from GSM Timer it OR unscheduled wake-up
2455 // This function read the TPU timer and fix the :
2456 // - system clock
2457 // - Nucleus timers
2458 // - L1 frame counter
2459 // - L1 next task counter
2460 // - Hardware timers
2461
2462 void l1s_wakeup(void)
2463 {
2464 #if (CODE_VERSION != SIMULATION)
2465 if (l1_config.pwr_mngt == PWR_MNGT)
2466 {
2467 // Restore interrupts ....
2468
2469 #if (CHIPSET == 12) || (CHIPSET == 15)
2470 // mask TGSM int.
2471 F_INTH_DISABLE_ONE_IT(C_INTH_TGSM_IT);
2472 #else
2473 INTH_DISABLEONEIT(IQ_TGSM); // mask TGSM int.
2474 #endif
2475
2476 #if (CHIPSET == 12) || (CHIPSET == 15)
2477 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up
2478 if ( l1s.pw_mgr.wake_up_int_id >= 256 )
2479 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM)+100;
2480 #else
2481 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up
2482 if ( l1s.pw_mgr.wake_up_int_id >= 256 )
2483 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)+100;
2484 #endif
2485
2486 // clear pending IQ_FRAME it and unmask it
2487 #if (CHIPSET == 12) || (CHIPSET == 15)
2488 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
2489 F_INTH_ENABLE_ONE_IT(C_INTH_FRAME_IT); // Unmask FRAME int.
2490 #else
2491 INTH_RESETONEIT(IQ_FRAME); // clear TDMA IRQ
2492 INTH_ENABLEONEIT(IQ_FRAME); // Unmask FRAME int.
2493 #endif
2494
2495 #if (CHIPSET == 8)
2496 // if deep sleep
2497 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2498 {
2499 UWORD8 i;
2500
2501 // Loop with check whether DPLL is locked: 100 us max.
2502 for (i=0;i<16;i++)
2503 {
2504 if (DPLL_READ_DPLL_LOCK)
2505 break;
2506 }
2507 wait_ARM_cycles(convert_nanosec_to_cycles(50000)); // 50us
2508
2509 // Enable DPLL
2510 //--------------------------------------------------
2511 DPLL_SET_PLL_ENABLE;
2512
2513 // Loop with check whether DPLL is locked: 100 us max.
2514 for (i=0;i<16;i++)
2515 {
2516 if (DPLL_READ_DPLL_LOCK)
2517 break;
2518 }
2519 wait_ARM_cycles(convert_nanosec_to_cycles(50000)); // 50us
2520 } // if deep sleep
2521
2522 #endif // CHIPSET == 8
2523
2524 //=================================================
2525 //Restart PERIPHERALS clocks if necessary after a big sleep period
2526 // WARNING: restart other clocks modules!!!
2527 //=================================================
2528
2529
2530 #if(CHIPSET == 15)
2531 if(l1s.pw_mgr.sleep_performed == FRAME_STOP )
2532 {
2533
2534 //ABB_Wakeup_BS(); //Not Used
2535 //DBB_Wakeup_BS(); //Not Used
2536 }
2537 #else
2538 // if big sleep
2539 if ( l1s.pw_mgr.sleep_performed == FRAME_STOP )
2540 {
2541
2542 UWORD16 clocks_stopped;
2543 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
2544 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
2545 *((volatile UWORD16 *)ARMIO_CNTL_REG) |= ARMIO_CLOCKEN;
2546 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
2547 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) |= 0x0001;
2548
2549 }
2550 #endif
2551
2552
2553 /***************************************************/
2554 /* Compute effective sleeping time .... */
2555 /* */
2556 /* sleep duration is */
2557 /* - TIMER_INIT */
2558 /* - or TIMER_INIT - TIMER_VALUE */
2559 /* */
2560 /* "frame_adjust" = TRUE for unschedules wake-up */
2561 /* FALSE for scheduled wake-up */
2562 /***************************************************/
2563 l1s.pw_mgr.frame_adjust = l1s_compute_wakeup_ticks();
2564
2565 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
2566 if ((l1s.pw_mgr.frame_adjust == TRUE))
2567 l1s.pw_mgr.wakeup_type = WAKEUP_BY_ASYNC_INTERRUPT;
2568 #endif
2569
2570
2571 /* Fix Frame */
2572
2573 l1s_recover_Frame();
2574
2575
2576 /* Fix Hardware Timers */
2577 /* */
2578 /* GSM 1.0 : ntd - timer clock not cut */
2579 /* */
2580 /* GSM 1.5 : deep sleep - need to fix timers */
2581
2582 if (l1s.pw_mgr.sleep_performed == CLOCK_STOP)
2583 l1s_recover_HWTimers();
2584
2585
2586 /* Fix Os */
2587
2588 if (Cust_recover_Os()) l1s.pw_mgr.Os_ticks_required = TRUE;
2589 }
2590 #else // SIMULATION part
2591 // update L1 timers (FN,...)
2592 l1s_recover_Frame();
2593 #endif
2594 }
2595
2596
2597
2598 /* l1s_wakeup_adjust() */
2599 /* Description: 1 frame adjust a fter unscheduled wake-up */
2600 /* This function fix the : */
2601 /* - system clock */
2602 /* - Nucleus timers */
2603 /* - L1 frame counter */
2604 /* - L1 next task counter */
2605 /* - Hardware timers */
2606
2607
2608 void l1s_wakeup_adjust ()
2609 {
2610 #if (CODE_VERSION != SIMULATION)
2611 if (l1_config.pwr_mngt == PWR_MNGT)
2612 {
2613
2614 UWORD32 previous_sleep_time;
2615
2616 /***************************************************/
2617 // Freeze GSM Timer .... */
2618 /***************************************************/
2619 ULDP_TIMER_FREEZE;
2620
2621 /***************************************************/
2622 // Compute effective sleeping time ....
2623 //
2624 // compute sleep duration
2625 // - TIMER_INIT
2626 // - or TIMER_INIT - TIMER_VALUE
2627 /***************************************************/
2628 // save sleep duration that was computed at "unscheduled wakeup"
2629 previous_sleep_time = l1s.pw_mgr.sleep_duration;
2630
2631 l1s_compute_wakeup_ticks();
2632
2633 // reset flag for adjustment request ....
2634 l1s.pw_mgr.frame_adjust = FALSE;
2635
2636 // fix sleep duration
2637 // => compute difference with duration computed at
2638 // "unscheduled wakeup"
2639 l1s.pw_mgr.sleep_duration -= previous_sleep_time;
2640
2641 // adjust system with 1 frame IF NECESSARY ....
2642 if (l1s.pw_mgr.sleep_duration)
2643 {
2644 /***************************************************/
2645 /* Fix Frame */
2646 /***************************************************/
2647 l1s_recover_Frame();
2648
2649 /***************************************************/
2650 /* Fix Os */
2651 /***************************************************/
2652 if (Cust_recover_Os()) l1s.pw_mgr.Os_ticks_required = TRUE;
2653 }
2654 }
2655 #endif
2656 }
2657
2658
2659 /*-------------------------------------------------------*/
2660 /* l1s_compute_wakeup_Ticks() */
2661 /*-------------------------------------------------------*/
2662 /* */
2663 /* Description: wake-up */
2664 /* ------------ */
2665 /* This function compute the sleep duration according to */
2666 /* current value of count down counter. */
2667 /* - if TIMER_VALUE = 0 it returns TIMER_INIT */
2668 /* - else it returns TIMER_INIT-TIMER_VALUE*/
2669 /* */
2670 /*-------------------------------------------------------*/
2671 BOOL l1s_compute_wakeup_ticks(void)
2672 {
2673 UWORD16 temp_clear_intr;
2674 #if (CODE_VERSION != SIMULATION)
2675 if (l1_config.pwr_mngt == PWR_MNGT)
2676 {
2677 // read current value of count down counter
2678 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_VALUE;
2679
2680 // if count down=0 it's a scheduled wake-up....
2681 if (l1s.pw_mgr.sleep_duration == 0)
2682 {
2683 // read sleeping planned value in TPU INIT register
2684 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT;
2685 // INTH is different from the ULPD interrupt -> aynchronous wakeup
2686 #if (CHIPSET == 12) || (CHIPSET == 15)
2687 if (l1s.pw_mgr.wake_up_int_id != C_INTH_TGSM_IT)
2688 #else
2689 if (l1s.pw_mgr.wake_up_int_id != IQ_TGSM)
2690 #endif
2691 {
2692 l1s.pw_mgr.wakeup_type = WAKEUP_ASYNCHRONOUS_ULPD_0;
2693 // RESET IT_ULPD in ULPD module
2694 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on reading the register
2695 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM;
2696 #if (CHIPSET == 12) || (CHIPSET == 15)
2697 // RESET IQ_TGSM (IT_ULPD) in IT register
2698 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT);
2699 // RESET IQ_FRAME in IT register
2700 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
2701 l1s.pw_mgr.wake_up_int_id = C_INTH_TGSM_IT;
2702 #else
2703 // RESET IQ_TGSM (IT_ULPD) in IT register
2704 INTH_RESETONEIT(IQ_TGSM);
2705 // RESET IQ_FRAME in IT register
2706 INTH_RESETONEIT(IQ_FRAME);
2707 l1s.pw_mgr.wake_up_int_id = IQ_TGSM;
2708 #endif
2709 return(FALSE);
2710 }
2711 else
2712 return(FALSE);
2713 }
2714 else // Unscheduled wakeup
2715 {
2716 // read sleeping planned value in TPU INIT register & compute time elapsed
2717 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT - l1s.pw_mgr.sleep_duration;
2718 return(TRUE);
2719 }
2720 }
2721 #endif
2722 return(FALSE);//omaps00090550
2723 }
2724
2725 /*-------------------------------------------------------*/
2726 /* l1s_recover_Frame() */
2727 /*-------------------------------------------------------*/
2728 /* */
2729 /* Description: adjust layer1 data from sleep duration */
2730 /* ------------ */
2731 /*-------------------------------------------------------*/
2732 void l1s_recover_Frame(void)
2733 {
2734 if (l1_config.pwr_mngt == PWR_MNGT)
2735 {
2736 /***************************************************/
2737 /* Fix Frame counters . */
2738 /***************************************************/
2739 l1s.debug_time += l1s.pw_mgr.sleep_duration; // used for debug and by L3 scenario.
2740
2741 // Time...
2742 // Update "actual time".
2743 l1s_increment_time(&(l1s.actual_time), l1s.pw_mgr.sleep_duration);
2744
2745 // Update "next time".
2746 l1s.next_time = l1s.actual_time;
2747 l1s_increment_time(&(l1s.next_time), 1); // Next time is actual_time + 1
2748
2749 #if L1_GPRS
2750 // Update "next plus time".
2751 l1s.next_plus_time = l1s.next_time;
2752 l1s_increment_time(&(l1s.next_plus_time), 1); // Next_plus time is next_time + 1
2753 #endif
2754
2755 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
2756 trace_fct(CST_L1S_ADJUST_TIME, (UWORD32)(-1));
2757 #endif
2758
2759 // Multiframe table...
2760 // Increment active frame % mftab size.
2761 l1s.afrm = (l1s.afrm + l1s.pw_mgr.sleep_duration) % MFTAB_SIZE;
2762
2763 // Control function counters...
2764 // Increment frame count from last AFC update.
2765 l1s.afc_frame_count+= l1s.pw_mgr.sleep_duration;
2766 // reset counter to mask SNR/TOA results for 2 fr.
2767 #if (TOA_ALGO == 2)
2768 l1s.toa_var.toa_snr_mask=0;
2769 #else
2770 l1s.toa_snr_mask=0;
2771 #endif
2772
2773 /***************************************************/
2774 /* Fix next L1S task counter */
2775 /***************************************************/
2776 // Decrement time to next L1S task.
2777 if((l1a_l1s_com.time_to_next_l1s_task > 0) &&
2778 (l1a_l1s_com.time_to_next_l1s_task < MAX_FN))
2779 l1a_l1s_com.time_to_next_l1s_task -= l1s.pw_mgr.sleep_duration;
2780 } // l1_config.pwr_mngt == PWR_MNGT
2781 }
2782
2783
2784 /*-------------------------------------------------------*/
2785 /* l1s_recover_HWTimers() */
2786 /*-------------------------------------------------------*/
2787 /* */
2788 /* Description: adjust hardware timers from sleep */
2789 /* ------------ duration */
2790 /* */
2791 /* Timers clocks are enabled after VTCX0+SLICER+13MHZ */
2792 /* setup times. So sleep duration is : */
2793 /* GSM TIMER - SETUP_FRAME + SETUP_SLICER + SETUP_VTCXO */
2794 /* + SETUP_CLK13 */
2795 /*-------------------------------------------------------*/
2796
2797 void l1s_recover_HWTimers(void)
2798 {
2799 #if (CODE_VERSION != SIMULATION)
2800
2801 #define SETUP_FRAME_IN_CLK32 (SETUP_FRAME*4.615*32.768)
2802 #if (CHIPSET == 15)
2803 #define DELTA_TIME (0)
2804 #else
2805 #define DELTA_TIME (SETUP_FRAME_IN_CLK32 -SETUP_SLICER - SETUP_VTCXO)
2806 #endif
2807
2808
2809 if (l1_config.pwr_mngt == PWR_MNGT)
2810 {
2811 WORD32 timer1,timer2,timer;
2812 #if (CHIPSET == 12) || (CHIPSET == 15)
2813 WORD32 timer_sec;
2814 #endif
2815 UWORD16 cntlreg;
2816 UWORD16 modereg;
2817 double duration;
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830 //WORD32 old;- OMAPS 90550 new
2831
2832 // read Hercules Timers & Watchdog
2833 //=================================================
2834 // Tint = Tclk * (LOAD_TIM+1) * 2^(PTV+1)
2835 // Tclk = 1.2308us for Fclk=13Mhz
2836 // PTV = 7 (pre-scaler field)
2837 //-------------------------------------------------
2838
2839 cntlreg = Dtimer1_Get_cntlreg();
2840 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
2841 {
2842 cntlreg = cntlreg&0x1F;
2843 cntlreg >>= 2; // take PTV
2844 cntlreg = 1 << (cntlreg+1); // compute 2^(PTV+1)
2845 // convert sleep duration in HWTimers ticks....
2846 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308);
2847 if (duration < 0.0){
2848 duration = 0.0; // This needs to be done for all the timers
2849 }
2850 timer1 = Dtimer1_ReadValue() - (UWORD16) duration;
2851
2852 Dtimer1_Start(0);
2853 Dtimer1_WriteValue(timer1);
2854 Dtimer1_Start(1);
2855 }
2856
2857 cntlreg = Dtimer2_Get_cntlreg();
2858 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
2859 {
2860 cntlreg = cntlreg&0x1F;
2861 cntlreg >>= 2; // take PTV
2862 cntlreg = 1 << (cntlreg+1);
2863 // convert sleep duration in HWTimers ticks....
2864 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308);
2865 if (duration < 0.0){
2866 duration = 0.0; // This needs to be done for all the timers
2867 }
2868 timer2 = Dtimer2_ReadValue() - (UWORD16) duration;
2869 Dtimer2_Start(0);
2870 Dtimer2_WriteValue(timer2);
2871 Dtimer2_Start(1);
2872 }
2873
2874 cntlreg = TIMER_Read(0);
2875 modereg = TIMER_Read(2);
2876 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
2877 {
2878 // in watchdog mode PTV is forced to 7
2879 if ( modereg & TIMER_WDOG )
2880 cntlreg |= TIMER_PTV;
2881
2882 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
2883 cntlreg = 1 << (cntlreg+1);
2884 // convert sleep duration in HWTimers ticks....
2885 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.001078);
2886
2887 timer = TIMER_ReadValue() - (UWORD16) duration;
2888 TIMER_START_STOP(0);
2889 TIMER_WriteValue(timer);
2890 TIMER_START_STOP(1);
2891 }
2892
2893 #if (CHIPSET == 12) || (CHIPSET == 15)
2894 cntlreg = TIMER_SEC_Read(0);
2895 modereg = TIMER_SEC_Read(2);
2896 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
2897 {
2898 // in watchdog mode PTV is forced to 7
2899 if ( modereg & TIMER_WDOG )
2900 cntlreg |= TIMER_PTV;
2901
2902 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
2903 cntlreg = 1 << (cntlreg+1);
2904 // convert sleep duration in HWTimers ticks....
2905 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.001078);
2906
2907 timer_sec = TIMER_SEC_ReadValue() - (UWORD16) duration;
2908 TIMER_SEC_START_STOP(0);
2909 TIMER_SEC_WriteValue(timer_sec);
2910 TIMER_SEC_START_STOP(1);
2911 }
2912 #endif
2913
2914 }
2915 #endif
2916 }
2917 /*-------------------------------------------------------*/
2918 /* l1s_get_next_gauging_in_Packet_Idle() */
2919 /*-------------------------------------------------------*/
2920 /* */
2921 /* Description: */
2922 /* ------------ */
2923 /* return the nbr of frames before the next gauging */
2924 /* return -1 means no activity planned */
2925 /*-------------------------------------------------------*/
2926 #if L1_GPRS
2927 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void)
2928 {
2929 WORD32 next_gauging;
2930
2931 // gauging performed with Normal Paging (we are in Idle mode)
2932 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
2933 return ((UWORD32)(-1)); // no activity planned //omaps00090550
2934
2935 // we are not in Packet Idle Mode
2936 if (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED)
2937 return ((UWORD32)(-1)); // no activity planned //omaps00090550
2938
2939 next_gauging = l1s.next_gauging_scheduled_for_PNP - l1s.actual_time.fn ;
2940 if (next_gauging < 0)
2941 next_gauging+=MAX_FN;
2942
2943 if (next_gauging <= MIN_SLEEP_TIME)
2944 return(0);
2945
2946 return (next_gauging);
2947 }
2948 #endif
2949 /*-------------------------------------------------------*/
2950 /* l1s_gauging_decision_with_PNP() */
2951 /*-------------------------------------------------------*/
2952 /* */
2953 /* Description: */
2954 /* ------------ */
2955 /* */
2956 /*-------------------------------------------------------*/
2957 #if L1_GPRS
2958 BOOL l1s_gauging_decision_with_PNP(void)
2959 {
2960 #define TWO_SECONDS_IN_FRAME (UWORD16)(2000/4.615)
2961 WORD32 time_to_next_gauging=0; //changed to WORD32- sajal
2962 // It's time to perform the next gauging
2963 time_to_next_gauging = l1s.next_gauging_scheduled_for_PNP - l1s.actual_time.fn;
2964 if (time_to_next_gauging < 0)
2965 {
2966 time_to_next_gauging += MAX_FN;
2967 }
2968
2969 if( (time_to_next_gauging == 0) || (time_to_next_gauging > TWO_SECONDS_IN_FRAME))
2970 {
2971
2972 l1s.next_gauging_scheduled_for_PNP = l1s.actual_time.fn + TWO_SECONDS_IN_FRAME;
2973 if (l1s.next_gauging_scheduled_for_PNP >= MAX_FN) l1s.next_gauging_scheduled_for_PNP -= MAX_FN;
2974 return (TRUE);
2975 }
2976
2977 return (FALSE); // do not perform gauging
2978 }
2979 #endif
2980 /*-------------------------------------------------------*/
2981 /* l1s_gauging_decision_with_NP() */
2982 /*-------------------------------------------------------*/
2983 /* */
2984 /* Description: */
2985 /* ------------ */
2986 /* */
2987 /*-------------------------------------------------------*/
2988 BOOL l1s_gauging_decision_with_NP(void)
2989 {
2990
2991 static UWORD8 time_to_gaug;
2992
2993 // a paging is scheduled or , was scheduled but discarded by a higher priority task
2994 if (l1s.pw_mgr.paging_scheduled == TRUE)
2995 {
2996 l1s.pw_mgr.paging_scheduled = FALSE; // reset Flag.
2997
2998 // A gauging session is needed : start gauging session with this paging bloc !
2999
3000 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
3001 #if 0
3002 if (l1s.pw_mgr.enough_gaug != TRUE)
3003 time_to_gaug = 0;
3004 #else
3005 if ((l1s.pw_mgr.enough_gaug != TRUE)||(l1s.force_gauging_next_paging_due_to_CCHR == 1))
3006 {
3007 time_to_gaug = 0;
3008 l1s.force_gauging_next_paging_due_to_CCHR = 0;
3009 }
3010 #endif
3011 if (time_to_gaug > 0)
3012 {
3013 time_to_gaug--; // perform the gauging with an another paging.
3014 }
3015 else // perform the gauging with this paging
3016 {
3017 if (l1s.task_status[NP].current_status == ACTIVE )
3018 {
3019 time_to_gaug = GAUG_VS_PAGING_RATE[l1a_l1s_com.bs_pa_mfrms-2]-1;
3020
3021 return (TRUE); // gauging allowed
3022 }
3023 else // a gauging is scheduled to be perform here but the paging is missing
3024 { // (paging discarded by a higher priority task ?)
3025 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep until next gauging
3026 }
3027 }
3028 }
3029 return (FALSE); // gauging not allowed
3030 }
3031
3032 /*************************************************************/
3033 /* Gauging task management : */
3034 /* */
3035 /* CALYPSO */
3036 /* */
3037 /* 9 8 7 6 5 4 3 2 1 0 */
3038 /* C0 C1 C2 C3 C4 W R - - - */
3039 /* | | */
3040 /* | | */
3041 /* |_ start gauging |_ stop gauging */
3042 /* */
3043 /*OTHERS: */
3044 /* */
3045 /* 11 10 9 8 7 6 5 4 3 2 1 0 */
3046 /* C0 C1 C2 C3 C4 W R - - - - - */
3047 /* | | | | | */
3048 /* | | |_ start gauging |_ stop gauging */
3049 /* | | | | */
3050 /* | |_ (ITCOM) | |(ITCOM) */
3051 /* | | */
3052 /* |_ pgm PLL |_restore PLL */
3053 /* */
3054 /* */
3055 /*************************************************************/
3056 void l1s_gauging_task(void)
3057 {
3058 if (l1_config.pwr_mngt == PWR_MNGT)
3059 {
3060 /*************************************************************/
3061 if (l1s.pw_mgr.gauging_task == ACTIVE)
3062 {
3063 /*************************************************************/
3064 // COUNT = 10 ==> PLL is at 65 Mhz, start the gauging
3065 /*************************************************************/
3066 #if (CHIPSET==7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
3067 // the gauging was started with the begining of the paging
3068 #else
3069 if (l1s.pw_mgr.gaug_count == (l1s.pw_mgr.gaug_duration-1))
3070 {
3071 #if (CODE_VERSION != SIMULATION)
3072 ULDP_GAUGING_START; // start gauging
3073 #endif
3074
3075 #if (TRACE_TYPE != 0)
3076 #if (GSM_IDLE_RAM != 0)
3077 l1_trace_gauging_intram();
3078 #else
3079 l1_trace_gauging();
3080 #endif
3081 #endif
3082 }
3083 #endif
3084
3085 l1s.pw_mgr.gaug_count--; // decrement counter
3086
3087
3088 // When a MISC task is enabled L1S must be ran every frame
3089 // to be able to enable the frame interrupt for DSP
3090 l1a_l1s_com.time_to_next_l1s_task = 0;
3091 }
3092
3093 /*************************************************************/
3094 // REQUEST A GAUGING PROCESS ON EACH PAGING BLOCK
3095 // IN IDLE MODE .....
3096 /*************************************************************/
3097
3098 else if (l1s.pw_mgr.gauging_task == INACTIVE )
3099 {
3100 BOOL decision = FALSE;
3101
3102 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
3103 decision = l1s_gauging_decision_with_NP();
3104 #if L1_GPRS
3105 else
3106 if (l1a_l1s_com.l1s_en_task[PNP] == TASK_ENABLED)
3107 decision = l1s_gauging_decision_with_PNP();
3108 #endif
3109
3110 if (decision == TRUE)
3111 {
3112 // gauging duration
3113 l1s.pw_mgr.gaug_count = l1s.pw_mgr.gaug_duration;
3114
3115 #if (CHIPSET==7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
3116 // start ULPD gauging immediately with Calypso because we needn't IT_COM.
3117 #if (CODE_VERSION != SIMULATION)
3118 ULDP_GAUGING_START;
3119 #if (CHIPSET == 12) || (CHIPSET == 15)
3120 // Force the DPLL to be active
3121 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS);
3122 #endif
3123 #endif
3124
3125 #if (TRACE_TYPE != 0)
3126 #if (GSM_IDLE_RAM != 0)
3127 l1_trace_gauging_intram();
3128 #else
3129 l1_trace_gauging();
3130 #endif
3131 #endif
3132 #endif
3133
3134 // DSP programmation .......
3135 #if (DSP >= 33)
3136 #if (CHIPSET==4)
3137 l1s_dsp_com.dsp_ndb_ptr->d_pll_config |= B_32KHZ_CALIB;
3138 #endif
3139 #else
3140 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD2; // IDLE1 only for DSP
3141 #endif
3142
3143 l1s.pw_mgr.gauging_task = ACTIVE;
3144 }
3145 }
3146 }
3147 }
3148 /*-------------------------------------------------------*/
3149 /* l1s_gauging_task_end() */
3150 /*-------------------------------------------------------*/
3151 /* */
3152 /* Description: */
3153 /* ------------ */
3154 /* stop the gauging activity */
3155 /*-------------------------------------------------------*/
3156 void l1s_gauging_task_end(void)
3157 {
3158 if (l1_config.pwr_mngt == PWR_MNGT)
3159 {
3160 /*************************************************************/
3161 if (l1s.pw_mgr.gauging_task == ACTIVE)
3162 {
3163 /*************************************************************/
3164 // COUNT = 1 ==> stop the gauging and free DSP idle modes....
3165 /*************************************************************/
3166 if (l1s.pw_mgr.gaug_count == 1)
3167 {
3168 // wait for end of gauging interrupt ...
3169 l1s.pw_mgr.gauging_task = WAIT_IQ;
3170
3171 // Unmask ULPD GAUGING int.
3172 #if (CODE_VERSION != SIMULATION)
3173 #if (CHIPSET == 12) || (CHIPSET == 15)
3174 F_INTH_ENABLE_ONE_IT(C_INTH_ULPD_GAUGING_IT);
3175 #else
3176 INTH_ENABLEONEIT(IQ_ULPD_GAUGING);
3177 #endif
3178 ULDP_GAUGING_STOP; // stop ULPD gauging
3179 #if (CHIPSET == 12) || (CHIPSET == 15)
3180 // Allow the DPLL to be cut according to ARM sleep mode
3181 //( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= (CLKM_DPLL_DIS);
3182 #endif
3183 #endif
3184
3185 // DSP programmation : free IDLE modes...
3186 #if (DSP >= 33)
3187 #if (CHIPSET==4)
3188 l1s_dsp_com.dsp_ndb_ptr->d_pll_config &= ~B_32KHZ_CALIB;
3189 #endif
3190 #else
3191 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1;
3192 #endif
3193
3194
3195 #if (CODE_VERSION == SIMULATION)
3196 // in order to simulate the Gauging interrupt
3197 GAUGING_Handler();
3198
3199 #if (TRACE_TYPE==5)
3200 trace_ULPD("Stop Gauging", l1s.actual_time.fn);
3201 #endif
3202 #endif
3203 }
3204 }
3205 }
3206 }
3207
3208 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
3209 #endif
3210
3211
3212