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comparison L1/cust0/mv100/l1_rf10.h @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename l1_rf10.h
5 * Version 1.18
6 * Date 01/21/03
7 *
8 ************* Revision Controle System Header *************/
9
10 // is this defined somewhere else?
11 //#define RF_HW_BAND_EGSM
12 //#define RF_HW_BAND_DCS
13 #define RF_HW_BAND_PCS 0x4
14 #define RF_HW_BAND_DUAL_US 0x80
15 #define RF_HW_BAND_DUAL_EXT 0x20
16
17 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS
18 /************************************/
19 /* SYNTHESIZER setup time... */
20 /************************************/
21 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit.
22 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
23
24 /************************************/
25 /* time for TPU scenario ending... */
26 /************************************/
27 #define RX_TPU_SCENARIO_ENDING 0 // execution time of BDLENA down
28 // contained in serialization time
29 #define TX_TPU_SCENARIO_ENDING DLT_1B - SL_SU_DELAY2 + 1 // execution time of BULON down
30 // minus serialization time + 1 TPU_MOVE
31
32 /******************************************************/
33 /* TXPWR configuration... */
34 /* Fixed TXPWR value when GSM management is disabled. */
35 /******************************************************/
36 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
37 // #define FIXED_TXPWR 0x3f12 // TXPWR=10, value=252
38 //#define FIXED_TXPWR 0x1952
39 #define FIXED_TXPWR 0x1d12 // TXPWR=15
40 #endif
41
42
43 /************************************/
44 /* ANALOG delay (in qbits) */
45 /************************************/
46 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
47 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
48 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
49 #if (ANALOG == 1)
50 #define UL_ABB_DELAY 6 // modulator input to output delay
51 #endif
52 #if ((ANALOG == 2) || (ANALOG == 3))
53 #define UL_ABB_DELAY 3 // modulator input to output delay
54 #endif
55
56 /************************************/
57 /* TX Propagation delay... */
58 /************************************/
59 #if (ANALOG == 1)
60 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
61 #endif
62 #if (ANALOG == 2) || (ANALOG == 3)
63 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY + 2) // = 42
64 #endif
65
66 /************************************/
67 /* Initial value for APC DELAY */
68 /************************************/
69 #if (ANALOG == 1)
70 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
71 #define APCDEL_DOWN 2 // minimum value: 2
72 #define APCDEL_UP (6+5) // minimum value: 6
73 #endif
74 #if (ANALOG == 2) || (ANALOG == 3)
75 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
76 #define APCDEL_DOWN (2+0) // minimum value: 2
77 #define APCDEL_UP (6+8) // minimum value: 6
78 #endif
79
80 #define GUARD_BITS 8
81
82 /************************************/
83 /* Initial value for AFC... */
84 /************************************/
85 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
86
87 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames
88 // Clara (RF=10) LDO wakeup requires 3 frames
89
90 /************************************/
91 /* Baseband registers */
92 /************************************/
93 #if (ANALOG == 1)
94 // Omega registers values will be programmed at 1st DSP communication interrupt
95 #define C_DEBUG1 0x0000 // Enable f_tx delay of 400000 cyc DEBUG
96 #define C_AFCCTLADD 0x002a | TRUE // Value at reset
97 #define C_VBUR 0x418e | TRUE // Uplink gain amp 0dB, Sidetone gain to mute
98 #define C_VBDR 0x098c | TRUE // Downlink gain amp 0dB, Volume control 0 dB
99 #define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // value at reset-Changed from 0x0016- CR 27.12
100 #define C_BULIOFF 0x3fc4 | TRUE // value at reset
101 #define C_BULQOFF 0x3fc6 | TRUE // value at reset
102 #define C_DAI_ON_OFF 0x0000 // value at reset
103 #define C_AUXDAC 0x0018 | TRUE // value at reset
104 #define C_VBCR 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1
105 // BULRUDEL will be initialized on rach only ....
106 #define C_APCDEL (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)
107 #define C_BBCTL 0x604c | TRUE // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
108 #endif
109 #if (ANALOG ==2)
110 // IOTA registers values will be programmed at 1st DSP communication interrupt
111 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
112 #define C_AFCCTLADD 0x002a | TRUE // Value at reset
113 #define C_VBUR 0x418e | TRUE // No uplink mute, Side tone mute, PGA_UL 0dB
114 #define C_VBDR 0x098c | TRUE // PGA_DL 0dB, Volume 0dB
115 #define C_APCOFF 0x1016 | (0x28 << 6) | TRUE // value at reset-Changed from 3c to 28 CR 17.11.02// x2 slope 128
116 #define C_BULIOFF 0x3fc4 | TRUE // value at reset
117 #define C_BULQOFF 0x3fc6 | TRUE // value at reset
118 #define C_DAI_ON_OFF 0x0000 // value at reset
119 #define C_AUXDAC 0x0018 | TRUE // value at reset
120 #define C_VBCR 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1
121 #define C_VBCR2 0x0016 | TRUE // MICBIASEL=0, VDLHSO=0, MICAUX=0
122 // BULRUDEL will be initialized on rach only ....
123 #define C_APCDEL (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)
124 #define C_APCDEL2 0x0034
125 #define C_BBCTL 0xb04c | TRUE // External RX I/Q DC offset calibration, Output common mode=1.35V
126 // Monoslot, Vpp=8/15*Vref
127 #define C_BULGCAL 0x001c | TRUE // IAG=0 dB, QAG=0 dB
128 #endif
129
130 #if (ANALOG == 3)
131 // SYREN registers values will be programmed at 1st DSP communication interrupt
132 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
133 #define C_AFCCTLADD 0x002a | TRUE // Value at reset
134 #define C_VBUR 0x1E6<<6 | VBUCTRL | TRUE // Side tone mute, PGA_UL 0dB
135 #define C_VBDR 0x026<<6 | VBDCTRL | TRUE // PGA_DL 0dB, Volume 0dB
136 #define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // x2 slope 128, APCSWP = 0
137 #define C_BULIOFF 0x3fc4 | TRUE // value at reset
138 #define C_BULQOFF 0x3fc6 | TRUE // value at reset
139 #define C_DAI_ON_OFF 0x0000 // value at reset
140 #define C_AUXDAC (0x00<<6) | 0x18 | TRUE // value at reset
141 #define C_VBCR (0x108<<6) | 0x10 | TRUE // VULSWITCH=1 AUXI 28,2 dB
142 #define C_VBCR2 (0x01<<6) | 0x16 | TRUE // HSMIC on, SPKG gain @ 2,5dB
143 // BULRUDEL will be initialized on rach only ....
144 #define C_APCDEL (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)
145 #define C_APCDEL2 0x0034
146 #define C_BBCTL 0xB04c | TRUE // External autocalibration, Output common mode=1.35V
147 // Monoslot, Vpp=8/15*Vref
148 #define C_BULGCAL 0x001c | TRUE // IAG=0 dB, QAG=0 dB
149
150 #define C_VBPOP (0x4)<<6 | 0x14 | TRUE // HSOAUTO enabled only
151 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
152 #define C_VAUDCR (0x0)<<6 | 0x1e | TRUE // Init to zero
153 #define C_VAUOCR (0x155)<<6 | VAUOCTRL | TRUE // Sppech on all outputs
154 #define C_VAUSCR (0x0)<<6 | 0x20 | TRUE // Init to zero
155 #define C_VAUDPLL (0x0)<<6 | 0x24 | TRUE // Init to zero
156
157 #endif
158
159
160 /************************************/
161 /* Automatic frequency compensation */
162 /************************************/
163 /********************* C_Psi_sta definition *****************************/
164 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
165 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
166 /* regarding Vega V/N = 2.4/4096 */
167 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
168 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
169 /* = 0.000195748 */
170 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
171 /************************************************************************/
172 #define C_Psi_sta_inv 4174L // (1/C_Psi_sta)
173 #define C_Psi_st 13L // C_Psi_sta * 0.8 F0.16
174 #define C_Psi_st_32 823216L // F0.32
175 #define C_Psi_st_inv 5217L // (1/C_Psi_st)
176
177 #if (VCXO_ALGO == 1)
178 // Linearity parameters
179 #define C_AFC_DAC_CENTER ((111)*8)
180 #define C_AFC_DAC_MIN ((-1196)*8)
181 #define C_AFC_DAC_MAX ((1419)*8)
182
183 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10
184 #endif
185
186 typedef struct
187 {
188 WORD16 eeprom_afc;
189 UWORD32 psi_sta_inv;
190 UWORD32 psi_st;
191 UWORD32 psi_st_32;
192 UWORD32 psi_st_inv;
193
194 #if (VCXO_ALGO == 1)
195 // VCXO adjustment parameters
196 // Parameters used when assuming linearity
197 WORD16 dac_center;
198 WORD16 dac_min;
199 WORD16 dac_max;
200 WORD16 snr_thr;
201 #endif
202 }
203 T_AFC_PARAMS;
204
205 /************************************/
206 /* Swap IQ definitions... */
207 /************************************/
208 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
209 #define SWAP_IQ_GSM 0
210 #define SWAP_IQ_DCS 2 // was 2 for sara version 1
211 #define SWAP_IQ_PCS 2
212 #define SWAP_IQ_GSM850 0 //TBD
213
214 /************************************/
215 /************************************/
216 // typedef
217 /************************************/
218 /************************************/
219
220 /*************************************************************/
221 /* Define structure for apc of TX Power ******/
222 /*************************************************************/
223 typedef struct
224 { // pcm-file "rf/tx/level.gsm|dcs"
225 UWORD16 apc; // 0..31
226 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
227 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
228 }
229 T_TX_LEVEL;
230
231 /************************************/
232 /* Automatic Gain Control */
233 /************************************/
234 /* Define structure for sub-band definition of TX Power ******/
235 typedef struct
236 {
237 UWORD16 upper_bound; //highest physical arfcn of the sub-band
238 WORD16 agc_calib; // AGC for each TXPWR
239 }T_RF_AGC_BAND;
240
241 /************************************/
242 /* Ramp definitions */
243 /************************************/
244 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
245 typedef struct
246 {
247 UWORD8 ramp_up [16]; // Ramp-up profile
248 UWORD8 ramp_down [16]; // Ramp-down profile
249 }
250 T_TX_RAMP;
251 #endif
252
253
254 // RF structure definition
255 //========================
256
257 enum RfRevision {
258 RF_IGNORE = 0x0000,
259 RF_SL2 = 0x1000,
260 RF_GAIA_20X = 0x2000,
261 RF_GAIA_20A = 0x2001,
262 RF_GAIA_20B = 0x2002,
263 RF_ATLAS_20B = 0x2020,
264 RF_PASCAL_20 = 0x2030
265 };
266
267 // Number of bands supported
268 #define GSM_BANDS 2
269
270 #define MULTI_BAND1 0
271 #define MULTI_BAND2 1
272 // RF table sizes
273 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
274 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
275
276 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
277 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
278 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
279 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
280 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
281
282 #define AGC_TABLE_SIZE 27
283
284 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
285
286
287 // RX parameters and tables
288 //-------------------------
289
290 // AGC parameters and tables
291 typedef struct
292 {
293 UWORD16 low_agc_noise_thr;
294 UWORD16 high_agc_sat_thr;
295 UWORD16 low_agc;
296 UWORD16 high_agc;
297 UWORD8 il2agc_pwr[121];
298 UWORD8 il2agc_max[121];
299 UWORD8 il2agc_av[121];
300 }
301 T_AGC;
302
303 // Calibration parameters
304 typedef struct
305 {
306 UWORD16 g_magic;
307 UWORD16 lna_att;
308 UWORD16 lna_switch_thr_low;
309 UWORD16 lna_switch_thr_high;
310 }
311 T_RX_CAL_PARAMS;
312
313 // RX temperature compensation
314 typedef struct
315 {
316 WORD16 temperature;
317 WORD16 agc_calib;
318 }
319 T_RX_TEMP_COMP;
320
321 // RF RX structure
322 typedef struct
323 {
324 T_AGC agc;
325 }
326 T_RF_RX; //common
327
328 // RF RX structure
329 typedef struct
330 {
331 T_RX_CAL_PARAMS rx_cal_params;
332 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
333 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
334 }
335 T_RF_RX_BAND;
336
337
338 // TX parameters and tables
339 //-------------------------
340
341 // TX temperature compensation
342 typedef struct
343 {
344 WORD16 temperature;
345 #if (ORDER2_TX_TEMP_CAL==1)
346 WORD16 a;
347 WORD16 b;
348 WORD16 c;
349 #else
350 WORD16 apc_calib; //WORD16 c
351 #endif
352 }
353 T_TX_TEMP_CAL;
354
355
356 // Ramp up and ramp down delay
357 typedef struct
358 {
359 UWORD16 up;
360 UWORD16 down;
361 }
362 T_RAMP_DELAY;
363
364 typedef struct
365 {
366 UWORD16 arfcn_limit;
367 WORD16 chan_cal;
368 }
369 T_TX_CHAN_CAL;
370
371 // RF TX structure
372 typedef struct
373 {
374 T_RAMP_DELAY ramp_delay;
375 UWORD8 guard_bits; // number of guard bits needed for ramp up
376 UWORD8 prg_tx;
377 }
378 T_RF_TX; //common
379
380 // RF TX structure
381 typedef struct
382 {
383 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
384 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
385 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
386 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
387 }
388 T_RF_TX_BAND;
389
390 // band structure
391 typedef struct
392 {
393 T_RF_RX_BAND rx;
394 T_RF_TX_BAND tx;
395 UWORD8 swap_iq;
396 }
397 T_RF_BAND;
398
399 // RF structure
400 typedef struct
401 {
402 // common for all bands
403 UWORD16 rf_revision;
404 UWORD16 radio_band_support;
405 T_RF_RX rx;
406 T_RF_TX tx;
407 T_AFC_PARAMS afc;
408 }
409 T_RF;
410
411 /************************************/
412 /* MADC definitions */
413 /************************************/
414 // Omega: 5 external channels if touch screen not used, 3 otherwise
415 enum ADC_INDEX {
416 ADC_VBAT,
417 ADC_VCHARG,
418 ADC_ICHARG,
419 ADC_VBACKUP,
420 ADC_BATTYP,
421 ADC_BATTEMP,
422 ADC_ADC3, // name of this ??
423 ADC_RFTEMP,
424 ADC_ADC4,
425 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
426 };
427
428 typedef struct
429 {
430 WORD16 converted[ADC_INDEX_END]; // converted
431 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
432 }
433 T_ADC;
434
435 /************************************/
436 /* MADC calibration */
437 /************************************/
438 typedef struct
439 {
440 UWORD16 a[ADC_INDEX_END];
441 WORD16 b[ADC_INDEX_END];
442 }
443 T_ADCCAL;
444
445 // Conversion table: ADC value -> temperature
446 typedef struct
447 {
448 UWORD16 adc; // ADC reading is 10 bits
449 WORD16 temp; // temp is in approx. range -30..+80
450 }
451 T_TEMP;
452
453 typedef struct
454 {
455 char *name;
456 void *addr;
457 int size;
458 }
459 T_CONFIG_FILE;
460
461 typedef struct
462 {
463 char *name; // name of ffs file suffix
464 T_RF_BAND *addr; // address to default flash structure
465 UWORD16 max_carrier; // max carrier
466 UWORD16 max_txpwr; // max tx power
467 }
468 T_BAND_CONFIG;
469
470 typedef struct
471 {
472 UWORD8 band[GSM_BANDS]; // index to band address
473 UWORD8 txpwr_tp; // tx power turning point
474 UWORD16 first_arfcn; // first index
475 }
476 T_STD_CONFIG;
477
478 enum GSMBAND_DEF
479 {
480 BAND_NONE,
481 BAND_EGSM900,
482 BAND_DCS1800,
483 BAND_PCS1900,
484 BAND_GSM850,
485 BAND_PCS1900_US,
486 // put new bands here
487 BAND_GSM900 //last entry
488 };
489
490 /************************************/
491 /* ABB (Omega) Initialization */
492 /************************************/
493
494 #if ((ANALOG == 1) || (ANALOG == 2))
495 #define ABB_TABLE_SIZE 16
496 #elif (ANALOG == 3)
497 #define ABB_TABLE_SIZE 22
498 #endif
499
500 // Note that this translation is probably not needed at all. But until L1 is
501 // (maybe) changed to simply initialize the ABB from a table of words, we
502 // use this to make things more easy-readable.
503 #if (ANALOG == 1)
504 enum ABB_REGISTERS {
505 ABB_AFCCTLADD = 0,
506 ABB_VBUR,
507 ABB_VBDR,
508 ABB_BBCTL,
509 ABB_APCOFF,
510 ABB_BULIOFF,
511 ABB_BULQOFF,
512 ABB_DAI_ON_OFF,
513 ABB_AUXDAC,
514 ABB_VBCR,
515 ABB_APCDEL
516 };
517 #elif (ANALOG == 2)
518 enum ABB_REGISTERS {
519 ABB_AFCCTLADD = 0,
520 ABB_VBUR,
521 ABB_VBDR,
522 ABB_BBCTL,
523 ABB_BULGCAL,
524 ABB_APCOFF,
525 ABB_BULIOFF,
526 ABB_BULQOFF,
527 ABB_DAI_ON_OFF,
528 ABB_AUXDAC,
529 ABB_VBCR,
530 ABB_VBCR2,
531 ABB_APCDEL,
532 ABB_APCDEL2
533 };
534 #elif (ANALOG == 3)
535 enum ABB_REGISTERS {
536 ABB_AFCCTLADD = 0,
537 ABB_VBUR,
538 ABB_VBDR,
539 ABB_BBCTL,
540 ABB_BULGCAL,
541 ABB_APCOFF,
542 ABB_BULIOFF,
543 ABB_BULQOFF,
544 ABB_DAI_ON_OFF,
545 ABB_AUXDAC,
546 ABB_VBCR,
547 ABB_VBCR2,
548 ABB_APCDEL,
549 ABB_APCDEL2,
550 ABB_VBPOP,
551 ABB_VAUDINITD,
552 ABB_VAUDCR,
553 ABB_VAUOCR,
554 ABB_VAUSCR,
555 ABB_VAUDPLL
556 };
557 #endif
558