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comparison L1/cust0/mv100/l1_rf12.h @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename l1_rf12.h
5 * Version 1.9
6 * Date 03/21/03
7 *
8 ************* Revision Controle System Header *************/
9
10 #if (OP_L1_STANDALONE == 1)
11 // Define the correct enumeration of PA. Consult tpudrv12.h for the enumeration.
12 #if ((BOARD == 40) || (BOARD == 41) || (BOARD == 45)) // EvaRita + D-sample or EvaConso
13 #define PA 3
14 #else
15 #define PA 0
16 #endif
17 #else
18 #include "rf.cfg"
19 //#define PA 3
20 #endif
21
22 #ifndef PA
23 #error PA not defined.
24 #endif
25
26 #define RF_RITA_10 0x2030 // Check with TIDK
27
28 //#define RF_HW_BAND_EGSM
29 //#define RF_HW_BAND_DCS
30 #define RF_HW_BAND_PCS 0x4
31 #define RF_HW_BAND_DUAL_US 0x80
32 #define RF_HW_BAND_DUAL_EXT 0x20
33
34 //#define RF_HW_BAND_SUPPORT (0x0020 | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS
35 // radio_band_support E-GSM/DCS + GSM850/PCS
36 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_DUAL_US)
37
38 /************************************/
39 /* SYNTHESIZER setup time... */
40 /************************************/
41 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit.
42 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
43
44 /************************************/
45 /* time for TPU scenario ending... */
46 /************************************/
47 //
48 // The following values are used to take into account any TPU activity AFTER
49 // BDLON (or BDLENA) down (for RX) and BULON down (for TX)
50 // - If there are no TPU commands after BDLON (or BDLENA) down and BULON down,
51 // these defines must be ZERO
52 // - If there IS some TPU command after BDLON (or BDLENA) and BULON down,
53 // these defines must be equal to the time difference (in qbits) between
54 // the BDLON (or BDLENA) or BULON time and the last TPU command on
55 // the TPU scenario
56 #define RX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BDLENA down
57 #define TX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BULON down
58
59
60 /******************************************************/
61 /* TXPWR configuration... */
62 /* Fixed TXPWR value when GSM management is disabled. */
63 /******************************************************/
64 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
65 // #define FIXED_TXPWR 0x3f12 // TXPWR=10, value=252
66 //#define FIXED_TXPWR 0x1952
67 #define FIXED_TXPWR 0x1d12 // TXPWR=15
68 #endif
69
70
71 /************************************/
72 /* ANALOG delay (in qbits) */
73 /************************************/
74 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
75 #if (PA == 3) // Hitachi
76 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
77 #else
78 #define UL_DELAY_1RF 7 // time spent in the first uplink RF block
79 #endif
80 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
81 #if (ANALOG == 1)
82 #define UL_ABB_DELAY 6 // modulator input to output delay
83 #endif
84 #if ((ANALOG == 2) || (ANALOG == 3))
85 #define UL_ABB_DELAY 3 // modulator input to output delay
86 #endif
87
88 /************************************/
89 /* TX Propagation delay... */
90 /************************************/
91 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
92 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
93 #endif
94
95 /************************************/
96 /* Initial value for APC DELAY */
97 /************************************/
98 #if (ANALOG == 1)
99 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
100 #define APCDEL_DOWN 2 // minimum value: 2
101 #define APCDEL_UP (6+5) // minimum value: 6
102 #endif
103 #if (ANALOG == 2) || (ANALOG == 3)
104 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
105 #define APCDEL_DOWN (2+0) // minimum value: 2
106 #if (PA == 3) // Hitachi
107 #define APCDEL_UP (6+1) // minimum value: 6
108 #else
109 #define APCDEL_UP (6+3+1) // minimum value: 6
110 #endif
111 // REMOVE // Jerome Modif for ARF7: (6+3) instead of (6+8)
112 #endif
113
114 #define GUARD_BITS 7
115
116 /************************************/
117 /* Initial value for AFC... */
118 /************************************/
119 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
120
121 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames and RF BAND GAP stable after 4 frames
122 // Rita (RF=12) LDO wakeup requires 6 frames
123
124 /************************************/
125 /* Baseband registers */
126 /************************************/
127 #if (ANALOG == 1) // Omega registers values will be programmed at 1st DSP communication interrupt
128 #define C_DEBUG1 0x0000 // Enable f_tx delay of 400000 cyc DEBUG
129 #define C_AFCCTLADD 0x002a | TRUE // Value at reset
130 #define C_VBUR 0x418e | TRUE // Uplink gain amp 0dB, Sidetone gain to mute
131 #define C_VBDR 0x098c | TRUE // Downlink gain amp 0dB, Volume control 0 dB
132 // RITA does not need an APCOFFSET because the PACTRL is internal:
133 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // value at reset-Changed from 0x0016- CR 27.12
134 #if (PA == 3) // Hitachi
135 #define C_APCOFF 0x1016 | (0x0 << 6) | TRUE
136 #else
137 #define C_APCOFF 0x1016 | (0x30 << 6) | TRUE
138 #endif
139 #define C_BULIOFF 0x3fc4 | TRUE // value at reset
140 #define C_BULQOFF 0x3fc6 | TRUE // value at reset
141 #define C_DAI_ON_OFF 0x0000 // value at reset
142 #define C_AUXDAC 0x0018 | TRUE // value at reset
143 #define C_VBCR 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1
144 // BULRUDEL will be initialized on rach only ....
145 #define C_APCDEL (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)
146 #define C_BBCTL 0x604c | TRUE // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
147 #endif
148 #if (ANALOG ==2)
149 // IOTA registers values will be programmed at 1st DSP communication interrupt
150 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
151 #define C_AFCCTLADD 0x002a | TRUE // Value at reset
152 #define C_VBUR 0x418e | TRUE // No uplink mute, Side tone mute, PGA_UL 0dB
153 #define C_VBDR 0x098c | TRUE // PGA_DL 0dB, Volume 0dB
154 // RITA does not need an APCOFFSET because the PACTRL is internal:
155 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // x2 slope 128
156 #if (PA == 3) // Hitachi
157 #define C_APCOFF 0x1016 | (0x0 << 6) | TRUE // x2 slope 128
158 #else
159 #define C_APCOFF 0x1016 | (0x30 << 6) | TRUE // x2 slope 128
160 #endif
161 #define C_BULIOFF 0x3fc4 | TRUE // value at reset
162 #define C_BULQOFF 0x3fc6 | TRUE // value at reset
163 #define C_DAI_ON_OFF 0x0000 // value at reset
164 #define C_AUXDAC 0x0018 | TRUE // value at reset
165 #define C_VBCR 0x02d0 | TRUE // VULSWITCH=1, VDLAUX=1, VDLEAR=1
166 #define C_VBCR2 0x0016 | TRUE // MICBIASEL=0, VDLHSO=0, MICAUX=0
167 // BULRUDEL will be initialized on rach only ....
168 #define C_APCDEL (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)
169 #define C_APCDEL2 0x0034
170 #define C_BBCTL 0xB04c | TRUE // Extenal DL calibration, Output common mode=1.35V
171 // Monoslot, Vpp=8/15*Vref
172 #define C_BULGCAL 0x001c | TRUE // IAG=0 dB, QAG=0 dB
173 #endif
174
175 #if (ANALOG == 3)
176 // SYREN registers values will be programmed at 1st DSP communication interrupt
177 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
178 #define C_AFCCTLADD 0x002a | TRUE // Value at reset
179 #define C_VBUR 0x1E6<<6 | VBUCTRL | TRUE // Side tone mute, PGA_UL 0dB
180 #define C_VBDR 0x026<<6 | VBDCTRL | TRUE // PGA_DL 0dB, Volume 0dB
181 #if (PA == 3) // Hitachi
182 #define C_APCOFF 0x1016 | (0x0 << 6) | TRUE // x2 slope 128
183 #else
184 #define C_APCOFF 0x1016 | (0x30 << 6) | TRUE // x2 slope 128
185 #endif
186 #define C_BULIOFF 0x3fc4 | TRUE // value at reset
187 #define C_BULQOFF 0x3fc6 | TRUE // value at reset
188 #define C_DAI_ON_OFF 0x0000 // value at reset
189 #define C_AUXDAC (0x00<<6) | 0x18 | TRUE // value at reset
190 #define C_VBCR (0x108<<6) | 0x10 | TRUE // VULSWITCH=1 AUXI 28,2 dB
191 #define C_VBCR2 (0x01<<6) | 0x16 | TRUE // HSMIC on, SPKG gain @ 2,5dB
192 // BULRUDEL will be initialized on rach only ....
193 #define C_APCDEL (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004)
194 #define C_APCDEL2 0x0034
195 #define C_BBCTL 0xB04c | TRUE // Internal autocalibration, Output common mode=1.35V
196 // Monoslot, Vpp=8/15*Vref
197 #define C_BULGCAL 0x001c | TRUE // IAG=0 dB, QAG=0 dB
198
199 #define C_VBPOP (0x4)<<6 | 0x14 | TRUE // HSOAUTO enabled only
200 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
201 #define C_VAUDCR (0x0)<<6 | 0x1e | TRUE // Init to zero
202 #define C_VAUOCR (0x155)<<6 | VAUOCTRL | TRUE // Speech on all outputs
203 #define C_VAUSCR (0x0)<<6 | 0x20 | TRUE // Init to zero
204 #define C_VAUDPLL (0x0)<<6 | 0x24 | TRUE // Init to zero
205
206 #endif
207
208
209 /************************************/
210 /* Automatic frequency compensation */
211 /************************************/
212 /********************* C_Psi_sta definition *****************************/
213 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
214 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
215 /* regarding Vega V/N = 2.4/4096 */
216 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
217 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
218 /* = 0.000195748 */
219 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
220 /************************************************************************/
221 #define C_Psi_sta_inv 12902L // (1/C_Psi_sta)
222 #define C_Psi_st 4L // C_Psi_sta * 0.8 F0.16
223 #define C_Psi_st_32 266313L // F0.32
224 #define C_Psi_st_inv 16128L // (1/C_Psi_st)
225
226 #if (VCXO_ALGO == 1)
227 // Linearity parameters
228 #define C_AFC_DAC_CENTER ((-1242)*8)
229 #define C_AFC_DAC_MIN ((-2000)*8)
230 #define C_AFC_DAC_MAX ((1419)*8)
231
232 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10
233 #endif
234
235 typedef struct
236 {
237 WORD16 eeprom_afc;
238 UWORD32 psi_sta_inv;
239 UWORD32 psi_st;
240 UWORD32 psi_st_32;
241 UWORD32 psi_st_inv;
242
243 #if (VCXO_ALGO)
244 // VCXO adjustment parameters
245 // Parameters used when assuming linearity
246 WORD16 dac_center;
247 WORD16 dac_min;
248 WORD16 dac_max;
249 WORD16 snr_thr;
250 #endif
251 }
252 T_AFC_PARAMS;
253
254 /************************************/
255 /* Swap IQ definitions... */
256 /************************************/
257 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
258 #if RF_PG==10
259 // PG 1.0 -> 1 (Swap RX only)
260 // GSM 850 => TX is ALWAYS swapped compared to GSM 900
261 #define SWAP_IQ_GSM 1
262 #define SWAP_IQ_DCS 1
263 #define SWAP_IQ_PCS 1
264 #define SWAP_IQ_GSM850 3 // Swap TX compared to GSM 900
265 #else
266 // All PG versions ABOVE 1.0 -> 0 (No Swap)
267 // GSM 850 => TX is ALWAYS swapped compared to GSM 900
268 #define SWAP_IQ_GSM 0
269 #define SWAP_IQ_DCS 0
270 #define SWAP_IQ_PCS 0
271 #define SWAP_IQ_GSM850 2 // Swap TX compared to GSM 900
272 #endif
273
274 /************************************/
275 /************************************/
276 // typedef
277 /************************************/
278 /************************************/
279
280 /*************************************************************/
281 /* Define structure for apc of TX Power ******/
282 /*************************************************************/
283 typedef struct
284 { // pcm-file "rf/tx/level.gsm|dcs"
285 UWORD16 apc; // 0..31
286 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
287 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
288 }
289 T_TX_LEVEL;
290
291 /************************************/
292 /* Automatic Gain Control */
293 /************************************/
294 /* Define structure for sub-band definition of TX Power ******/
295 typedef struct
296 {
297 UWORD16 upper_bound; //highest physical arfcn of the sub-band
298 WORD16 agc_calib; // AGC for each TXPWR
299 }T_RF_AGC_BAND;
300
301 /************************************/
302 /* Ramp definitions */
303 /************************************/
304 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
305 typedef struct
306 {
307 UWORD8 ramp_up [16]; // Ramp-up profile
308 UWORD8 ramp_down [16]; // Ramp-down profile
309 }
310 T_TX_RAMP;
311 #endif
312
313
314 // RF structure definition
315 //========================
316
317 // Number of bands supported
318 #define GSM_BANDS 2
319
320 #define MULTI_BAND1 0
321 #define MULTI_BAND2 1
322 // RF table sizes
323 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
324 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
325
326 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
327 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
328 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
329 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
330 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
331
332 #define AGC_TABLE_SIZE 20
333 #define MIN_AGC_INDEX 6
334
335 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
336
337
338 // RX parameters and tables
339 //-------------------------
340
341 // AGC parameters and tables
342 typedef struct
343 {
344 UWORD16 low_agc_noise_thr;
345 UWORD16 high_agc_sat_thr;
346 UWORD16 low_agc;
347 UWORD16 high_agc;
348 UWORD8 il2agc_pwr[121];
349 UWORD8 il2agc_max[121];
350 UWORD8 il2agc_av[121];
351 }
352 T_AGC;
353
354 // Calibration parameters
355 typedef struct
356 {
357 UWORD16 g_magic;
358 UWORD16 lna_att;
359 UWORD16 lna_switch_thr_low;
360 UWORD16 lna_switch_thr_high;
361 }
362 T_RX_CAL_PARAMS;
363
364 // RX temperature compensation
365 typedef struct
366 {
367 WORD16 temperature;
368 WORD16 agc_calib;
369 }
370 T_RX_TEMP_COMP;
371
372 // RF RX structure
373 typedef struct
374 {
375 T_AGC agc;
376 }
377 T_RF_RX; //common
378
379 // RF RX structure
380 typedef struct
381 {
382 T_RX_CAL_PARAMS rx_cal_params;
383 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
384 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
385 }
386 T_RF_RX_BAND;
387
388
389 // TX parameters and tables
390 //-------------------------
391
392 // TX temperature compensation
393 typedef struct
394 {
395 WORD16 temperature;
396 #if (ORDER2_TX_TEMP_CAL==1)
397 WORD16 a;
398 WORD16 b;
399 WORD16 c;
400 #else
401 WORD16 apc_calib;
402 #endif
403 }
404 T_TX_TEMP_CAL;
405
406 // Ramp up and ramp down delay
407 typedef struct
408 {
409 UWORD16 up;
410 UWORD16 down;
411 }
412 T_RAMP_DELAY;
413
414 typedef struct
415 {
416 UWORD16 arfcn_limit;
417 WORD16 chan_cal;
418 }
419 T_TX_CHAN_CAL;
420
421 // RF TX structure
422 typedef struct
423 {
424 T_RAMP_DELAY ramp_delay;
425 UWORD8 guard_bits; // number of guard bits needed for ramp up
426 UWORD8 prg_tx;
427 }
428 T_RF_TX; //common
429
430 // RF TX structure
431 typedef struct
432 {
433 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
434 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
435 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
436 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
437 }
438 T_RF_TX_BAND;
439
440 // band structure
441 typedef struct
442 {
443 T_RF_RX_BAND rx;
444 T_RF_TX_BAND tx;
445 UWORD8 swap_iq;
446 }
447 T_RF_BAND;
448
449 // RF structure
450 typedef struct
451 {
452 // common for all bands
453 UWORD16 rf_revision;
454 UWORD16 radio_band_support;
455 T_RF_RX rx;
456 T_RF_TX tx;
457 T_AFC_PARAMS afc;
458 }
459 T_RF;
460
461 /************************************/
462 /* MADC definitions */
463 /************************************/
464 // Omega: 5 external channels if touch screen not used, 3 otherwise
465 enum ADC_INDEX {
466 ADC_VBAT,
467 ADC_VCHARG,
468 ADC_ICHARG,
469 ADC_VBACKUP,
470 ADC_BATTYP,
471 ADC_BATTEMP,
472 ADC_ADC3, // name of this ??
473 ADC_RFTEMP,
474 ADC_ADC4,
475 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
476 };
477
478 typedef struct
479 {
480 WORD16 converted[ADC_INDEX_END]; // converted
481 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
482 }
483 T_ADC;
484
485 /************************************/
486 /* MADC calibration */
487 /************************************/
488 typedef struct
489 {
490 UWORD16 a[ADC_INDEX_END];
491 WORD16 b[ADC_INDEX_END];
492 }
493 T_ADCCAL;
494
495 // Conversion table: ADC value -> temperature
496 typedef struct
497 {
498 UWORD16 adc; // ADC reading is 10 bits
499 WORD16 temp; // temp is in approx. range -30..+80
500 }
501 T_TEMP;
502
503 typedef struct
504 {
505 char *name;
506 void *addr;
507 int size;
508 }
509 T_CONFIG_FILE;
510
511 typedef struct
512 {
513 char *name; // name of ffs file suffix
514 T_RF_BAND *addr; // address to default flash structure
515 UWORD16 max_carrier; // max carrier
516 UWORD16 max_txpwr; // max tx power
517 }
518 T_BAND_CONFIG;
519
520 typedef struct
521 {
522 UWORD8 band[GSM_BANDS]; // index to band address
523 UWORD8 txpwr_tp; // tx power turning point
524 UWORD16 first_arfcn; // first index
525 }
526 T_STD_CONFIG;
527 enum GSMBAND_DEF
528 {
529 BAND_NONE,
530 BAND_EGSM900,
531 BAND_DCS1800,
532 BAND_PCS1900,
533 BAND_GSM850,
534 // put new bands here
535 BAND_GSM900 //last entry
536 };
537
538 /************************************/
539 /* ABB (Omega) Initialization */
540 /************************************/
541
542 #if ((ANALOG == 1) || (ANALOG == 2))
543 #define ABB_TABLE_SIZE 16
544 #elif (ANALOG == 3)
545 #define ABB_TABLE_SIZE 22
546 #endif
547
548 // Note that this translation is probably not needed at all. But until L1 is
549 // (maybe) changed to simply initialize the ABB from a table of words, we
550 // use this to make things more easy-readable.
551 #if (ANALOG == 1)
552 enum ABB_REGISTERS {
553 ABB_AFCCTLADD = 0,
554 ABB_VBUR,
555 ABB_VBDR,
556 ABB_BBCTL,
557 ABB_APCOFF,
558 ABB_BULIOFF,
559 ABB_BULQOFF,
560 ABB_DAI_ON_OFF,
561 ABB_AUXDAC,
562 ABB_VBCR,
563 ABB_APCDEL
564 };
565 #elif (ANALOG == 2)
566 enum ABB_REGISTERS {
567 ABB_AFCCTLADD = 0,
568 ABB_VBUR,
569 ABB_VBDR,
570 ABB_BBCTL,
571 ABB_BULGCAL,
572 ABB_APCOFF,
573 ABB_BULIOFF,
574 ABB_BULQOFF,
575 ABB_DAI_ON_OFF,
576 ABB_AUXDAC,
577 ABB_VBCR,
578 ABB_VBCR2,
579 ABB_APCDEL,
580 ABB_APCDEL2
581 };
582 #elif (ANALOG == 3)
583 enum ABB_REGISTERS {
584 ABB_AFCCTLADD = 0,
585 ABB_VBUR,
586 ABB_VBDR,
587 ABB_BBCTL,
588 ABB_BULGCAL,
589 ABB_APCOFF,
590 ABB_BULIOFF,
591 ABB_BULQOFF,
592 ABB_DAI_ON_OFF,
593 ABB_AUXDAC,
594 ABB_VBCR,
595 ABB_VBCR2,
596 ABB_APCDEL,
597 ABB_APCDEL2,
598 ABB_VBPOP,
599 ABB_VAUDINITD,
600 ABB_VAUDCR,
601 ABB_VAUOCR,
602 ABB_VAUSCR,
603 ABB_VAUDPLL
604 };
605 #endif