FreeCalypso > hg > freecalypso-citrine

comparison L1/cust1/l1_rf61.h @ 0:75a11d740a02

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
parents
children
comparison
equal deleted inserted replaced
-1:000000000000 0:75a11d740a02
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename l1_rf61.h
5 * Version 1.0
6 * Date June 16th, 2005
7 *
8 ************* Revision Controle System Header *************/
9
10 #ifndef __L1_RF_H__
11 #define __L1_RF_H__
12
13 #if (ANLG_FAM == 11)
14 #include "bspTwl3029_Madc.h"
15 #endif
16
17 #define RF_LOCOSTO 0x2050 // Check with TIDK
18
19 //LNA Specific BAND Index Settings
20 #define RF_QUADBAND 0 //Default Setting 850, EGSM,DCS,PCS
21 #define RF_EU_TRIBAND 1 // EGSM,DCS,PCS
22 #define RF_EU_DUALBAND 2 // EGSM,DCS
23 #define RF_US_TRIBAND 3 // 850,DCS,PCS
24 #define RF_US_DUALBAND 4 //850, PCS
25 #define RF_PCS1900_900_DUALBAND 5 // EGSM, PCS
26 #define RF_DCS1800_850_DUALBAND 6 //850, DCS
27
28 #define RF_BAND_SYSTEM_INDEX RF_QUADBAND //for other PCB's Please redefine here.
29 #define RF_LNA_MASK 0x0003 // Reuse last 2 bits from
30
31 //End LNA Changes
32
33 //#define RF_HW_BAND_EGSM
34 //#define RF_HW_BAND_DCS
35 #define RF_HW_BAND_PCS 0x4
36 #define RF_HW_BAND_DUAL_US 0x80
37 #define RF_HW_BAND_DUAL_EXT 0x20
38 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT)
39
40 /************************************/
41 /* SYNTHESIZER setup time... */
42 /************************************/
43 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1) //RX Synthesizer setup time in qbit.
44 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
45
46 /************************************/
47 /* Time for TPU scenario ending... */
48 /************************************/
49 //
50 // The following values are used to take into account any TPU activity AFTER
51 // BDLON (or BDLENA) down (for RX) and BULON down (for TX)
52 // - If there are no TPU commands after BDLON (or BDLENA) down and BULON down,
53 // these defines must be ZERO
54 // - If there IS some TPU command after BDLON (or BDLENA) and BULON down,
55 // these defines must be equal to the time difference (in qbits) between
56 // the BDLON (or BDLENA) or BULON time and the last TPU command on
57 // the TPU scenario
58 #define RX_TPU_SCENARIO_ENDING 6 // execution time of AFTER BDLENA down last value : 0
59 #define TX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BULON down last value : 14
60
61
62 /******************************************************/
63 /* TXPWR configuration... */
64 /* Fixed TXPWR value when GSM management is disabled. */
65 /******************************************************/
66 #if ( ANLG_FAM == 11)
67 #define FIXED_TXPWR 0x5C // TXPWR=500 for the moment...change later TEMP_FIX
68 #endif
69
70
71 /************************************/
72 /* RF delay (in qbits) */
73 /************************************/
74 #define DL_DELAY_RF 0 // time spent in the Downlink global RF chain by the modulated signal
75 #define UL_DELAY_1RF 0 // time spent in the first uplink RF block
76 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
77
78 #define UL_ABB_DELAY 12 // 12 for RF output DELAY
79
80 #define GUARD_BITS 5
81
82 /************************************/
83 /* TX Propagation delay... */
84 /************************************/
85 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 50
86
87 /************************************/
88 /* Initial value for APC DELAY */
89 /************************************/
90 #define APCDEL_DOWN (0) // To add this value, the setup delay minimum value: 2 last value : 0
91 //SG #define APCDEL_UP (12)
92 #define APCDEL_UP (0) //To add this value, the setup delay minimum value: 6
93 #define C_APCDEL1 (((APCDEL_DOWN & 0x1f)<<5) |(APCDEL_UP & 0x1f) )
94 #define C_APCDEL2 (((APCDEL_DOWN & 0x3e0)) |((APCDEL_UP>>5) & 0x1f) )
95
96
97 /************************************/
98 /* Initial value for AFC... */
99 /************************************/
100 #define EEPROM_AFC ((150)*8) // F14.2 required!!!!! (default : -952*8, initial deviation of -2400 forced)
101
102 #if(CHIPSET == 15)
103 #define SETUP_AFC_AND_RF 0
104 #else
105 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames and RF BAND GAP stable after 4 frames
106 #endif
107 #define C_DRP_DCXO_XTAL_DSP_ADDRESS 0x7F80 // DRP DCXO XTAL DSP address
108
109 /************************************/
110 /* DCO Registers Initialization */
111 /************************************/
112 #define C_DCO_SAMPLES_PER_SYMBOL 1
113 /* The basic frequency table in DSP is approximately 2.115KHz (26MHZ/(512*24))
114 * The FCW value needs to intended IF Frequency / 2.115KHZ.
115 * Hence since IF is 100KFZ, FCW = 100 / 2.115 ~= 47 */
116 #define C_DCO_FCW 47
117
118 /***************************************************************
119 * Threshold between LIF_100 KHZ (at high power levels) and
120 * LIF_120KHz (at low power level)
121 * the threshold defintion for GSM and GPRS is as given below
122 * ************************************************************ */
123 #define C_IF_ZERO_LOW_THRESHOLD_GSM 180 // if IL < -90dbm use Zero IF else Low IF STd L1 format
124 #define C_IF_ZERO_LOW_THRESHOLD_GPRS 180 // if IL < -90dbm use Zero IF else Low IF STd L1 format
125
126 /* Since CSF filter coefficients are changed in accordance with GENIE
127 * algorithm, below are values programmed in DRP to select HW/SW CSF filter */
128 #define CSF_CWL_HARDWARE_FILTER_64TAP 0x0100
129 #define CSF_CWL_PROGRAMMABLE_FILTER_64TAP 0x0000
130
131 /* Below are the attenuation losses to be compensated for LIF_100KHZ and LIF_120KHZ Path
132 * !!!! Note: The below attenuations are applicable when ROC is enabled !!!! */
133 #define SCF_ATTENUATION_LIF_100KHZ (0) /* value of 0 represents 0dB attenuation as per L1 F7.1 format */
134 #define SCF_ATTENUATION_LIF_120KHZ (1) /* value of 1 represents 0.5dB attenuation */
135 #define SCF_ATTENUATION_ZIF (0) /* No attenuation when ZIF mode is used */
136
137
138 /************************************/
139 /* DRP Retiming Related */
140 /************************************/
141 #define C_RETIMING_DISABLED 0x0
142 #define C_RETIMING_ENABLED 0x1
143
144 #define C_RETIMING_CONFIG C_RETIMING_DISABLED
145
146 /*************************************/
147 /* DRP WRAPPER Initialization */
148 /*************************************/
149 #define C_APCCTRL2 0x05C8 // BGEN=1, APCOFF=64, APC_LDO_EN=0, MODE=0
150 // SG #define C_APCCTRL2 0x01FC
151 #define DRP_DBB_RX_IRQ_COUNT 16
152
153 #define TTY_L1_STANDALONE 0
154
155 /************************************/
156 /* Triton audio initialize */
157 /************************************/
158 #if (ANLG_FAM == 11)
159 #if (TTY_L1_STANDALONE == 1)
160 #define C_VULGAIN 0x10 // -12dB
161 // #define C_VULGAIN 0x09 // voice uplink gain set to 7dB
162 #define C_SIDETONE 0x0d // -23dB
163 // #define C_SIDETONE 0x0f // side tone set to MUTE
164 #define C_VDLGAIN 0x4c //
165 // #define C_VDLGAIN 0x2c // set PGA gain to 2dB
166 #define C_CTRL1 0x30 // MicBias = 1, DL Filter Bypass
167 // #define C_CTRL1 0x00 // VSYNC = 1, reset Dig Modulator, VSP, Digital filter
168 #define C_CTRL2 0x10 //
169 // #define C_CTRL2 0x00 // reset value
170 #define C_CTRL3 0x25 // MIC IN (diff), MICIP, MICIN. Amplifier: MIC AMP, Gain = 25.6 dB, SPKAMP = +2.5 dB
171 #define C_CTRL4 0x00 // reset value
172 #define C_CTRL5 0x28 // SAMP FREQ = 48Khz, EARAMP = 1 dB
173 #define C_CTRL6 0x00 // reset value
174 #define C_POPAUTO 0x01 // POPmode set to/Automatic mode
175 #define C_OUTEN1 0x12 // Audio left/Audio Mono, Audio Right/ Audio mono
176 #define C_OUTEN2 0x05 // EAR= voice speech, AUXO = voice speech
177 #define C_OUTEN3 0x01 // SPK = voice speech
178 #define C_AULGA 0x00 // reset value
179 #define C_AURGA 0x00 // reset value
180 #else
181 #define C_VULGAIN 0x09 // voice uplink gain set to 7dB
182 #define C_SIDETONE 0x06 // side tone set to MUTE
183 #define C_VDLGAIN 0x2c // set PGA gain to 2dB
184 #define C_CTRL1 0x00 // VSYNC = 1, reset Dig Modulator, VSP, Digital filter
185 #define C_CTRL2 0x00 // reset value
186 #define C_CTRL3 0x21 // MIC IN (diff), MICIP, MICIN. Amplifier: MIC AMP, Gain = 25.6 dB, SPKAMP = +2.5 dB
187 #define C_CTRL4 0x00 // reset value
188 #define C_CTRL5 0x28 // SAMP FREQ = 48Khz, EARAMP = 1 dB
189 #define C_CTRL6 0x00 // reset value
190 #define C_POPAUTO 0x01 // POPmode set to/Automatic mode
191 #define C_OUTEN1 0x24 // Audio left/Audio Mono, Audio Right/ Audio mono
192 #define C_OUTEN2 0x01 // EAR= voice speech, AUXO = voice speech
193 #define C_OUTEN3 0x01 // SPK = voice speech
194 #define C_AULGA 0x00 // reset value
195 #define C_AURGA 0x00 // reset value
196 #endif //(L1_GTT == 1)
197 #endif //(ANLG_FAM == 11)
198
199 /************************************/
200 /* Automatic frequency compensation */
201 /************************************/
202 /********************* C_Psi_sta definition *****************************/
203 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
204 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
205 /* regarding Vega V/N = 2.4/4096 */
206 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
207 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
208 /* = 0.000195748 */
209 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
210 /************************************************************************/
211 #define C_Psi_sta_inv 6142L // 12902L // (1/C_Psi_sta)
212 #define C_Psi_st 9L // 4L // C_Psi_sta * 0.8 F0.16
213 #define C_Psi_st_32 559386L // 266313L // F0.32
214 #define C_Psi_st_inv 7678L // 16128L // (1/C_Psi_st)
215
216 #if (VCXO_ALGO == 1)
217 // Linearity parameters
218 #define C_AFC_DAC_CENTER ((4264)) //((-1242)*8)
219 #define C_AFC_DAC_MIN ((-11128)) //((-2000)*8)
220 #define C_AFC_DAC_MAX ((19656)) //((1419)*8)
221 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10
222 #endif
223
224 typedef struct
225 {
226 WORD16 eeprom_afc;
227 UWORD32 psi_sta_inv;
228 UWORD32 psi_st;
229 UWORD32 psi_st_32;
230 UWORD32 psi_st_inv;
231
232 #if (VCXO_ALGO)
233 // VCXO adjustment parameters
234 // Parameters used when assuming linearity
235 WORD16 dac_center;
236 WORD16 dac_min;
237 WORD16 dac_max;
238 WORD16 snr_thr;
239 #endif
240 }
241 T_AFC_PARAMS;
242
243 /************************************/
244 /* Swap IQ definitions... */
245 /************************************/
246 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
247 #define SWAP_IQ_GSM 0
248 #define SWAP_IQ_DCS 0
249 #define SWAP_IQ_PCS 0
250 #define SWAP_IQ_GSM850 0 // Swap TX compared to GSM 900
251
252 #define LNA_OFF (1)
253 #define LNA_ON (0)
254 /************************************/
255 /************************************/
256 // typedef
257 /************************************/
258 /************************************/
259
260 /*************************************************************/
261 /* Define structure for apc of TX Power ******/
262 /*************************************************************/
263 typedef struct
264 { // pcm-file "rf/tx/level.gsm|dcs"
265 UWORD16 apc; // 0..31
266 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
267 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
268 }
269 T_TX_LEVEL;
270
271 /************************************/
272 /* Automatic Gain Control */
273 /************************************/
274 /* Define structure for sub-band definition of TX Power ******/
275 typedef struct
276 {
277 UWORD16 upper_bound; //highest physical arfcn of the sub-band
278 WORD16 agc_calib; // AGC for each TXPWR
279 } T_RF_AGC_BAND;
280
281 /************************************/
282 /* Ramp definitions */
283 /************************************/
284
285 typedef struct
286 {
287 UWORD8 ramp_up [20]; // Ramp-up profile
288 UWORD8 ramp_down [20]; // Ramp-down profile
289 }
290 T_TX_RAMP;
291
292
293 // RF structure definition
294 //========================
295 #if (L1_FF_MULTIBAND == 0)
296 // Number of bands supported
297 #define GSM_BANDS 2
298
299 #define MULTI_BAND1 0
300 #define MULTI_BAND2 1
301 #else
302 #endif
303
304 // RF table sizes
305 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
306 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
307
308 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
309 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
310 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
311 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
312 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
313
314 #define AGC_TABLE_SIZE 24
315 #define MIN_AGC_INDEX 0 // size step for AGC table
316
317 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
318 #if (REL99 && FF_PRF)
319 #define MAX_UPLINK_TIME_SLOT 4 // max number of time slot in uplink
320 #endif
321
322
323 // RX parameters and tables
324 //-------------------------
325
326 // AGC parameters and tables
327 typedef struct
328 {
329 UWORD16 low_agc_noise_thr;
330 UWORD16 high_agc_sat_thr;
331 UWORD16 low_agc;
332 UWORD16 high_agc;
333 UWORD8 il2agc_pwr[121];
334 UWORD8 il2agc_max[121];
335 UWORD8 il2agc_av[121];
336 }
337 T_AGC;
338
339 // Calibration parameters
340 typedef struct
341 {
342 UWORD16 g_magic;
343 UWORD16 lna_att;
344 UWORD16 lna_switch_thr_low;
345 UWORD16 lna_switch_thr_high;
346 }
347 T_RX_CAL_PARAMS;
348
349 // RX temperature compensation
350 typedef struct
351 {
352 WORD16 temperature;
353 WORD16 agc_calib;
354 }
355 T_RX_TEMP_COMP;
356
357 // RF RX structure
358 typedef struct
359 {
360 T_AGC agc;
361 }
362 T_RF_RX; //common
363
364 // RF RX structure
365 typedef struct
366 {
367 T_RX_CAL_PARAMS rx_cal_params;
368 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
369 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
370 }
371 T_RF_RX_BAND;
372
373
374 // TX parameters and tables
375 //-------------------------
376
377 // TX temperature compensation
378 typedef struct
379 {
380 WORD16 temperature;
381 #if (ORDER2_TX_TEMP_CAL==1)
382 WORD16 a;
383 WORD16 b;
384 WORD16 c;
385 #else
386 WORD16 apc_calib;
387 #endif
388 }
389 T_TX_TEMP_CAL;
390
391 // Ramp up and ramp down delay
392 typedef struct
393 {
394 UWORD16 up;
395 UWORD16 down;
396 }
397 T_RAMP_DELAY;
398
399 typedef struct
400 {
401 UWORD16 arfcn_limit;
402 WORD16 chan_cal;
403 }
404 T_TX_CHAN_CAL;
405
406 // RF TX structure
407 typedef struct
408 {
409 T_RAMP_DELAY ramp_delay;
410 UWORD8 guard_bits; // number of guard bits needed for ramp up
411 UWORD8 prg_tx;
412 }
413 T_RF_TX; //common
414
415 // RF TX structure
416 typedef struct
417 {
418 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
419 #if (REL99 && FF_PRF)
420 T_TX_LEVEL levels_power_reduction[MAX_UPLINK_TIME_SLOT];
421 #endif
422 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
423 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
424 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
425 }
426 T_RF_TX_BAND;
427
428 // band structure
429 typedef struct
430 {
431 T_RF_RX_BAND rx;
432 T_RF_TX_BAND tx;
433 UWORD8 swap_iq;
434 }
435 T_RF_BAND;
436
437 // RF structure
438 typedef struct
439 {
440 // common for all bands
441 UWORD16 rf_revision;
442 UWORD16 radio_band_support;
443 T_RF_RX rx;
444 T_RF_TX tx;
445 T_AFC_PARAMS afc;
446 }
447 T_RF;
448
449 /************************************/
450 /* MADC definitions */
451 /************************************/
452 // TRITON: 5 external channels
453 enum ADC_INDEX {
454 ADC_ADIN1,
455 ADC_ADIN2,
456 ADC_ADIN3,
457 ADC_BATT_TYPE,
458 ADC_BTEMP,
459 ADC_USBVBUS ,
460 ADC_VBKP,
461 ADC_ICHG,
462 ADC_VCHG,
463 ADC_VBAT,
464 ADC_HOTDIE ,
465 ADC_RFTEMP,
466 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
467 };
468
469
470 typedef struct
471 {
472 WORD16 converted[ADC_INDEX_END]; // converted
473 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
474 }
475 T_ADC;
476
477
478 /************************************/
479 /* MADC calibration */
480 /************************************/
481 typedef struct
482 {
483 UWORD16 a[ADC_INDEX_END];
484 WORD16 b[ADC_INDEX_END];
485 }
486 T_ADCCAL;
487
488 // Conversion table: ADC value -> temperature
489 typedef struct
490 {
491 UWORD16 adc; // ADC reading is 10 bits
492 WORD16 temp; // temp is in approx. range -30..+80
493 }
494 T_TEMP;
495
496 typedef struct
497 {
498 char *name;
499 void *addr;
500 int size;
501 }
502 T_CONFIG_FILE;
503
504 #if (L1_FF_MULTIBAND == 0)
505
506 typedef struct
507 {
508 char *name; // name of ffs file suffix
509 T_RF_BAND *addr; // address to default flash structure
510 UWORD16 max_carrier; // max carrier
511 UWORD16 max_txpwr; // max tx power
512 }
513 T_BAND_CONFIG;
514
515 typedef struct
516 {
517 UWORD8 band[GSM_BANDS]; // index to band address
518 UWORD8 txpwr_tp; // tx power turning point
519 UWORD16 first_arfcn; // first index
520 }
521 T_STD_CONFIG;
522
523 enum GSMBAND_DEF
524 {
525 BAND_NONE,
526 BAND_EGSM900,
527 BAND_DCS1800,
528 BAND_PCS1900,
529 BAND_GSM850,
530 // put new bands here
531 BAND_GSM900 //last entry
532 };
533 #endif // L1_FF_MULTIBAND == 0
534
535 /************************************/
536 /* ABB (TRITON) Initialization */
537 /************************************/
538
539 /* ABB_TABLE_SIZE definitions for Triton */
540 #if (ANLG_FAM == 11)
541 #define ABB_TABLE_SIZE 15
542 #endif
543
544 /* ABB enum definitions for TRITON */
545 #if (ANLG_FAM == 11)
546 enum ABB_REGISTERS {
547 ABB_VULGAIN = 0,
548 ABB_VDLGAIN,
549 ABB_SIDETONE,
550 ABB_CTRL1,
551 ABB_CTRL2,
552 ABB_CTRL3,
553 ABB_CTRL4,
554 ABB_CTRL5,
555 ABB_CTRL6,
556 ABB_POPAUTO,
557 ABB_OUTEN1,
558 ABB_OUTEN2,
559 ABB_OUTEN3,
560 ABB_AULGA,
561 ABB_AURGA
562 };
563 #endif
564
565 /*************************************/
566 /* DRP WRAPPER Table */
567 /*************************************/
568 #define DRP_WRAPPER_TABLE_SIZE 3
569
570 enum DRP_WRAPPER_REGISTERS {
571 DRP_WRAPPER_APCCTRL2 = 0,
572 DRP_WRAPPER_APCDEL1,
573 DRP_WRAPPER_APCDEL2
574 };
575
576 extern T_RF_BAND rf_band[];
577 #endif //__L1_RF_H