FreeCalypso > hg > freecalypso-citrine

comparison L1/include/l1_confg.h @ 0:75a11d740a02

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
parents
children f93dab57b032
comparison
equal deleted inserted replaced
-1:000000000000 0:75a11d740a02
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_CONFG.H
4 *
5 * Filename l1_confg.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #ifndef __L1_CONFG_H__
11 #define __L1_CONFG_H__
12
13 // Traces...
14 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART
15 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack
16 // TRACE_TYPE == 1 -> L1/L3 interface trace
17 // TRACE_TYPE == 2 -> Trace mode: ~33~~1~011...
18 // TRACE_TYPE == 3 -> same as above (2) plus FER or stats trace
19 // TRACE_TYPE == 4 -> L1/L3 interface trace on A-sample with protocol stack
20 // TRACE_TYPE == 5 -> trace for full simulation
21 // TRACE_TYPE == 6 -> CPU load trace for hisr
22 // TRACE_TYPE == 7 -> CPU LOAD trace for layer 1 hisr for all TDMA. Output on
23 // UART at 38400 bps =>
24 // format : <hisr cpu value in microseconds> <frame number>
25
26 // Code PB reported workaround
27 //------------------------------
28
29
30 // Code Version possible choices
31 //------------------------------
32 #define SIMULATION 1
33 #define NOT_SIMULATION 2
34
35 // RLC functions Version possible choices
36 //------------------------------
37 #define POLL_FORCED 0
38 #define RLC_SCENARIO 1
39 #define MODEM_FLOW 2
40
41 // possible choices for UART trace output
42 //------------------------------
43 #if (CHIPSET != 15)
44 #define MODEM_UART 0
45 #define IRDA_UART 1
46 #if (CHIPSET == 12)
47 #define MODEM2_UART 2
48 #endif
49 #else
50 // There is only one UART in Locosto
51 #define MODEM_UART 0
52 #endif
53
54 //============
55 // CODE CHOICE
56 //============
57 #if 0
58 #if (OP_L1_STANDALONE==0)
59 #define CODE_VERSION NOT_SIMULATION
60 #else // OP_L1_STANDALONE
61 #ifdef WIN32
62 #define CODE_VERSION SIMULATION
63 #else // WIN32
64 #define CODE_VERSION NOT_SIMULATION
65 #endif // WIN32
66 #endif // OP_L1_STANDALONE
67 #endif // #if 0
68
69 /* FreeCalypso */
70 #define CODE_VERSION NOT_SIMULATION
71 #define AMR 1
72 #define L1_12NEIGH 1
73 #define L1_EOTD 0
74 #define L1_GTT 0
75 #define ORDER2_TX_TEMP_CAL 1
76 #define TRACE_TYPE 4
77 #define VCXO_ALGO 1
78
79 /* TESTMODE will be enabled with feature l1tm */
80
81 #if CONFIG_AUDIO
82 # define AUDIO_TASK 1 // Enable the L1 audio features
83 # define MELODY_E2 1
84 #endif
85
86 #if CONFIG_GPRS
87 # define L1_GPRS 1
88 #else
89 # define L1_GPRS 0
90 #endif
91
92 //---------------------------------------------------------------------------------
93 // Test with full simulation.
94 //---------------------------------------------------------------------------------
95 #if (CODE_VERSION == SIMULATION)
96
97
98 #undef FF_L1_IT_DSP_USF
99 #define FF_L1_IT_DSP_USF 0
100 #undef FF_L1_IT_DSP_DTX
101 #if (AMR == 1)
102 #define FF_L1_IT_DSP_DTX 1 //it should be 1, sajal- temp made it 0 for build purpose
103 #else
104 #define FF_L1_IT_DSP_DTX 0
105 #endif
106
107 #define L1_DRP_IQ_SCALING 0
108
109 // Test Scenari...
110 #define SCENARIO_FILE 1 // Test Scenario comes from input files.
111 #define SCENARIO_MEM 0 // Test Scenario comes from RAM.
112
113 // In Simulation AUDIO_DEBUG Should be 0
114 #define AUDIO_DEBUG 0
115
116 // Traces...
117 #undef TRACE_TYPE
118 #define TRACE_TYPE 5
119 #define LOGFILE_TRACE 1 // trace in an output logfile
120
121 #define BURST_PARAM_LOG_ENABLE 0 // Burst Param Log Enable
122
123 #define FLOWCHART 0 // Message sequence/flow chart trace.
124 #define NUCLEUS_TRACE 0 // Nucleus error trace
125 #define EOTD_TRACE 1 // EOTD log trace
126 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
127
128 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
129
130 // Control algorithms...
131 #define AFC_ALGO 1 // AFC algorithm.
132 #if (L1_SAIC != 0)
133 #define TOA_ALGO 2 // TOA algorithm.
134 #else
135 #define TOA_ALGO 1 // TOA algorithm.
136 #endif
137 #define AGC_ALGO 1 // AGC algorithm.
138 #define TA_ALGO 0 // TA (Timing Advance) algorithm.
139 #undef VCXO_ALGO
140 #define VCXO_ALGO 1 // VCXO algo
141 #undef DCO_ALGO
142 #define DCO_ALGO 0 // DCO algo (TIDE)
143 #undef ORDER2_TX_TEMP_CAL
144 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection
145
146
147 #define FACCH_TEST 0 // FACCH test enabled.
148
149 #define ADC_TIMER_ON 0 // Timer for ADC measurements
150 #define AFC_ON 1 // Enable of the Omega AFC module
151
152 #define AUDIO_TASK 1 // Enable the L1 audio features
153 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
154 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
155
156 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
157 #define TTY_SYNC_MCU 0 // TTY WORKAROUND BUG03401
158 #define TTY_SYNC_MCU_2 0 //
159 #define L1_GTT_FIFO_TEST_ATOMIC 0 //
160 #define NEW_WKA_PATCH 0
161 #define OPTIMISED 0
162
163 #define L1_RECOVERY 0 // L1 recovery
164
165 #undef L1_GPRS
166 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities
167
168 #undef AMR
169 #define AMR 1 // AMR version 1.0 supported
170
171 #undef L1_12NEIGH
172 #define L1_12NEIGH 1 // new L1-RR interface for 12 neighbour cells
173
174 #undef L1_GTT
175 #define L1_GTT 1 // Enable Global Text Telephony feature for simulation
176
177 #undef OP_L1_STANDALONE
178 #define OP_L1_STANDALONE 1 // Selection of code for L1 stand alone
179
180 #undef OP_RIV_AUDIO
181 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio
182
183 #undef OP_WCP
184 #define OP_WCP 0 // No WCP integration
185
186 #undef L1_DRP
187 #define L1_DRP 0 // L1 supporting DRP interface
188
189 #undef DRP_MEM_SIMULATION
190 #define DRP_MEM_SIMULATION 0
191 //---------------------------------------------------------------------------------
192 // Test with H/W platform.
193 //---------------------------------------------------------------------------------
194
195 #if (GSM_IDLE_RAM == 1)
196 #define GSM_IDLE_RAM_DEBUG 0
197 #endif
198
199 #define AFC_BYPASS_MODE 0
200 #define PWMEAS_IF_MODE_FORCE 0
201 // WA for OMAPS00099442 must be disabled in PC simulation
202 #undef L1_FF_WA_OMAPS00099442
203 #define L1_FF_WA_OMAPS00099442 0
204
205 #elif (CODE_VERSION == NOT_SIMULATION)
206
207 #define L1_DRP_IQ_SCALING 1
208 // In Target AUDIO_DEBUG could be turned ON to debug any AUDIO ON/OFF issues
209 #define AUDIO_DEBUG 0
210
211 #if (GSM_IDLE_RAM == 1)
212 #if ((CHIPSET == 12) || (CHIPSET == 10))
213 #define GSM_IDLE_RAM_DEBUG 1
214 #else
215 #define GSM_IDLE_RAM_DEBUG 0
216 #endif
217 #else
218 #define GSM_IDLE_RAM_DEBUG 0
219 #endif
220
221 //FreeCalypso: L1_VPM commented out, as I suspect it's a LoCosto-ism
222 //#define L1_VPM 1
223
224 #if (OP_L1_STANDALONE == 1)
225 #if (CHIPSET == 15)
226 #if ((BOARD == 71) && (FLASH == 0))
227 // Not possible in I-SAMPLE only RAM configuration as there will
228 // not be enough memory space
229 #define BURST_PARAM_LOG_ENABLE 0
230 #else
231 #define BURST_PARAM_LOG_ENABLE 1
232 #endif
233 #else
234 #define BURST_PARAM_LOG_ENABLE 0
235 #endif
236 #else
237 #define BURST_PARAM_LOG_ENABLE 0
238 #endif
239
240 // Work around about Calypso RevA: the bus is floating (Cf PB01435)
241 // (corrected with Calypso ReV B and Calypso C035)
242 #if (CHIPSET == 7)
243 #define W_A_CALYPSO_BUG_01435 1
244 #else
245 #define W_A_CALYPSO_BUG_01435 0
246 #endif
247
248 #if (CHIPSET == 12) // Not needed for CHIPSET =15, as there is no extended page mode in Locosto
249 #define W_A_CALYPSO_PLUS_SPR_19599 1
250 #else
251 #define W_A_CALYPSO_PLUS_SPR_19599 0
252 #endif
253
254 // for AMR thresolds definition CQ22226
255 #define W_A_AMR_THRESHOLDS 1
256 #define W_A_PCTM_RX_AGC_GLOBAL_PARAMS 1 // For support of PCTM
257
258 #if (L1_GTT==1)
259 #define TTY_SYNC_MCU 0
260 #define TTY_SYNC_MCU_2 0
261 #define L1_GTT_FIFO_TEST_ATOMIC 0
262 #define NEW_WKA_PATCH 0
263 #define OPTIMISED 0
264 #else
265 #define TTY_SYNC_MCU_2 0
266 #define L1_GTT_FIFO_TEST_ATOMIC 0
267 #define TTY_SYNC_MCU 0
268 #define NEW_WKA_PATCH 0
269 #define OPTIMISED 0
270
271 #endif
272
273 /*
274 * FreeCalypso: these FF_L1_IT_DSP_USF and FF_L1_IT_DSP_DTX features (?)
275 * are new with the LoCosto L1 headers, i.e., not present in the Leonardo
276 * headers. I have no idea what they are, and I suspect they may likely
277 * be something that won't work on our Calypso platform, so I'm disabling
278 * them for now.
279 */
280
281 #undef FF_L1_IT_DSP_USF
282 #if 0 //(L1_GPRS == 1)
283 #define FF_L1_IT_DSP_USF 1
284 #else
285 #define FF_L1_IT_DSP_USF 0
286 #endif
287 #undef FF_L1_IT_DSP_DTX
288 #if 0 //(AMR == 1)
289 #define FF_L1_IT_DSP_DTX 1
290 #else
291 #define FF_L1_IT_DSP_DTX 0
292 #endif
293
294 // Traces...
295 #define NUCLEUS_TRACE 0 // Nucleus error trace
296 #define FLOWCHART 0 // Message sequence/flow chart trace.
297 #define LOGFILE_TRACE 0 // trace in an output logfile
298 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
299
300 // Test Scenari...
301 #define SCENARIO_FILE 0 // Test Scenario comes from input files.
302 #define SCENARIO_MEM 1 // // Test Scenario comes from RAM.
303
304 #if (OP_L1_STANDALONE == 1)
305 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
306 #else
307 #define L2_L3_SIMUL 0
308 #endif
309
310 // Control algorithms...
311 #define AFC_ALGO 1 // AFC algorithm.
312 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
313 #if (L1_SAIC != 0)
314 #define TOA_ALGO 2 // TOA algorithm.
315 #else
316 #define TOA_ALGO 1 // TOA algorithm.
317 #endif
318 #define AGC_ALGO 1 // AGC algorithm.
319 #define TA_ALGO 1 // TA (Timing Advance) algorithm.
320
321 #define FACCH_TEST 0 // FACCH test enabled.
322
323 #define ADC_TIMER_ON 0 // Timer for ADC measurements
324 #define AFC_ON 1 // Enable of the Omega AFC module
325
326 #if 0
327 /* FreeCalypso: moved to config section above */
328 #define AUDIO_TASK 1 // Enable the L1 audio features
329 #endif
330 #define AUDIO_SIMULATION 0 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
331 #if (OP_L1_STANDALONE == 1)
332 #define AUDIO_L1_STANDALONE 1 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
333 #else
334 #define AUDIO_L1_STANDALONE 0
335 #endif
336
337 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
338
339 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management
340
341 #define L1_RECOVERY 1 // L1 recovery
342
343 #if ((RF_FAM == 60) || (RF_FAM == 61))
344 #define L1_DRP 1 // L1 supporting DRP interface
345 #else
346 #define L1_DRP 0 // L1 supporting DRP interface
347 #endif
348 #define DRP_MEM_SIMULATION 0 // DRP memory simulation OFF by default
349
350 #if (L1_GPRS == 1)
351 #define RLC_VERSION RLC_SCENARIO
352 #if (RLC_VERSION == RLC_SCENARIO)
353 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO
354 // output stat on CRC error blocks
355 // The user must enter the cs type and
356 // the number of frames desired.
357 #else
358 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
359 #endif
360
361 #if (OP_L1_STANDALONE == 1)
362 #define DSP_BACKGROUND_TASKS 1 // Enable the TEST of DSP background.tasks
363 // activated by a layer 3 message (BG_TASK_START (<task number>))
364 // deactivated by a layer 3 message (BG_TASK_STOP (<task number>))
365 // Warning : Works only with DSP>=31
366 #else
367 #define DSP_BACKGROUND_TASKS 0
368 #endif
369
370 #else
371 #define DSP_BACKGROUND_TASKS 0
372 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
373 #endif
374 #define PWMEAS_IF_MODE_FORCE 1
375 // WA for OMAPS00099442 (OMAPS0010023 (N12.x), OMAPS000010022 (N5.x))
376 // The problem is: When NW is lost due to reception gap or cell border range,
377 // the MS will try to re-synchronize on the cell with the TPU timing aligned
378 // with the timing of the cell. So the FB will start within the 92 bits of the TPU window and
379 // will be missed. This issue is due to a limitation of the legacy FB demodulation algorithm
380 // WA is to re-initialize the TPU with an arbitrary timing value
381 #undef L1_FF_WA_OMAPS00099442
382 #define L1_FF_WA_OMAPS00099442 1
383
384 #endif
385
386 // Audio tasks selection
387 //-----------------------
388
389 #if (AUDIO_TASK == 1)
390 #define KEYBEEP 1 // Enable keybeep feature
391 #define TONE 1 // Enable tone feature
392 // Temporary modification for protocol stack compatibility - GSMLITE will be removed
393 #if (OP_L1_STANDALONE == 1)
394 #define GSMLITE 1
395 #endif
396 #if (CODE_VERSION == SIMULATION)
397 #define L1_VOICE_MEMO 1
398 #endif
399 #if ((OP_L1_STANDALONE == 1) || (!GSMLITE))
400 #define MELODY_E1 1 // Enable melody format E1 feature
401
402 #if(L1_VOICE_MEMO == 1)
403 #define VOICE_MEMO 1 // Enable voice memorization feature
404 #else
405 #define VOICE_MEMO 0
406 #endif
407 #define FIR 1 // Enable FIR feature
408 #if (DSP >= 33)
409 #define AUDIO_MODE 1 // Enable Audio mode feature
410 #else
411 #define AUDIO_MODE 0 // Disable Audio mode feature
412 #endif
413 #else
414 #define MELODY_E1 0 // Disable melody format E1 feature
415 #if(L1_VOICE_MEMO == 1)
416 #define VOICE_MEMO 1 // Enable voice memorization feature
417 #else
418 #define VOICE_MEMO 0
419 #endif
420 #if (MELODY_E2)
421 #define FIR 1 // Enable FIR feature
422 #else
423 #define FIR 0 // Disable FIR feature
424 #endif
425 #define AUDIO_MODE 0 // Disable Audio mode feature
426 #endif
427
428
429 #else
430 #define KEYBEEP 0 // Enable keybeep feature
431 #define TONE 0 // Enable tone feature
432 #define MELODY_E1 0 // Enable melody format E1 feature
433 #define VOICE_MEMO 0 // Enable voice memorization feature
434 #define FIR 0 // Enable FIR feature
435 #define AUDIO_MODE 0 // Enable Audio mode feature
436 #endif
437
438 //FreeCalypso: LoCosto-ism below disabled
439 //#define L1_MIDI_BUFFER 1
440
441 /*
442 * L1_CPORT appears in the Leonardo L1 headers, and is enabled only for
443 * CHIPSET 12. The LoCosto version doesn't have it at all.
444 */
445 #define L1_CPORT 0
446
447 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2
448 #if (OP_RIV_AUDIO == 1)
449 #define L1_AUDIO_DRIVER (L1_VOICE_MEMO_AMR | L1_EXT_AUDIO_MGT | L1_MP3) // Riviera audio driver (only Voice Memo AMR is available)
450 #endif
451
452
453 // Vocoder selections
454 //-------------------
455
456 #define FR 1 // Full Rate
457 #define FR_HR 2 // Full Rate + Half Rate
458 #define FR_EFR 3 // Full Rate + Enhanced Full Rate
459 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate
460
461 // Standard (frequency plan) selections
462 //-------------------------------------
463 #if(L1_FF_MULTIBAND == 0) // std id is not used if multiband feature is enabled
464
465 #define GSM 1 // GSM900.
466 #define GSM_E 2 // GSM900 Extended.
467 #define PCS1900 3 // PCS1900.
468 #define DCS1800 4 // DCS1800.
469 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands)
470 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands)
471 #define GSM850 7 // GSM850 Band
472 #define DUAL_US 8 // PCS1900 + GSM850
473
474 #endif // L1_FF_MULTIBAND
475
476 /*------------------------------------*/
477 /* Power Management */
478 /*------------------------------------*/
479 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1
480
481 /*------------------------------------*/
482 /* BT Audio */
483 /*------------------------------------*/
484 #if ((L1_MP3 == 1) || (L1_AAC == 1))
485 #if (OP_L1_STANDALONE == 0)
486 #if((PSP_STANDALONE == 1) || (DRP_FW_BUILD == 1))
487 #define L1_BT_AUDIO 0
488 #else
489 #define L1_BT_AUDIO 1
490 #endif
491 #else
492 #define L1_BT_AUDIO 0
493 #endif
494 #endif
495 /*---------------------------------------------------------------------------*/
496 /* DSP configurations */
497 /* ------------------ */
498 /* DSP | FR| HR|EFR|14.4| SPEED |12LA68|12LA68 |4L32|AEC| MCU/DSP */
499 /* (version) | | | | | |POLE80|POLE112| |/NS| interface */
500 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
501 /* 0 (821) | x | | | | 39Mhz | x | | | | 1 */
502 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
503 /* 1 (830) | x | | | | 39Mhz | (1) | | x | | 1 */
504 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
505 /* 2 (912) | x | x | | | 58.5Mhz | x | | | | 2 */
506 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
507 /* 3 (10xx) | x | | x | x | 65Mhz | x | | | x | 3 */
508 /* ----------+---+---+---+----+---------+------+-------+----|---+---------- */
509 /* 4 (11xx) | x | x | x | x | 65Mhz | x | x (3)| | x | 3 */
510 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
511 /* 5 (830) | x | | | | 39Mhz | x | | | | 1 */
512 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
513 /* 6 (11xx) | x | x | x | x | 65Mhz | x | x (3)| |(2)| 3 */
514 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
515 /* */
516 /*(1) this version can be loaded on a 12LA68/POLE80 but the RIF/DL problem is*/
517 /* not corrected. */
518 /* */
519 /*(2) AEC is disabled at DSP level but L1 must be compiled with MCU/DSP */
520 /* interface which support AEC, therefore AEC is defined as 1. */
521 /* */
522 /*(3) Pole112 include RIF DL correction. No patch is needed if this one only */
523 /* include RIF/DL problem. */
524 /* */
525 /*---------------------------------------------------------------------------*/
526 #if (DSP == 16 || DSP == 17)
527
528 /* #define CLKMOD1 0x414e // ...
529 #define CLKMOD2 0x414e // ...65 Mips
530 #define CLKSTART 0x29 // ...65 Mips */
531
532 #define CLKMOD1 0x4006 // ...
533 #define CLKMOD2 0x4116 // ...65 Mips pll free
534 #define CLKSTART 0x29 // ...65 Mips
535
536 /* #define CLKMOD1 0x2116 //This settings force the DSP to never enteridle
537 #define CLKMOD2 0x2116 //In this case the PLL will be always on. 39 Mips
538 #define CLKSTART 0x25 // ...39 Mips */
539
540 #define VOC FR_HR_EFR // FR + HR + EFR.
541 #define DATA14_4 1 // No 14.4 data allowed.
542 #define AEC 1 // AEC/NS supported.
543 #define MAP 3
544 #define DSP_START 0x2000
545 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
546
547 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
548
549 /* DSP debug trace configuration */
550 /*-------------------------------*/
551 #if (MELODY_E2)
552 // In case of the melody E2 the DSP trace must be disable because the
553 // melody instrument waves are overlayed with DSP trace buffer
554
555 // DSP debug trace API buffer config
556 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
557 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
558 #else
559 // DSP debug trace API buffer config
560 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
561 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
562 #endif
563
564 #elif (DSP == 30) // First GPRS.
565 #define CLKMOD1 0x4006 // ...
566 #define CLKMOD2 0x4116 // ...65 Mips pll free
567 #define CLKSTART 0x29 // ...65 Mips
568
569 #define VOC FR_HR_EFR // FR + HR + EFR.
570 #define DATA14_4 1 // No 14.4 data allowed.
571 #define AEC 1 // AEC/NS not supported.
572 #define MAP 3
573 #define DSP_START 0x1F81
574 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
575 #define ULYSSE 0
576
577 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
578 #elif (DSP == 31) // ROM Code GPRS G0.
579 #define CLKMOD1 0x4006 // ...
580 #define CLKMOD2 0x4116 // ...65 Mips pll free
581 #define CLKSTART 0x29 // ...65 Mips
582
583 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
584 #define DATA14_4 1 // 14.4 data allowed.
585 #define AEC 1 // AEC/NS not supported.
586 #define MAP 3
587
588 #define DSP_START 0x8763
589
590 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
591 #define INSTALL_ADD_WITH_PATCH 0x1352 // Used to set gprs_install_address pointer
592
593 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
594 #define ULYSSE 0
595
596 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
597 #elif (DSP == 32) // ROM Code GPRS G1.
598 #define CLKMOD1 0x4006 // ...
599 #define CLKMOD2 0x4116 // ...65 Mips pll free
600 #define CLKSTART 0x29 // ...65 Mips
601
602 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
603 #define DATA14_4 1 // 14.4 data allowed.
604 #define AEC 1 // AEC/NS not supported.
605 #define MAP 3
606
607 #define DSP_START 0x8763
608
609 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
610
611 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
612 #define ULYSSE 0
613
614 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
615 #elif (DSP == 33) // ROM Code GPRS.
616 #define CLKMOD1 0x4006 // ...
617 #define CLKMOD2 0x4116 // ...65 Mips pll free
618 #define CLKSTART 0x29 // ...65 Mips
619 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
620 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
621 #define AEC 1 // AEC/NS not supported.
622 #define L1_NEW_AEC 1
623
624 #if ((L1_NEW_AEC) && (!AEC))
625 // First undef the flag to avoid warnings at compilation time
626 #undef AEC
627 #define AEC 1
628 #endif
629
630 #define MAP 3
631
632 #define DSP_START 0x7000
633
634 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
635
636 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
637 #define ULYSSE 0
638
639 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
640
641 #if (CODE_VERSION == NOT_SIMULATION)
642 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
643 // management.
644 // DSP_IDLE3 is not supported in simulation
645 #else
646 #define W_A_DSP_IDLE3 0
647 #endif
648
649 // DSP software work-around config
650 // bit0 - Work-around to support CRTG.
651 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
652 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
653 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
654
655 #if (ANALOG == 1) // OMEGA / NAUSICA
656 #define C_DSP_SW_WORK_AROUND 0x0006
657
658 #elif (ANALOG == 2) // IOTA
659 #define C_DSP_SW_WORK_AROUND 0x000E
660
661 #elif (ANALOG == 3) // SYREN
662 #define C_DSP_SW_WORK_AROUND 0x000E
663
664 #endif
665
666 /* DSP debug trace configuration */
667 /*-------------------------------*/
668 #if (MELODY_E2)
669 // In case of the melody E2 the DSP trace must be disable because the
670 // melody instrument waves are overlayed with DSP trace buffer
671
672 // DSP debug trace API buffer config
673 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
674 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
675
676 // DSP debug trace type config
677 // |<-------------- Features -------------->|<---------- Levels ----------->|
678 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
679 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
680
681 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
682 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
683 // Currently not supported !
684 #endif
685 #else
686 // DSP debug trace API buffer config
687 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
688 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
689
690 // DSP debug trace type config
691 // |<-------------- Features -------------->|<---------- Levels ----------->|
692 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
693 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
694
695 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
696 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
697 #endif
698 #endif
699 /* d_error_status */
700 /*-------------------------------*/
701
702 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
703 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
704
705 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
706 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852
707 #define DSP_DEBUG_GPRS_MASK 0x0f3d
708 #endif
709
710 #if DCO_ALGO
711 // DCO type of scheduling
712 #define C_CN_DCO_PARAM 0xA248
713 #endif
714
715 #elif (DSP == 34) // ROM Code GPRS AMR.
716 #define CLKMOD1 0x4006 // ...
717 #define CLKMOD2 0x4116 // ...65 Mips pll free
718 #define CLKSTART 0x29 // ...65 Mips
719 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
720 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
721 #define AEC 1 // AEC/NS not supported.
722 #define L1_NEW_AEC 1
723
724 #if ((L1_NEW_AEC) && (!AEC))
725 // First undef the flag to avoid warnings at compilation time
726 #undef AEC
727 #define AEC 1
728 #endif
729 #define MAP 3
730
731 #define DSP_START 0x7000
732
733 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
734
735 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
736 #define ULYSSE 0
737
738 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
739
740 #if (CODE_VERSION == NOT_SIMULATION)
741 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
742 // management.
743 // DSP_IDLE3 is not supported in simulation
744 #else
745 #define W_A_DSP_IDLE3 0
746 #endif
747
748 // DSP software work-around config
749 // bit0 - Work-around to support CRTG.
750 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
751 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
752 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
753 #if (ANALOG == 1) // OMEGA / NAUSICA
754 #define C_DSP_SW_WORK_AROUND 0x0006
755
756 #elif (ANALOG == 2) // IOTA
757 #define C_DSP_SW_WORK_AROUND 0x000E
758
759 #elif (ANALOG == 3) // SYREN
760 #define C_DSP_SW_WORK_AROUND 0x000E
761
762 #endif
763
764 /* DSP debug trace configuration */
765 /*-------------------------------*/
766 #if (MELODY_E2)
767 // In case of the melody E2 the DSP trace must be disable because the
768 // melody instrument waves are overlayed with DSP trace buffer
769
770 // DSP debug trace API buffer config
771 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
772 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
773
774 // DSP debug trace type config
775 // |<-------------- Features -------------->|<---------- Levels ----------->|
776 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
777 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
778
779 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
780 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
781 // Currently not supported !
782 #endif
783 #else
784 // DSP debug trace API buffer config
785 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
786 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
787
788 // DSP debug trace type config
789 // |<-------------- Features -------------->|<---------- Levels ----------->|
790 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
791 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
792
793 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
794 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
795 #endif
796
797 // AMR trace
798 #define C_AMR_TRACE_ID 55
799
800 #endif
801 /* d_error_status */
802 /*-------------------------------*/
803
804 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
805 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
806
807 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
808 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852
809 #define DSP_DEBUG_GPRS_MASK 0x0f3d
810 #endif
811
812 #elif (DSP == 35) // ROM Code GPRS AMR.
813 #define CLKMOD1 0x4006 // ...
814 #define CLKMOD2 0x4116 // ...65 Mips pll free
815 #define CLKSTART 0x29 // ...65 Mips
816 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
817 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
818 #define AEC 1 // AEC/NS not supported.
819 #define L1_NEW_AEC 1
820
821 #if ((L1_NEW_AEC) && (!AEC))
822 // First undef the flag to avoid warnings at compilation time
823 #undef AEC
824 #define AEC 1
825 #endif
826 #define MAP 3
827
828 #define FF_L1_TCH_VOCODER_CONTROL 1
829 #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
830
831 #define DSP_START 0x7000
832
833 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
834
835 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
836 #define ULYSSE 0
837
838 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
839
840 #if (CODE_VERSION == NOT_SIMULATION)
841 #if (CHIPSET != 12)
842 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
843 // management.
844 // DSP_IDLE3 is not supported in simulation
845 #else
846 #define W_A_DSP_IDLE3 0 // Work around to report DSP state to the ARM for Deep Sleep
847 // management.
848 // DSP_IDLE3 is not supported in simulation
849 #endif // CHIPSET 12
850 #else
851 #define W_A_DSP_IDLE3 0
852 #endif
853
854 #define W_A_DSP_PR20037 1
855
856 // DSP software work-around config
857 // bit0 - Work-around to support CRTG.
858 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
859 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
860 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
861 #if (ANALOG == 1) // OMEGA / NAUSICA
862 #define C_DSP_SW_WORK_AROUND 0x0006
863
864 #elif (ANALOG == 2) // IOTA
865 #define C_DSP_SW_WORK_AROUND 0x000E
866
867 #elif (ANALOG == 3) // SYREN
868 #define C_DSP_SW_WORK_AROUND 0x000E
869
870 #endif
871
872 /* DSP debug trace configuration */
873 /*-------------------------------*/
874 #if (MELODY_E2)
875 // In case of the melody E2 the DSP trace must be disable because the
876 // melody instrument waves are overlayed with DSP trace buffer
877
878 // DSP debug trace API buffer config
879 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
880 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
881
882 // DSP debug trace type config
883 // |<-------------- Features -------------->|<---------- Levels ----------->|
884 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
885 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
886
887 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
888 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
889 // Currently not supported !
890 #endif
891 #else
892 // DSP debug trace API buffer config
893 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
894 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
895
896 // DSP debug trace type config
897 // |<-------------- Features -------------->|<---------- Levels ----------->|
898 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
899 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst.
900
901 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
902 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
903 #endif
904
905 // AMR trace
906 #define C_AMR_TRACE_ID 55
907
908 #endif
909 /* d_error_status */
910 /*-------------------------------*/
911
912 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
913 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
914
915 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
916 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852
917 #define DSP_DEBUG_GPRS_MASK 0x0f3d
918 #endif
919 #elif (DSP >= 36) // ROM Code GPRS AMR.
920
921 #if ((L1_PCM_EXTRACTION) && (SPEECH_RECO))
922 #error "PCM extraction and Speech recognition not supported simultaneously"
923 #endif
924
925 #define CLKMOD1 0x4006 // ...
926 #define CLKMOD2 0x4116 // ...65 Mips pll free
927 #define CLKSTART 0x29 // ...65 Mips
928 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
929 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
930
931 #if 0
932 /* what we got with LoCosto L1 headers */
933 #define AEC 0 // AEC/NS not supported.
934 #define L1_NEW_AEC 0
935 #else
936 /* what we are used to from the Leonardo version */
937 #define AEC 1 // AEC/NS not supported.
938 #if (OP_RIV_AUDIO == 0)
939 #define L1_NEW_AEC 1
940 #else
941 // Available but not yet tuned with Riviera AUDIO
942 #define L1_NEW_AEC 0
943 #endif
944 #endif
945
946 #if ((L1_NEW_AEC) && (!AEC))
947 // First undef the flag to avoid warnings at compilation time
948 #undef AEC
949 #define AEC 1
950 #endif
951 #define MAP 3
952 #undef L1_AMR_NSYNC
953 #define L1_AMR_NSYNC 1
954 #define FF_L1_TCH_VOCODER_CONTROL 1
955 #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
956
957 #define DSP_START 0x7000
958
959 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
960
961 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
962 #define ULYSSE 0
963
964 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
965
966 #if (CODE_VERSION == NOT_SIMULATION)
967 #if ((CHIPSET != 12) && (CHIPSET != 15))
968 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
969 // management.
970 // DSP_IDLE3 is not supported in simulation
971 #else // CHIPSET 12
972 #define W_A_DSP_IDLE3 0 // Work around to report DSP state to the ARM for Deep Sleep
973 // management.
974 // DSP_IDLE3 is not supported in simulation
975 #endif // CHIPSET 12
976 #else // CODE_VERSION
977 #define W_A_DSP_IDLE3 0
978 #endif
979
980 #define W_A_DSP_PR20037 1
981
982 // DSP software work-around config
983 // bit0 - Work-around to support CRTG.
984 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
985 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
986 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
987 #if (ANALOG == 1) // OMEGA / NAUSICA
988 #define C_DSP_SW_WORK_AROUND 0x0006
989
990 #elif (ANALOG == 2) // IOTA
991 #define C_DSP_SW_WORK_AROUND 0x000E
992
993 #elif (ANALOG == 3) // SYREN
994 #define C_DSP_SW_WORK_AROUND 0x000E
995
996 #elif (ANALOG == 11) // TRITON
997 #define C_DSP_SW_WORK_AROUND 0x000E
998
999 #endif
1000
1001 /* DSP debug trace configuration */
1002 /*-------------------------------*/
1003 // Note:
1004 // In case of melody E2, MP3, AAC or Dyn Dwnld ACTIVITY the DSP trace is automatically disabled
1005 // because the melody instrument waves are overlayed with DSP trace buffer (supported since patch 7c20)
1006
1007 // DSP debug trace API buffer config
1008 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
1009 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
1010
1011 // DSP debug trace type config
1012 // |<-------------- Features -------------->|<---------- Levels ----------->|
1013 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
1014
1015 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)// C_DEBUG_TRACE_TYPE 0x0012 changed from 0x0054 for DSP load reduce
1016 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = KERNEL; Features = Timer, Burst, Buffer Header.
1017 #else
1018 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = KERNEL; Features = Timer, Burst, Buffer Header.
1019 #endif
1020
1021
1022 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
1023 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
1024 // Currently not supported !
1025 #endif
1026
1027 // AMR trace
1028 #define C_AMR_TRACE_ID 55
1029
1030
1031 /* d_error_status */
1032 /*-------------------------------*/
1033
1034 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
1035 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
1036
1037 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
1038 #define DSP_DEBUG_GSM_MASK 0x08BD // L1_MCU-SPR-15852
1039 #define DSP_DEBUG_GPRS_MASK 0x0f3d
1040 #endif
1041 #endif // DSP
1042
1043 /*------------------------------------*/
1044 /* Default value */
1045 /*------------------------------------*/
1046 #ifndef W_A_DSP1
1047 #define W_A_DSP1 0
1048 #endif
1049
1050 #ifndef DATA14_4
1051 #define DATA14_4 0
1052 #endif
1053
1054 #ifndef W_A_ITFORCE
1055 #define W_A_ITFORCE 0
1056 #endif
1057
1058 #ifndef W_A_DSP_IDLE3
1059 #define W_A_DSP_IDLE3 0
1060 #endif
1061
1062 #ifndef L1_NEW_AEC
1063 #define L1_NEW_AEC 0
1064 #endif
1065
1066 #ifndef DSP_DEBUG_TRACE_ENABLE
1067 #define DSP_DEBUG_TRACE_ENABLE 0
1068 #endif
1069
1070 #ifndef DEBUG_DEDIC_TCH_BLOCK_STAT
1071 #define DEBUG_DEDIC_TCH_BLOCK_STAT 0
1072 #endif
1073
1074 #ifndef D_ERROR_STATUS_TRACE_ENABLE
1075 #define D_ERROR_STATUS_TRACE_ENABLE 0
1076 #endif
1077
1078 #ifndef L1_GTT
1079 #define L1_GTT 0
1080 #define TTY_SYNC_MCU 0
1081 #define TTY_SYNC_MCU_2 0
1082 #define L1_GTT_FIFO_TEST_ATOMIC 0
1083 #define NEW_WKA_PATCH 0
1084 #define OPTIMISED 0
1085 #endif
1086
1087 #ifndef L1_AMR_NSYNC
1088 #define L1_AMR_NSYNC 0
1089 #endif
1090
1091 #ifndef FF_L1_TCH_VOCODER_CONTROL
1092 #define FF_L1_TCH_VOCODER_CONTROL 0
1093 #define W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0
1094 #define W_A_DSP_PR20037 0
1095 #endif
1096
1097
1098 /*------------------------------------*/
1099 /* Download */
1100 /*------------------------------------*/
1101
1102
1103 /* Possible values for the download status */
1104
1105 #define LEAD_READY 1
1106 #define BLOCK_READY 2
1107 #define PROGRAM_DONE 3
1108 #define PAGE_SELECTION 4
1109
1110
1111 /************************************/
1112 /* Options of compilation... */
1113 /************************************/
1114
1115 // Possible choice of hardware plateform.
1116 #define GEMINI 1 // GEMINI chip (rom dsp code)
1117 #define POLESTAR 2 // POLESTAR chip (no rom)
1118
1119 // Possible choice for DSP software setup.
1120 #define NO_DWNLD 0
1121 #define PATCH_DWNLD 1
1122 #define DSP_DWNLD 2
1123 #define PATCH_DSP_DWNLD 3
1124
1125 // MAC-S status reporting to Layer 1
1126 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1
1127
1128 /*
1129 * Possible choice for dll_dcch_downlink interface (with FN or without FN)
1130 * 0=without, 1=with FN parameter
1131 *
1132 * FreeCalypso note: the Leonardo version had this setting set to 1, i.e.,
1133 * 3 arguments to dll_dcch_downlink(). We don't have any source or even
1134 * header files for the Leonardo version of DL, but disassembly shows
1135 * that dll_dcch_downlink() does expect the FN parameter. The source for
1136 * DL from LoCosto also has a SEND_FN_TO_L2_IN_DCCH configurable setting,
1137 * and it is set to 1 in the dl.h local header. But here is the kicker:
1138 * the LoCosto version of this l1_confg.h header has the setting set to 0!
1139 *
1140 * I couldn't believe my eyes, so I disassembled the binary objects present
1141 * in the copy of the LoCosto source from scottn.us: yes, indeed that
1142 * code version contains an outright bug in that L1 does not pass the
1143 * 3rd argument (in ARM register r2), but DL expects it to be there.
1144 * (Thus DL is getting whatever "garbage" happens to be in r2 as the FN
1145 * parameter. I did not take the time to investigate what the downstream
1146 * effects are.)
1147 *
1148 * For FreeCalypso I'm setting SEND_FN_TO_L2_IN_DCCH to 1, both here
1149 * in L1 and in DL, where it was already set.
1150 */
1151 #define SEND_FN_TO_L2_IN_DCCH 1
1152
1153 /*
1154 * FreeCalypso change: I'm disabling L1_CHECK_COMPATIBLE (a new "feature"
1155 * added with LoCosto version of L1, not present in the Leonardo version)
1156 * because l1_async.c fails to compile with it enabled. Examination of
1157 * the code reveals that this "compatibility check" involves things
1158 * which we won't be enabling any time soon, if ever.
1159 */
1160 #define L1_CHECK_COMPATIBLE 0 //Check L1A message compatiblity
1161
1162 //---------------------------------------------------------------------------------
1163
1164 #endif /* __L1_CONFG_H__ */