FreeCalypso > hg > freecalypso-citrine
comparison L1/include/l1_defty.h @ 0:75a11d740a02
initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 09 Jun 2016 00:02:41 +0000 |
parents | |
children | f93dab57b032 |
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-1:000000000000 | 0:75a11d740a02 |
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1 /************* Revision Controle System Header ************* | |
2 * GSM Layer 1 software | |
3 * L1_DEFTY.H | |
4 * | |
5 * Filename l1_defty.h | |
6 * Copyright 2003 (C) Texas Instruments | |
7 * | |
8 ************* Revision Controle System Header *************/ | |
9 | |
10 #if (L1_RF_KBD_FIX == 1) | |
11 #include "l1_macro.h" | |
12 | |
13 #if(OP_L1_STANDALONE == 0) | |
14 #include "kpd/kpd_scan_functions.h" | |
15 #endif | |
16 | |
17 #endif | |
18 | |
19 #include "../../gpf/inc/cust_os.h" | |
20 #if(L1_DYN_DSP_DWNLD == 1) | |
21 #include "../dyn_dwl_include/l1_dyn_dwl_defty.h" | |
22 #endif | |
23 #if (L1_AAC == 1) //ADDED for AAC -sajal | |
24 #include "l1aac_defty.h" | |
25 #endif | |
26 | |
27 typedef struct | |
28 { | |
29 UWORD8 enable; // activation of FACCH test | |
30 UWORD8 period; // period of FACCH test | |
31 } | |
32 T_FACCH_TEST_PARAMS; | |
33 | |
34 typedef struct | |
35 { | |
36 UWORD16 modulus; | |
37 UWORD16 relative_position; | |
38 } | |
39 T_BCCHS_SCHEDULE; | |
40 | |
41 typedef struct | |
42 { | |
43 UWORD8 schedule_array_size; | |
44 T_BCCHS_SCHEDULE schedule_array[10]; | |
45 } | |
46 T_BCCHS; | |
47 | |
48 typedef struct | |
49 { | |
50 UWORD8 srr; /* SACCH Repetition Request - UL */ | |
51 UWORD8 sro; /* SACCH Repetition Order - DL */ | |
52 UWORD8 buffer[22+1]; /* New uplink buffer to save the repetition block data in case of retransmission */ | |
53 BOOL buffer_empty; /* It is equal to 1 if the UL repetion buffer should be empty otherwise 0 */ | |
54 } | |
55 T_REPEAT_SACCH; | |
56 | |
57 typedef struct | |
58 { | |
59 API buffer[12]; /* New buffer to save the DL data for comparison */ | |
60 UWORD8 buffer_empty; /* To indicate the saved buffer */ | |
61 }T_REPEAT_FACCH_PIPELINE; | |
62 typedef struct | |
63 { | |
64 T_REPEAT_FACCH_PIPELINE pipeline[2]; | |
65 UWORD8 counter; | |
66 UWORD8 counter_candidate; | |
67 } T_REPEAT_FACCH; | |
68 | |
69 typedef struct | |
70 { | |
71 BOOL status; | |
72 UWORD16 radio_freq; | |
73 UWORD32 fn_offset; | |
74 UWORD32 time_alignmt; | |
75 UWORD8 sb26_attempt; | |
76 UWORD8 tsc; | |
77 UWORD16 bcch_blks_req; | |
78 UWORD8 timing_validity; | |
79 UWORD8 search_mode; | |
80 UWORD8 gprs_priority; | |
81 UWORD8 sb26_offset; // Set to 1 when SB26 RX win is entirely in frame 25. | |
82 #if (L1_12NEIGH ==1) | |
83 UWORD32 fn_offset_mem; | |
84 UWORD32 time_alignmt_mem; | |
85 #endif // (L1_12NEIGH ==1) | |
86 #if ((REL99 == 1) && ((FF_BHO == 1) || (FF_RTD == 1))) | |
87 UWORD8 nb_fb_attempt ; | |
88 UWORD8 fb26_position; // used for RTD feature | |
89 #endif | |
90 } | |
91 T_NCELL_SINGLE; | |
92 | |
93 #if ((REL99 == 1) && (FF_BHO == 1)) | |
94 typedef struct | |
95 { | |
96 UWORD8 fb_found_attempt; | |
97 UWORD16 radio_freq; | |
98 UWORD32 fn_offset; | |
99 UWORD32 time_alignmt; | |
100 UWORD32 fb_toa; | |
101 } | |
102 T_BHO_PARAM; | |
103 #endif // #if ((REL99 == 1) && (FF_BHO == 1)) | |
104 | |
105 typedef struct | |
106 { | |
107 UWORD8 active_neigh_id_norm; | |
108 UWORD8 active_neigh_tc_norm; | |
109 UWORD8 active_neigh_id_top; | |
110 UWORD8 active_neigh_tc_top; | |
111 UWORD8 current_list_size; | |
112 T_NCELL_SINGLE list[6]; | |
113 } | |
114 T_BCCHN_LIST; | |
115 | |
116 typedef struct | |
117 { | |
118 UWORD8 active_fb_id; | |
119 UWORD8 active_sbconf_id; | |
120 UWORD8 active_sb_id; | |
121 UWORD8 current_list_size; | |
122 UWORD8 first_in_list; //point at oldest element in list. Used when parsing the list. | |
123 #if (L1_EOTD==1) | |
124 #if L1_EOTD_QBIT_ACC | |
125 // Store serving fn_offset and time_alignmt, so that they can be tracked | |
126 // independently. | |
127 UWORD32 serv_fn_offset; | |
128 UWORD32 serv_time_alignmt; | |
129 #endif | |
130 // Need to track any TOA updates in dedicated mode else | |
131 // QB errors are introduced in the results... | |
132 | |
133 UWORD8 eotd_toa_phase; | |
134 WORD32 eotd_toa_tracking; | |
135 WORD32 eotd_cache_toa_tracking; | |
136 | |
137 UWORD8 eotd_meas_session; | |
138 UWORD32 fn_sb_serv; // for methods 1 & 2 | |
139 UWORD32 ta_sb_serv; // for methods 1 & 2 | |
140 WORD32 teotdS; // for method 2 only | |
141 UWORD32 fn_offset_serv; // for method 2 only | |
142 #endif | |
143 #if (L1_12NEIGH==1) | |
144 T_NCELL_SINGLE list[NBR_NEIGHBOURS+1]; // 1 place (13th) for S.C in EOTD. | |
145 #else | |
146 T_NCELL_SINGLE list[6]; | |
147 #endif | |
148 } | |
149 T_NSYNC_LIST; | |
150 | |
151 typedef struct | |
152 { | |
153 UWORD8 cbch_state; | |
154 UWORD32 starting_fn; | |
155 UWORD32 first_block[48]; | |
156 UWORD8 cbch_num; | |
157 UWORD8 schedule_length; | |
158 UWORD8 next; | |
159 WORD32 start_continuous_fn; | |
160 } | |
161 T_CBCH_HEAD_SCHEDULE; | |
162 | |
163 typedef struct | |
164 { | |
165 UWORD8 cbch_num; | |
166 UWORD8 next; | |
167 UWORD32 start_fn[6]; | |
168 } | |
169 T_CBCH_INFO_SCHEDULE; | |
170 | |
171 /*=========================================================================*/ | |
172 /* Moved type definitions from Debis files. */ | |
173 /*=========================================================================*/ | |
174 #if (AMR == 1) | |
175 // AMR ver 1.0 parameters | |
176 typedef struct | |
177 { | |
178 BOOL noise_suppression_bit; | |
179 BOOL initial_codec_mode_indicator; | |
180 UWORD8 initial_codec_mode; | |
181 UWORD8 active_codec_set; | |
182 UWORD8 threshold[3]; | |
183 UWORD8 hysteresis[3]; | |
184 } | |
185 T_AMR_CONFIGURATION; | |
186 #endif | |
187 | |
188 typedef struct | |
189 { | |
190 #if(L1_A5_3 == 1 && OP_L1_STANDALONE != 1) | |
191 UWORD8 A[15+1]; | |
192 #else | |
193 UWORD8 A[7+1]; | |
194 #endif | |
195 } | |
196 T_ENCRYPTION_KEY; | |
197 | |
198 typedef struct | |
199 { | |
200 UWORD8 A[22+1]; | |
201 } | |
202 T_RADIO_FRAME; | |
203 | |
204 typedef struct | |
205 { | |
206 UWORD8 n32; | |
207 UWORD8 n51; | |
208 UWORD8 n26; | |
209 } | |
210 T_SHORT_FRAME_NUMBER; | |
211 | |
212 typedef struct | |
213 { | |
214 UWORD16 A[31+1]; | |
215 } | |
216 T_CHAN_LIST; | |
217 | |
218 typedef struct | |
219 { | |
220 UWORD16 num_of_chans; | |
221 T_CHAN_LIST chan_number; | |
222 } | |
223 T_BCCH_LIST; | |
224 | |
225 typedef struct | |
226 { | |
227 UWORD16 rf_chan_num; | |
228 UWORD8 l2_channel_type; | |
229 UWORD8 error_cause; | |
230 T_RADIO_FRAME l2_frame; | |
231 UWORD8 bsic; | |
232 UWORD8 tc; | |
233 } | |
234 T_PH_DATA_IND; | |
235 | |
236 typedef struct | |
237 { | |
238 UWORD16 A[63+1]; | |
239 } | |
240 T_MA_FIELD; | |
241 | |
242 typedef struct | |
243 { | |
244 UWORD16 rf_chan_cnt; | |
245 T_MA_FIELD rf_chan_no; | |
246 } | |
247 T_MOBILE_ALLOCATION; | |
248 | |
249 typedef struct | |
250 { | |
251 BOOL start_time_present; | |
252 T_SHORT_FRAME_NUMBER start_time; | |
253 } | |
254 T_STARTING_TIME; | |
255 | |
256 typedef struct | |
257 { | |
258 UWORD16 radio_freq_no; | |
259 WORD8 rxlev; | |
260 } | |
261 T_RXLEV_MEAS; | |
262 | |
263 typedef struct | |
264 { | |
265 UWORD8 maio; | |
266 UWORD8 hsn; | |
267 } | |
268 T_HOPPING_RF; | |
269 | |
270 typedef struct | |
271 { | |
272 UWORD16 radio_freq; | |
273 } | |
274 T_SINGLE_RF; | |
275 | |
276 typedef union | |
277 { | |
278 T_SINGLE_RF single_rf; | |
279 T_HOPPING_RF hopping_rf; | |
280 } | |
281 T_CHN_SEL_CHOICE; | |
282 | |
283 typedef struct | |
284 { | |
285 BOOL h; | |
286 T_CHN_SEL_CHOICE rf_channel; | |
287 } | |
288 T_CHN_SEL; | |
289 | |
290 typedef struct | |
291 { | |
292 T_CHN_SEL chan_sel; | |
293 UWORD8 channel_type; | |
294 UWORD8 subchannel; | |
295 UWORD8 timeslot_no; | |
296 UWORD8 tsc; | |
297 } | |
298 T_CHANNEL_DESCRIPTION; | |
299 | |
300 typedef struct | |
301 { | |
302 UWORD8 ncc; | |
303 UWORD8 bcc; | |
304 UWORD16 bcch_carrier; | |
305 } | |
306 T_CELL_DESC; | |
307 | |
308 typedef struct | |
309 { | |
310 T_CELL_DESC cell_description; | |
311 T_CHANNEL_DESCRIPTION channel_desc_1; | |
312 UWORD8 channel_mode_1; | |
313 T_STARTING_TIME starting_time; | |
314 UWORD8 ho_acc; | |
315 UWORD8 txpwr; | |
316 BOOL report_time_diff; | |
317 T_MOBILE_ALLOCATION frequency_list; | |
318 T_CHANNEL_DESCRIPTION channel_desc_2; | |
319 UWORD8 channel_mode_2; | |
320 T_MOBILE_ALLOCATION frequency_list_bef_sti; | |
321 T_CHANNEL_DESCRIPTION channel_desc_1_bef_sti; | |
322 T_CHANNEL_DESCRIPTION channel_desc_2_bef_sti; | |
323 BOOL cipher_mode; | |
324 UWORD8 a5_algorithm; | |
325 } | |
326 T_HO_PARAMS; | |
327 | |
328 typedef struct | |
329 { | |
330 UWORD8 subchannel; | |
331 UWORD8 channel_mode; | |
332 #if (AMR == 1) | |
333 T_AMR_CONFIGURATION amr_configuration; | |
334 #endif | |
335 } | |
336 T_MPHC_CHANNEL_MODE_MODIFY_REQ; | |
337 | |
338 typedef struct | |
339 { | |
340 UWORD8 sub_channel; | |
341 UWORD8 frame_erasure; | |
342 } | |
343 T_OML1_CLOSE_TCH_LOOP_REQ; | |
344 | |
345 typedef struct | |
346 { | |
347 #if (defined _WINDOWS && (OP_RIV_AUDIO == 1)) | |
348 T_RV_HDR header; | |
349 #endif | |
350 UWORD8 tested_device; | |
351 } | |
352 T_OML1_START_DAI_TEST_REQ; | |
353 | |
354 /***********************************************************/ | |
355 /* Type definitions for DEBUG... */ | |
356 /***********************************************************/ | |
357 typedef struct // translate string in int and int in string | |
358 { | |
359 CHAR *message; | |
360 WORD32 SignalCode; | |
361 WORD32 size; | |
362 } | |
363 MSG_DEBUG; | |
364 | |
365 typedef struct // translate string in int and int in string | |
366 { | |
367 CHAR *name; | |
368 } | |
369 TASK_TRACE; | |
370 | |
371 /***********************************************************/ | |
372 /* Type definitions for data structures used for MFTAB */ | |
373 /* managment... */ | |
374 /***********************************************************/ | |
375 typedef struct | |
376 { | |
377 void (*fct_ptr)(UWORD8,UWORD8); | |
378 CHAR param1; | |
379 CHAR param2; | |
380 } | |
381 T_FCT; | |
382 | |
383 typedef struct | |
384 { | |
385 T_FCT fct[L1_MAX_FCT]; | |
386 } | |
387 T_FRM; | |
388 | |
389 typedef struct | |
390 { | |
391 T_FRM frmlst[MFTAB_SIZE]; | |
392 } | |
393 T_MFTAB; | |
394 | |
395 typedef struct | |
396 { | |
397 const T_FCT *address; | |
398 UWORD8 size; | |
399 } | |
400 T_TASK_MFTAB; | |
401 | |
402 | |
403 #if (GSM_IDLE_RAM != 0) | |
404 typedef struct | |
405 { | |
406 BOOL l1s_full_exec; | |
407 BOOL trff_ctrl_enable_cause_int; | |
408 WORD32 hw_timer; | |
409 WORD32 os_load; | |
410 UWORD32 sleep_mode; | |
411 | |
412 #if GSM_IDLE_RAM_DEBUG | |
413 UWORD32 killing_flash_access; | |
414 UWORD32 killing_ext_ram_access; | |
415 UWORD32 irq; | |
416 UWORD32 fiq; | |
417 UWORD32 nb_inth; | |
418 | |
419 #if (CHIPSET == 10) && (OP_WCP == 1) | |
420 UWORD16 TC_true_control; | |
421 #endif // CHIPSET && OP_WCP | |
422 #endif // GSM_IDLE_RAM_DEBUG | |
423 UWORD32 task_bitmap_idle_ram[SIZE_TAB_L1S_MONITOR]; | |
424 UWORD32 mem_task_bitmap_idle_ram[SIZE_TAB_L1S_MONITOR]; | |
425 } | |
426 T_L1S_GSM_IDLE_INTRAM; | |
427 #endif // GSM_IDLE_RAM | |
428 | |
429 | |
430 /***********************************************************/ | |
431 /* TPU controle register components definition. */ | |
432 /***********************************************************/ | |
433 | |
434 #if (CODE_VERSION==SIMULATION) | |
435 typedef struct // contents of REG_CMD register | |
436 { | |
437 unsigned int tpu_reset_bit : 1; // TPU_RESET bit : ON (reset TPU) | |
438 unsigned int tpu_pag_bit : 1; // TPU_PAG bit : 0 (page 0) | |
439 unsigned int tpu_enb_bit : 1; // TPU_ENB bit : ON (TPU commun.int.) | |
440 unsigned int dsp_pag_bit : 1; // DSP_PAG bit : 0 (page 0) | |
441 unsigned int dsp_enb_bit : 1; // DSP_ENB bit : ON (DSP commun.int.) | |
442 unsigned int tpu_stat_bit : 1; // TPU_STAT bit : ON (if TPU active) OFF (if TPU in IDLE) | |
443 unsigned int tpu_idle_bit : 1; // TPU_IDLE bit : ON (force IDLE mode) | |
444 } | |
445 T_reg_cmd; // Rem: we must keep "unsigned int" type for bitmap. | |
446 #else | |
447 typedef struct // contents of REG_CMD register | |
448 { | |
449 unsigned int tpu_reset_bit : 1; // TPU_RESET bit : ON (reset TPU) | |
450 unsigned int tpu_pag_bit : 1; // TPU_PAG bit : 0 (page 0) | |
451 unsigned int tpu_enb_bit : 1; // TPU_ENB bit : ON (TPU commun.int.) | |
452 unsigned int unused_1 : 1; // | |
453 unsigned int dsp_enb_bit : 1; // DSP_ENB bit : ON (DSP commun.int.) | |
454 unsigned int unused_2 : 1; // | |
455 unsigned int unused_3 : 1; // | |
456 unsigned int tsp_reset_bit : 1; // TSP_RESET bit : ON (reset TSP) | |
457 unsigned int tpu_idle_bit : 1; // TPU_IDLE bit : ON (force IDLE mode) | |
458 unsigned int tup_wait_bit : 1; // TPU_WAIT bit : ON (TPU ready) | |
459 unsigned int tpu_ck_enb_bit: 1; // TPU_CLK bit : ON (TPU clock on) | |
460 } | |
461 T_reg_cmd; | |
462 #endif | |
463 /***********************************************************/ | |
464 /* */ | |
465 /* Data structure for global info components. */ | |
466 /* */ | |
467 /***********************************************************/ | |
468 | |
469 typedef struct | |
470 { | |
471 API d_task_d; // 0x0800 (0) Downlink task command. | |
472 API d_burst_d; // 0x0801 (1) Downlink burst identifier. | |
473 API d_task_u; // 0x0802 (2) Uplink task command. | |
474 API d_burst_u; // 0x0803 (3) Uplink burst identifier. | |
475 API d_task_md; // 0x0804 (4) Downlink Monitoring (FB/SB) command. | |
476 #if (DSP >= 33) | |
477 API d_background; // 0x0805 (5) Background tasks | |
478 #else | |
479 API d_reserved; // 0x0805 (5) Reserved | |
480 #endif | |
481 API d_debug; // 0x0806 (6) Debug/Acknowledge/general purpose word. | |
482 API d_task_ra; // 0x0807 (7) RA task command. | |
483 API d_fn; // 0x0808 (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only. | |
484 // bit [0..7] -> b_fn_report, FN in the normalized reporting period. | |
485 // bit [8..15] -> b_fn_sid, FN % 104, used for SID positionning. | |
486 API d_ctrl_tch; // 0x0809 (9) Tch channel description. | |
487 // bit [0..3] -> b_chan_mode, channel mode. | |
488 // bit [4..5] -> b_chan_type, channel type. | |
489 // bit [6] -> reset SACCH | |
490 // bit [7] -> vocoder O | |
491 // bit [8] -> b_sync_tch_ul, synchro. TCH/UL. | |
492 // bit [9] -> b_sync_tch_dl, synchro. TCH/DL. | |
493 // bit [10] -> b_stop_tch_ul, stop TCH/UL. | |
494 // bit [11] -> b_stop_tch_dl, stop TCH/DL. | |
495 // bit [12.13] -> b_tch_loop, tch loops A/B/C. | |
496 API hole; // 0x080A (10) unused hole. | |
497 | |
498 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11)) | |
499 API d_ctrl_abb; // 0x080B (11) Bit field indicating the analog baseband register to send. | |
500 // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB | |
501 // bit [1.2] -> unused | |
502 // bit [3] -> b_apcdel: delays-register in NDB | |
503 // bit [4] -> b_afc: freq control register in DB | |
504 // bit [5..15] -> unused | |
505 #endif | |
506 API a_a5fn[2]; // 0x080C (12..13) Encryption Frame number. | |
507 // word 0, bit [0..4] -> T2. | |
508 // word 0, bit [5..10] -> T3. | |
509 // word 1, bit [0..11] -> T1. | |
510 API d_power_ctl; // 0x080E (14) Power level control. | |
511 API d_afc; // 0x080F (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb"). | |
512 API d_ctrl_system; // 0x0810 (16) Controle Register for RESET/RESUME. | |
513 // bit [0..2] -> b_tsq, training sequence. | |
514 // bit [3] -> b_bcch_freq_ind, BCCH frequency indication. | |
515 // bit [15] -> b_task_abort, DSP task abort command. | |
516 // bit [4] -> B_SWH_APPLY_WHITENING, Apply whitening. | |
517 //#if (((DSP == 36)||(DSP == 37)||(DSP == 38) || (DSP == 39))) | |
518 // API d_swh_ApplyWhitening_db; // 0x0811 SWH Whitening Activation Flag | |
519 //#endif | |
520 } | |
521 T_DB_MCU_TO_DSP; | |
522 | |
523 #if (DSP == 38) || (DSP == 39) | |
524 // DB COMMON to GSM and GPRS | |
525 typedef struct | |
526 { | |
527 API d_dco_algo_ctrl_nb; // DRP DCO enable/disable for normal burst | |
528 API d_dco_algo_ctrl_sb; // DRP DCO enable/disable for synchro burst | |
529 API d_dco_algo_ctrl_pw; // DRP DCO enable/disable for power burst | |
530 API d_swh_ctrl_db; | |
531 API d_fast_paging_ctrl; | |
532 } | |
533 T_DB_COMMON_MCU_TO_DSP; | |
534 #endif // DSP == 38 || DSP == 39 | |
535 | |
536 /* DSP CPU load measurement */ | |
537 #if (DSP == 38) || (DSP == 39) | |
538 // DB COMMON to GSM and GPRS | |
539 typedef struct | |
540 { | |
541 API d_dsp_fgd_tsk_tim0; | |
542 API d_dsp_fgd_tsk_tim1; | |
543 API d_tdma_dsp_fn; | |
544 API d_dsp_page_read; | |
545 } | |
546 T_DB_MCU_TO_DSP_CPU_LOAD; | |
547 #endif // DSP == 38 || DSP == 39 | |
548 | |
549 typedef struct | |
550 { | |
551 API d_task_d; // 0x0828 (0) Downlink task command. | |
552 API d_burst_d; // 0x0829 (1) Downlink burst identifier. | |
553 API d_task_u; // 0x082A (2) Uplink task command. | |
554 API d_burst_u; // 0x082B (3) Uplink burst identifier. | |
555 API d_task_md; // 0x082C (4) Downlink Monitoring (FB/SB) task command. | |
556 #if (DSP >= 33) | |
557 API d_background; // 0x082D (5) Background tasks | |
558 #else | |
559 API d_reserved; // 0x082D (5) Reserved | |
560 #endif | |
561 API d_debug; // 0x082E (6) Debug/Acknowledge/general purpose word. | |
562 API d_task_ra; // 0x082F (7) RA task command. | |
563 | |
564 #if (DSP >= 33) | |
565 API a_serv_demod[4]; // 0x0830 ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR). | |
566 API a_pm[3]; // 0x0834 (12..14) Power measurement results, array of 3 words. | |
567 API a_sch[5]; // 0x0837 (15..19) Header + SB information, array of 5 words. | |
568 #else | |
569 API a_pm[3]; // ( 8..10) Power measurement results, array of 3 words. | |
570 API a_serv_demod[4]; // (11..14) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR). | |
571 API a_sch[5]; // (15..19) Header + SB information, array of 5 words. | |
572 #endif | |
573 } | |
574 T_DB_DSP_TO_MCU; | |
575 | |
576 #if (DSP == 38) || (DSP == 39) | |
577 typedef struct | |
578 { | |
579 // MISC Tasks | |
580 API d_dsp_page; // 0x08D4 | |
581 | |
582 // DSP status returned (DSP --> MCU). | |
583 API d_error_status; // 0x08D5 | |
584 | |
585 // RIF control (MCU -> DSP). // following is removed for Locosto | |
586 API d_spcx_rif_hole; // 0x08D6 | |
587 | |
588 | |
589 API d_tch_mode; // 0x08D7 TCH mode register. | |
590 // bit [0..1] -> b_dai_mode. | |
591 // bit [2] -> b_dtx. | |
592 | |
593 API d_debug1; // 0x08D8 bit 0 at 1 enable dsp f_tx delay for Omega | |
594 | |
595 API d_dsp_test; // 0x08D9 | |
596 | |
597 // Words dedicated to Software version (DSP code + Patch) | |
598 API d_version_number1; // 0x08DA | |
599 API d_version_number2; // 0x08DB | |
600 | |
601 API d_debug_ptr; // 0x08DC | |
602 API d_debug_bk; // 0x08DD | |
603 | |
604 API d_pll_config; // 0x08DE | |
605 | |
606 // GSM/GPRS DSP Debug trace support | |
607 API p_debug_buffer; // 0x08DF | |
608 API d_debug_buffer_size; // 0x08E0 | |
609 API d_debug_trace_type; // 0x08E1 | |
610 | |
611 #if (W_A_DSP_IDLE3 == 1) | |
612 // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3. | |
613 API d_dsp_state; // 0x08E2 | |
614 // 5 words are reserved for any possible mapping modification | |
615 API d_hole1_ndb[2]; // 0x08E3 | |
616 #else | |
617 // 6 words are reserved for any possible mapping modification | |
618 API d_hole1_ndb[3]; | |
619 #endif | |
620 | |
621 #if (AMR == 1) | |
622 API p_debug_amr; // 0x08E5??? DSP doc says reserved | |
623 #else | |
624 API d_hole_debug_amr; | |
625 #endif | |
626 | |
627 API d_dsp_iq_scaling_factor; // 0x08E6 | |
628 API d_mcsi_select; // 0x08E7 | |
629 | |
630 // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations | |
631 API d_apcdel1_bis; // 0x08E8 | |
632 API d_apcdel2_bis; | |
633 // New registers due to IOTA analog base band | |
634 API d_apcdel2; | |
635 | |
636 | |
637 API d_vbctrl2_hole; // 0x08EB | |
638 API d_bulgcal_hole; // 0x08EC | |
639 // Analog Based Band - removed in ROM 38 | |
640 API d_afcctladd_hole; // 0x08ED | |
641 API d_vbuctrl_hole; // 0x08EE - removed in ROM38 | |
642 API d_vbdctrl_hole; // 0x08EF - removed in ROM38 | |
643 | |
644 API d_apcdel1; // 0x08F0 | |
645 // New Variables Added due to the APC Switch | |
646 // But for when DSP is in Idle3 all writes from MCU to APC are routed via DSP | |
647 API d_apclev; // APCLEV - 0x08F1 (In ROM36 - apcoff ) | |
648 // NOTE: Used Only in Test mode | |
649 // Only when l1_config.tmode.rf_params.down_up == TMODE_UPLINK; | |
650 API d_apcctrl2; // APCCTRL2 - 0x08F2 (In ROM36 - bulioff) | |
651 API d_bulqoff_hole; // 0x08F3 | |
652 API d_dai_onoff; // 0x08F4 | |
653 API d_auxdac_hole; // 0x08F5 | |
654 | |
655 API d_vbctrl_hole; // 0x08F6 - removed in ROM38 | |
656 | |
657 API d_bbctrl_hole; // 0x08F7 - removed in ROM38 | |
658 | |
659 // Monitoring tasks control (MCU <- DSP) | |
660 // FB task | |
661 API d_fb_det; // 0x08F8 FB detection result. (1 for FOUND). | |
662 API d_fb_mode; // Mode for FB detection algorithm. | |
663 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR). | |
664 | |
665 // SB Task | |
666 API a_sch26[5]; // 0x08FE Header + SB information, array of 5 words. | |
667 | |
668 API d_audio_gain_ul; // 0x0903 | |
669 API d_audio_gain_dl; // 0x0904 | |
670 | |
671 // Controller of the melody E2 audio compressor - removed in ROM 38 | |
672 API d_audio_compressor_ctrl_hole; // 0x0905 - removed in ROM37,38 | |
673 | |
674 // AUDIO module | |
675 API d_audio_init; // 0x0906 | |
676 API d_audio_status; // | |
677 | |
678 // Audio tasks | |
679 // TONES (MCU -> DSP) | |
680 API d_toneskb_init; | |
681 API d_toneskb_status; | |
682 API d_k_x1_t0; | |
683 API d_k_x1_t1; | |
684 API d_k_x1_t2; | |
685 API d_pe_rep; | |
686 API d_pe_off; | |
687 API d_se_off; | |
688 API d_bu_off; // 0x0910 | |
689 API d_t0_on; | |
690 API d_t0_off; | |
691 API d_t1_on; | |
692 API d_t1_off; | |
693 API d_t2_on; | |
694 API d_t2_off; | |
695 API d_k_x1_kt0; | |
696 API d_k_x1_kt1; | |
697 API d_dur_kb; | |
698 API d_shiftdl; | |
699 API d_shiftul; // 0x091B | |
700 | |
701 API d_aec_18_hole; // 0x091C | |
702 | |
703 API d_es_level_api; | |
704 API d_mu_api; | |
705 | |
706 // Melody Ringer module | |
707 API d_melo_osc_used; // 0x091F | |
708 API d_melo_osc_active; // 0x0920 | |
709 API a_melo_note0[4]; | |
710 API a_melo_note1[4]; | |
711 API a_melo_note2[4]; | |
712 API a_melo_note3[4]; | |
713 API a_melo_note4[4]; | |
714 API a_melo_note5[4]; | |
715 API a_melo_note6[4]; | |
716 API a_melo_note7[4]; | |
717 | |
718 // selection of the melody format | |
719 API d_melody_selection; // 0x0941 | |
720 | |
721 // Holes due to the format melody E1 | |
722 API a_melo_holes[3]; | |
723 | |
724 // Speech Recognition module - Removed in ROM38 | |
725 API d_sr_holes[19]; // 0x0945 | |
726 | |
727 // Audio buffer | |
728 API a_dd_1[22]; // 0x0958 Header + DATA traffic downlink information, sub. chan. 1. | |
729 API a_du_1[22]; // 0x096E Header + DATA traffic uplink information, sub. chan. 1. | |
730 | |
731 // V42bis module | |
732 API d_v42b_nego0; // 0x0984 | |
733 API d_v42b_nego1; | |
734 API d_v42b_control; | |
735 API d_v42b_ratio_ind; | |
736 API d_mcu_control; | |
737 API d_mcu_control_sema; | |
738 | |
739 // Background tasks | |
740 API d_background_enable; // 0x098A | |
741 API d_background_abort; | |
742 API d_background_state; | |
743 API d_max_background; | |
744 API a_background_tasks[16]; // 0x098E | |
745 API a_back_task_io[16]; //0x099E | |
746 | |
747 // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory) | |
748 API d_gea_mode_ovly_hole; // 0x09AE | |
749 API a_gea_kc_ovly_hole[4]; // 0x09AF | |
750 | |
751 API d_hole3_ndb[6]; //0x09B3 | |
752 API d_dsp_aud_hint_flag; // 0x09B9; | |
753 | |
754 // word used for the init of USF threshold | |
755 API d_thr_usf_detect; // 0x09BA | |
756 | |
757 // Encryption module | |
758 API d_a5mode; // Encryption Mode. | |
759 | |
760 API d_sched_mode_gprs_ovly; // 0x09Bc | |
761 #if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1) | |
762 API d_hole1_fast_ndb[1]; // 0x09BD; | |
763 API d_dsp_hint_flag; // 0x09BE; //used for fast usf and fast dtx and other dyn dwn | |
764 // 6 words are reserved for any possible mapping modification | |
765 #if FF_L1_IT_DSP_DTX | |
766 API d_fast_dtx_enable;//used for enabling fast dtx- 0x09BF | |
767 API d_fast_dtx_enc_data;//fast usf written by DSP to indicate tx data is there or not- 0x09C0 | |
768 #else // FF_L1_IT_DSP_DTX | |
769 API d_hole3_fast_ndb[2]; // 0x09BF | |
770 #endif // FF_L1_IT_DSP_USF | |
771 #if (FF_L1_FAST_DECODING == 1) | |
772 API d_fast_paging_data; // 0x9C1 | |
773 #else | |
774 API d_hole_fast_paging_ndb; | |
775 #endif /* FF_L1_FAST_DECODING*/ | |
776 #else | |
777 // 7 words are reserved for any possible mapping modification | |
778 API d_hole4_ndb[5]; // 0x09BD | |
779 #endif | |
780 | |
781 // Ramp definition for Omega device | |
782 API a_ramp_hole[16]; //0x09C2 | |
783 | |
784 // CCCH/SACCH downlink information...(!!) | |
785 API a_cd[15]; //0x09D2 Header + CCCH/SACCH downlink information. | |
786 | |
787 // FACCH downlink information........(!!) | |
788 API a_fd[15]; // 0x09E1 Header + FACCH downlink information. | |
789 | |
790 // Traffic downlink data frames......(!!) | |
791 API a_dd_0[22]; // 0x09F0 Header + DATA traffic downlink information, sub. chan. 0. | |
792 | |
793 // CCCH/SACCH uplink information.....(!!) | |
794 API a_cu[15]; // 0x0A06 Header + CCCH/SACCH uplink information. | |
795 | |
796 // FACCH downlink information........(!!) | |
797 API a_fu[15]; // 0x0A15 Header + FACCH uplink information | |
798 | |
799 // Traffic downlink data frames......(!!) | |
800 API a_du_0[22]; // 0x0A24 Header + DATA traffic uplink information, sub. chan. 0. | |
801 | |
802 // Random access.....................(MCU -> DSP). | |
803 API d_rach; // 0x0A3A RACH information. | |
804 | |
805 //...................................(MCU -> DSP). | |
806 API a_kc[4]; // 0x0A3B Encryption Key Code. | |
807 | |
808 // Integrated Data Services module | |
809 API d_ra_conf; | |
810 API d_ra_act; | |
811 API d_ra_test; | |
812 API d_ra_statu; | |
813 API d_ra_statd; | |
814 API d_fax; | |
815 API a_data_buf_ul[21]; // 0x0A45 | |
816 API a_data_buf_dl[37]; // 0x0A5A | |
817 | |
818 API a_sr_holes0[422]; // 0x0A7F | |
819 | |
820 #if (L1_AEC == 1) | |
821 #if (L1_NEW_AEC) | |
822 API d_cont_filter; | |
823 API d_granularity_att; | |
824 API d_coef_smooth; | |
825 API d_es_level_max; | |
826 API d_fact_vad; | |
827 API d_thrs_abs; | |
828 API d_fact_asd_fil; | |
829 API d_fact_asd_mut; | |
830 API d_far_end_pow_h; | |
831 API d_far_end_pow_l; | |
832 API d_far_end_noise_h; | |
833 API d_far_end_noise_l; | |
834 #else | |
835 API a_sr_hole1[12]; | |
836 #endif | |
837 #else | |
838 API a_sr_hole2[12]; | |
839 #endif | |
840 | |
841 // Speech recognition model | |
842 API a_sr_holes1[145]; // 0x0C31 | |
843 | |
844 // Correction of PR G23M/L1_MCU-SPR-15494 | |
845 API d_cport_init; // 0x0CC2 | |
846 API d_cport_ctrl; | |
847 API a_cport_cfr[2]; | |
848 API d_cport_tcl_tadt; | |
849 API d_cport_tdat; | |
850 API d_cport_tvs; | |
851 API d_cport_status; | |
852 API d_cport_reg_value; | |
853 API a_cport_holes[1011]; | |
854 | |
855 API a_model_holes[1041]; | |
856 | |
857 // EOTD buffer | |
858 #if (L1_EOTD==1) | |
859 API d_eotd_first; | |
860 API d_eotd_max; | |
861 API d_eotd_nrj_high; | |
862 API d_eotd_nrj_low; | |
863 API a_eotd_crosscor[18]; | |
864 #else | |
865 API a_eotd_holes[22]; | |
866 #endif | |
867 // AMR ver 1.0 buffers | |
868 API a_amr_config[4]; // 0x14E5 | |
869 API a_ratscch_ul[6]; | |
870 API a_ratscch_dl[6]; | |
871 API d_amr_snr_est; // estimation of the SNR of the AMR speech block | |
872 #if (L1_VOICE_MEMO_AMR) | |
873 API d_amms_ul_voc; | |
874 #else | |
875 API a_voice_memo_amr_holes[1]; | |
876 #endif | |
877 API d_thr_onset_afs; // thresh detection ONSET AFS | |
878 API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS | |
879 API d_thr_ratscch_afs; // thresh detection RATSCCH AFS | |
880 API d_thr_update_afs; // thresh detection SID_UPDATE AFS | |
881 API d_thr_onset_ahs; // thresh detection ONSET AHS | |
882 API d_thr_sid_ahs; // thresh detection SID frames AHS | |
883 API d_thr_ratscch_marker; // thresh detection RATSCCH MARKER | |
884 API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA | |
885 API d_thr_soft_bits; // 0x14FF | |
886 | |
887 | |
888 API a_amrschd_debug[30]; // 0x1500 | |
889 #if (W_A_AMR_THRESHOLDS) | |
890 API a_d_macc_thr_afs[8]; // 0x151E | |
891 API a_d_macc_thr_ahs[6]; // 0x1526 | |
892 #else | |
893 API d_holes[14]; // 0x151E | |
894 #endif | |
895 | |
896 // There is no melody E2 in DSP ROM38 as of now -> Only Holes | |
897 API d_melody_e2_holes[17]; // 0x152C | |
898 | |
899 | |
900 API d_vol_ul_level_hole; // 0x153D | |
901 API d_vol_dl_level_hole; // 0x153E | |
902 API d_vol_speed_hole; // 0x153F | |
903 API d_sidetone_level_hole; // 0x1540 | |
904 | |
905 // Audio control area | |
906 API d_es_ctrl; // 0x1541 | |
907 API d_anr_ul_ctrl; | |
908 API d_aec_ul_ctrl; | |
909 API d_agc_ul_ctrl; | |
910 //API d_aqi_ctrl_hole1[4]; // Reserved for future UL modules earlier code now modified and added d_vad_noise_ene_ndb | |
911 API d_aqi_ctrl_hole1[1]; // Reserved for future UL modules | |
912 | |
913 API d_vad_noise_ene_ndb[2]; //NAVC API address-0x1546-MSB, 0x1547-LSB-> 2-WORDs | |
914 | |
915 API d_navc_ctrl_status; // NAVC control | |
916 | |
917 API d_iir_dl_ctrl; // 0x1549 | |
918 API d_lim_dl_ctrl; | |
919 API d_drc_dl_ctrl; | |
920 API d_agc_dl_ctrl; | |
921 API d_audio_apps_ctrl; // Reserved for future DL modules | |
922 API d_audio_apps_status; | |
923 API d_aqi_status; | |
924 | |
925 #if (L1_IIR == 1) | |
926 API d_iir_input_scaling; // 0x1550 | |
927 API d_iir_fir_scaling; // | |
928 API d_iir_input_gain_scaling; // | |
929 API d_iir_output_gain_scaling; // | |
930 API d_iir_output_gain; // | |
931 API d_iir_feedback; // | |
932 API d_iir_nb_iir_blocks; // | |
933 API d_iir_nb_fir_coefs; // | |
934 API a_iir_iir_coefs[80]; // 0x1558 | |
935 API a_iir_fir_coefs[32]; // 0x15A8 | |
936 | |
937 #if (L1_ANR == 1) | |
938 API d_anr_min_gain; | |
939 API d_anr_vad_thr; | |
940 API d_anr_gamma_slow; | |
941 API d_anr_gamma_fast; | |
942 API d_anr_gamma_gain_slow; | |
943 API d_anr_gamma_gain_fast; | |
944 API d_anr_thr2; | |
945 API d_anr_thr4; | |
946 API d_anr_thr5; | |
947 API d_anr_mean_ratio_thr1; | |
948 API d_anr_mean_ratio_thr2; | |
949 API d_anr_mean_ratio_thr3; | |
950 API d_anr_mean_ratio_thr4; | |
951 API d_anr_div_factor_shift; | |
952 API d_anr_ns_level; | |
953 #else | |
954 API d_anr_hole[15]; | |
955 #endif | |
956 | |
957 | |
958 #elif (L1_IIR == 2) //Srart address= 0x1550. | |
959 API d_iir4x_control; | |
960 API d_iir4x_frame_size; | |
961 API d_iir4x_fir_swap; | |
962 API d_iir4x_fir_enable; | |
963 API d_iir4x_fir_length; | |
964 API_SIGNED d_iir4x_fir_shift; | |
965 API_SIGNED a_iir4x_fir_taps[40]; | |
966 API d_iir4x_sos_enable; | |
967 API d_iir4x_sos_number; | |
968 API_SIGNED d_iir4x_sos_fact_1; | |
969 API_SIGNED d_iir4x_sos_fact_form_1; | |
970 API_SIGNED a_iir4x_sos_den_1[2]; | |
971 API_SIGNED a_iir4x_sos_num_1[3]; | |
972 API_SIGNED d_iir4x_sos_num_form_1; | |
973 API_SIGNED d_iir4x_sos_fact_2; | |
974 API_SIGNED d_iir4x_sos_fact_form_2; | |
975 API_SIGNED a_iir4x_sos_den_2[2]; | |
976 API_SIGNED a_iir4x_sos_num_2[3]; | |
977 API_SIGNED d_iir4x_sos_num_form_2; | |
978 API_SIGNED d_iir4x_sos_fact_3; | |
979 API_SIGNED d_iir4x_sos_fact_form_3; | |
980 API_SIGNED a_iir4x_sos_den_3[2]; | |
981 API_SIGNED a_iir4x_sos_num_3[3]; | |
982 API_SIGNED d_iir4x_sos_num_form_3; | |
983 API_SIGNED d_iir4x_sos_fact_4; | |
984 API_SIGNED d_iir4x_sos_fact_form_4; | |
985 API_SIGNED a_iir4x_sos_den_4[2]; | |
986 API_SIGNED a_iir4x_sos_num_4[3]; | |
987 API_SIGNED d_iir4x_sos_num_form_4; | |
988 API_SIGNED d_iir4x_sos_fact_5; | |
989 API_SIGNED d_iir4x_sos_fact_form_5; | |
990 API_SIGNED a_iir4x_sos_den_5[2]; | |
991 API_SIGNED a_iir4x_sos_num_5[3]; | |
992 API_SIGNED d_iir4x_sos_num_form_5; | |
993 API_SIGNED d_iir4x_sos_fact_6; | |
994 API_SIGNED d_iir4x_sos_fact_form_6; | |
995 API_SIGNED a_iir4x_sos_den_6[2]; | |
996 API_SIGNED a_iir4x_sos_num_6[3]; | |
997 API_SIGNED d_iir4x_sos_num_form_6; | |
998 API_SIGNED d_iir4x_gain; //End address= 0x15B0 | |
999 | |
1000 | |
1001 #if (L1_AGC_UL == 1) //Start address= 0x15B1 | |
1002 // AGC uplink | |
1003 API d_agc_ul_control; | |
1004 API d_agc_ul_frame_size; | |
1005 API_SIGNED d_agc_ul_targeted_level; | |
1006 API_SIGNED d_agc_ul_signal_up; | |
1007 API_SIGNED d_agc_ul_signal_down; | |
1008 API_SIGNED d_agc_ul_max_scale; | |
1009 API_SIGNED d_agc_ul_gain_smooth_alpha; | |
1010 API_SIGNED d_agc_ul_gain_smooth_alpha_fast; | |
1011 API_SIGNED d_agc_ul_gain_smooth_beta; | |
1012 API_SIGNED d_agc_ul_gain_smooth_beta_fast; | |
1013 API_SIGNED d_agc_ul_gain_intp_flag; | |
1014 #else | |
1015 API d_agc_ul_holes[11]; | |
1016 #endif //End address= 0x15BB | |
1017 | |
1018 #if (L1_AGC_DL == 1) | |
1019 // AGC downlink | |
1020 API d_agc_dl_control; //Start Address= 0x15BC | |
1021 API d_agc_dl_frame_size; | |
1022 API_SIGNED d_agc_dl_targeted_level; | |
1023 API_SIGNED d_agc_dl_signal_up; | |
1024 API_SIGNED d_agc_dl_signal_down; | |
1025 API_SIGNED d_agc_dl_max_scale; | |
1026 API_SIGNED d_agc_dl_gain_smooth_alpha; | |
1027 API_SIGNED d_agc_dl_gain_smooth_alpha_fast; | |
1028 API_SIGNED d_agc_dl_gain_smooth_beta; | |
1029 API_SIGNED d_agc_dl_gain_smooth_beta_fast; | |
1030 API_SIGNED d_agc_dl_gain_intp_flag; | |
1031 #else | |
1032 API d_agc_dl_holes[11]; | |
1033 #endif //End address= 0x15C6 | |
1034 | |
1035 | |
1036 #if(L1_AEC == 2) | |
1037 API d_aec_mode; //Start address= 0x15C7 | |
1038 API d_mu; | |
1039 API d_cont_filter; | |
1040 API d_scale_input_ul; | |
1041 API d_scale_input_dl; | |
1042 API d_div_dmax; | |
1043 API d_div_swap_good; | |
1044 API d_div_swap_bad; | |
1045 API d_block_init; | |
1046 API d_fact_vad; | |
1047 API d_fact_asd_fil; | |
1048 API d_fact_asd_mut; | |
1049 API d_thrs_abs; | |
1050 API d_es_level_max; | |
1051 API d_granularity_att; | |
1052 API d_coef_smooth; //End address= 0x15D6 | |
1053 | |
1054 #else | |
1055 | |
1056 #if (L1_ANR == 1) | |
1057 API d_iir_holes[1]; | |
1058 | |
1059 API d_anr_min_gain; | |
1060 API d_anr_vad_thr; | |
1061 API d_anr_gamma_slow; | |
1062 API d_anr_gamma_fast; | |
1063 API d_anr_gamma_gain_slow; | |
1064 API d_anr_gamma_gain_fast; | |
1065 API d_anr_thr2; | |
1066 API d_anr_thr4; | |
1067 API d_anr_thr5; | |
1068 API d_anr_mean_ratio_thr1; | |
1069 API d_anr_mean_ratio_thr2; | |
1070 API d_anr_mean_ratio_thr3; | |
1071 API d_anr_mean_ratio_thr4; | |
1072 API d_anr_div_factor_shift; | |
1073 API d_anr_ns_level; | |
1074 #else | |
1075 API d_iir_anr_hole[16]; | |
1076 #endif | |
1077 #endif | |
1078 | |
1079 | |
1080 #else | |
1081 API d_iir_holes_1[97]; | |
1082 #if (L1_AGC_UL == 1) | |
1083 // AGC uplink | |
1084 API d_agc_ul_control; | |
1085 API d_agc_ul_frame_size; | |
1086 API_SIGNED d_agc_ul_targeted_level; | |
1087 API_SIGNED d_agc_ul_signal_up; | |
1088 API_SIGNED d_agc_ul_signal_down; | |
1089 API_SIGNED d_agc_ul_max_scale; | |
1090 API_SIGNED d_agc_ul_gain_smooth_alpha; | |
1091 API_SIGNED d_agc_ul_gain_smooth_alpha_fast; | |
1092 API_SIGNED d_agc_ul_gain_smooth_beta; | |
1093 API_SIGNED d_agc_ul_gain_smooth_beta_fast; | |
1094 API_SIGNED d_agc_ul_gain_intp_flag; | |
1095 #else | |
1096 API d_agc_ul_holes[11]; | |
1097 #endif | |
1098 | |
1099 #if (L1_AGC_DL == 1) | |
1100 // AGC downlink | |
1101 API d_agc_dl_control; | |
1102 API d_agc_dl_frame_size; | |
1103 API_SIGNED d_agc_dl_targeted_level; | |
1104 API_SIGNED d_agc_dl_signal_up; | |
1105 API_SIGNED d_agc_dl_signal_down; | |
1106 API_SIGNED d_agc_dl_max_scale; | |
1107 API_SIGNED d_agc_dl_gain_smooth_alpha; | |
1108 API_SIGNED d_agc_dl_gain_smooth_alpha_fast; | |
1109 API_SIGNED d_agc_dl_gain_smooth_beta; | |
1110 API_SIGNED d_agc_dl_gain_smooth_beta_fast; | |
1111 API_SIGNED d_agc_dl_gain_intp_flag; | |
1112 #else | |
1113 API d_agc_dl_holes[11]; | |
1114 #endif | |
1115 | |
1116 #if(L1_AEC == 2) | |
1117 API d_aec_mode; | |
1118 API d_mu; | |
1119 API d_cont_filter; | |
1120 API d_scale_input_ul; | |
1121 API d_scale_input_dl; | |
1122 API d_div_dmax; | |
1123 API d_div_swap_good; | |
1124 API d_div_swap_bad; | |
1125 API d_block_init; | |
1126 API d_fact_vad; | |
1127 API d_fact_asd_fil; | |
1128 API d_fact_asd_mut; | |
1129 API d_thrs_abs; | |
1130 API d_es_level_max; | |
1131 API d_granularity_att; | |
1132 API d_coef_smooth; | |
1133 | |
1134 #else | |
1135 | |
1136 #if(L1_ANR == 1) | |
1137 API d_iir_holes[1]; | |
1138 | |
1139 API d_anr_min_gain; | |
1140 API d_anr_vad_thr; | |
1141 API d_anr_gamma_slow; | |
1142 API d_anr_gamma_fast; | |
1143 API d_anr_gamma_gain_slow; | |
1144 API d_anr_gamma_gain_fast; | |
1145 API d_anr_thr2; | |
1146 API d_anr_thr4; | |
1147 API d_anr_thr5; | |
1148 API d_anr_mean_ratio_thr1; | |
1149 API d_anr_mean_ratio_thr2; | |
1150 API d_anr_mean_ratio_thr3; | |
1151 API d_anr_mean_ratio_thr4; | |
1152 API d_anr_div_factor_shift; | |
1153 API d_anr_ns_level; | |
1154 #else | |
1155 API d_iir_anr_hole[16]; | |
1156 #endif | |
1157 | |
1158 #endif | |
1159 | |
1160 #endif //L1_IIR | |
1161 | |
1162 #if (L1_LIMITER == 1) | |
1163 API a_lim_mul_low[2]; // 0x15D7 | |
1164 API a_lim_mul_high[2]; | |
1165 API d_lim_gain_fall_q15; // 0x15DB | |
1166 API d_lim_gain_rise_q15; // | |
1167 API d_lim_block_size; // 0x15DD | |
1168 API d_lim_nb_fir_coefs; // | |
1169 API d_lim_slope_update_period; | |
1170 API a_lim_filter_coefs[16]; // 0x15E0 | |
1171 #else | |
1172 API d_lim_hole[25]; | |
1173 #endif | |
1174 #if (L1_ES == 1) | |
1175 API d_es_mode; // 0x15F0 | |
1176 API d_es_gain_dl; | |
1177 API d_es_gain_ul_1; | |
1178 API d_es_gain_ul_2; | |
1179 API d_es_tcl_fe_ls_thr; | |
1180 API d_es_tcl_dt_ls_thr; | |
1181 API d_es_tcl_fe_ns_thr; | |
1182 API d_es_tcl_dt_ns_thr; | |
1183 API d_es_tcl_ne_thr; | |
1184 API d_es_ref_ls_pwr; | |
1185 API d_es_switching_time; | |
1186 API d_es_switching_time_dt; | |
1187 API d_es_hang_time; | |
1188 API a_es_gain_lin_dl_vect[4]; | |
1189 API a_es_gain_lin_ul_vect[4]; | |
1190 #else | |
1191 API d_es_hole[21]; | |
1192 #endif | |
1193 | |
1194 #if (L1_ANR == 2) | |
1195 API_SIGNED d_anr_ns_level; // start address= 0x1605 | |
1196 API_SIGNED d_anr_control; | |
1197 API_SIGNED d_anr_tone_ene_th; | |
1198 API_SIGNED d_anr_tone_cnt_th; | |
1199 #else | |
1200 API d_anr_hole_2[4]; | |
1201 #endif //End address= 0x1608 | |
1202 | |
1203 #if (L1_WCM == 1) // start address= 0x1609 | |
1204 API_SIGNED d_wcm_mode; | |
1205 API_SIGNED d_wcm_frame_size; | |
1206 API_SIGNED d_wcm_num_sub_frames; | |
1207 API_SIGNED d_wcm_ratio; | |
1208 API_SIGNED d_wcm_threshold; | |
1209 API_SIGNED a_wcm_gain[16]; | |
1210 #else | |
1211 API_SIGNED d_wcm_holes[21]; | |
1212 #endif | |
1213 | |
1214 API a_tty_holes1[24]; // 0x161E | |
1215 | |
1216 #if (L1_GTT == 1) | |
1217 API d_tty_status; // 0x1636 | |
1218 API d_ctm_detect_shift; // 0x1637 | |
1219 API d_tty2x_baudot_mod_amplitude_scale; | |
1220 API d_tty2x_samples_per_baudot_stop_bit; | |
1221 API d_tty_reset_buffer_ul; | |
1222 API d_tty_loop_ctrl; | |
1223 API p_tty_loop_buffer; | |
1224 API d_ctm_mod_norm; | |
1225 API d_tty2x_offset_normalization; | |
1226 API d_tty2x_threshold_startbit; | |
1227 API d_tty2x_threshold_diff; // 0x1640 | |
1228 API d_tty2x_duration_startdetect; // 0x1641 | |
1229 API d_tty2x_startbit_thres; // 0x1642 | |
1230 API d_tty2x_hole_init_mute_frame_count; // 0x1643 | |
1231 API d_tty2x_dl_bypass_mute; // 0x1644 | |
1232 #else | |
1233 API a_tty_holes2[15]; | |
1234 #endif | |
1235 | |
1236 API a_tty_fifo_holes[131]; // 0x1645 | |
1237 | |
1238 // New DRP Releated Variables Start Here | |
1239 API a_drp_holes_1[6]; // 0x16C8 | |
1240 API d_drp_apcctrl2_hole; // 0x16CE - APC control register 2 | |
1241 API d_drp_afc_add_api; // 0x16CF - Address where AFC value needs to be written | |
1242 API a_drp_holes_2[12]; // 0x16D0 | |
1243 API a_drp_ramp[20]; // 0x16DC - Power ramp up/down in DRP registers format | |
1244 API a_drp_holes_3[271]; // 0x16F0 | |
1245 | |
1246 | |
1247 API d_dsp_write_debug_pointer; // 0x17FF | |
1248 | |
1249 #if (MELODY_E2) | |
1250 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE]; // 0x1800 | |
1251 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT]; | |
1252 API a_dsp_after_trace_holes[7440-(SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE + SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT)]; | |
1253 #else | |
1254 API a_dsp_trace[C_DEBUG_BUFFER_SIZE]; // 0x1800; | |
1255 API a_dsp_after_trace_holes[7440-C_DEBUG_BUFFER_SIZE]; // 0x1800 + C_DEBUG_BUFFER_SIZE | |
1256 // In this region MP3 variables are placed + holes | |
1257 #endif | |
1258 | |
1259 #if (L1_PCM_EXTRACTION) | |
1260 API a_pcm_api_download[160]; | |
1261 API a_pcm_api_upload[160]; | |
1262 API a_pcm_holes1[8]; | |
1263 API d_pcm_api_upload; | |
1264 API d_pcm_api_download; | |
1265 API d_pcm_api_error; | |
1266 API a_pcm_holes2[1181]; | |
1267 #else | |
1268 API a_pcm_holes[1512]; | |
1269 #endif | |
1270 | |
1271 #if REL99 | |
1272 #if FF_EMR | |
1273 API a_mean_cv_bep_page_0[3];//0x3AF8 | |
1274 API a_mean_cv_bep_padding_0; | |
1275 API a_mean_cv_bep_page_1[3]; | |
1276 API a_mean_cv_bep_padding_1; | |
1277 API a_emr_holes2[378]; | |
1278 #endif | |
1279 #else // L1_R99 | |
1280 API a_emr_holes1[386]; | |
1281 #endif // L1_R99 | |
1282 | |
1283 // SAIC related | |
1284 API a_swh_hole[16]; // 0x3C7A | |
1285 API d_swh_flag_ndb; // 0x3C8A - SWH (whitening) on / off flag | |
1286 API d_swh_Clipping_Threshold_ndb; // 0x3C8B - Threshold to which the DSP shall clip the SNR | |
1287 | |
1288 // A5/3 related | |
1289 API a_a5_kc[8]; // 0x3C8C | |
1290 | |
1291 // DCO related | |
1292 API d_dco_samples_per_symbol; // 0x3C94 No. of samples per symbol (IQ pair) | |
1293 API d_dco_fcw; // 0x3C95 Control word to tell the IF Frequency | |
1294 API a_dco_hole[15]; // 0x3C96 Hole related to DCO | |
1295 | |
1296 // A5/3 related | |
1297 // API a_a5_holes[801]; // 0x3CA5 | |
1298 | |
1299 #if ((FF_REPEATED_SACCH == 1) || (FF_REPEATED_DL_FACCH == 1 )) | |
1300 API a_a5_holes[286]; // 0x3CA5 | |
1301 API d_chase_comb_ctrl; // 0x3DC3 Control for the chase combine feature | |
1302 API a_a5_holes1[514]; // 0x3DC4 | |
1303 #else | |
1304 // A5/3 related | |
1305 API a_a5_holes[801]; // 0x3CA5 | |
1306 #endif /* (FF_REPEATED_SACCH == 1) */ | |
1307 | |
1308 | |
1309 | |
1310 } | |
1311 T_NDB_MCU_DSP; | |
1312 | |
1313 #elif (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) // NDB GSM | |
1314 typedef struct | |
1315 { | |
1316 // MISC Tasks | |
1317 API d_dsp_page; | |
1318 | |
1319 // DSP status returned (DSP --> MCU). | |
1320 API d_error_status; | |
1321 | |
1322 // RIF control (MCU -> DSP). | |
1323 API d_spcx_rif; | |
1324 | |
1325 API d_tch_mode; // TCH mode register. | |
1326 // bit [0..1] -> b_dai_mode. | |
1327 // bit [2] -> b_dtx. | |
1328 | |
1329 API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega | |
1330 | |
1331 API d_dsp_test; | |
1332 | |
1333 // Words dedicated to Software version (DSP code + Patch) | |
1334 API d_version_number1; | |
1335 API d_version_number2; | |
1336 | |
1337 API d_debug_ptr; | |
1338 API d_debug_bk; | |
1339 | |
1340 API d_pll_config; | |
1341 | |
1342 // GSM/GPRS DSP Debug trace support | |
1343 API p_debug_buffer; | |
1344 API d_debug_buffer_size; | |
1345 API d_debug_trace_type; | |
1346 | |
1347 #if (W_A_DSP_IDLE3 == 1) | |
1348 // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3. | |
1349 API d_dsp_state; | |
1350 // 5 words are reserved for any possible mapping modification | |
1351 API d_hole1_ndb[2]; | |
1352 #else | |
1353 // 6 words are reserved for any possible mapping modification | |
1354 API d_hole1_ndb[3]; | |
1355 #endif | |
1356 | |
1357 #if (AMR == 1) | |
1358 API p_debug_amr; | |
1359 #else | |
1360 API d_hole_debug_amr; | |
1361 #endif | |
1362 | |
1363 #if ((CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 | |
1364 #if (DSP == 35) || (DSP == 36) || (DSP == 37) | |
1365 API d_hole2_ndb[1]; | |
1366 API d_mcsi_select; | |
1367 #else | |
1368 API d_hole2_ndb[2]; | |
1369 #endif | |
1370 #else | |
1371 API d_hole2_ndb[2]; | |
1372 #endif | |
1373 | |
1374 // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations | |
1375 API d_apcdel1_bis; | |
1376 API d_apcdel2_bis; | |
1377 | |
1378 | |
1379 // New registers due to IOTA analog base band | |
1380 API d_apcdel2; | |
1381 API d_vbctrl2; | |
1382 API d_bulgcal; | |
1383 | |
1384 // Analog Based Band | |
1385 API d_afcctladd; | |
1386 | |
1387 API d_vbuctrl; | |
1388 API d_vbdctrl; | |
1389 API d_apcdel1; | |
1390 API d_apcoff; | |
1391 API d_bulioff; | |
1392 API d_bulqoff; | |
1393 API d_dai_onoff; | |
1394 API d_auxdac; | |
1395 | |
1396 #if (ANALOG == 1) | |
1397 API d_vbctrl; | |
1398 #elif ((ANALOG == 2) || (ANALOG == 3)) | |
1399 API d_vbctrl1; | |
1400 #endif | |
1401 | |
1402 API d_bbctrl; | |
1403 | |
1404 // Monitoring tasks control (MCU <- DSP) | |
1405 // FB task | |
1406 API d_fb_det; // FB detection result. (1 for FOUND). | |
1407 API d_fb_mode; // Mode for FB detection algorithm. | |
1408 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR). | |
1409 | |
1410 // SB Task | |
1411 API a_sch26[5]; // Header + SB information, array of 5 words. | |
1412 | |
1413 API d_audio_gain_ul; | |
1414 API d_audio_gain_dl; | |
1415 | |
1416 // Controller of the melody E2 audio compressor | |
1417 API d_audio_compressor_ctrl; | |
1418 | |
1419 // AUDIO module | |
1420 API d_audio_init; | |
1421 API d_audio_status; | |
1422 | |
1423 // Audio tasks | |
1424 // TONES (MCU -> DSP) | |
1425 API d_toneskb_init; | |
1426 API d_toneskb_status; | |
1427 API d_k_x1_t0; | |
1428 API d_k_x1_t1; | |
1429 API d_k_x1_t2; | |
1430 API d_pe_rep; | |
1431 API d_pe_off; | |
1432 API d_se_off; | |
1433 API d_bu_off; | |
1434 API d_t0_on; | |
1435 API d_t0_off; | |
1436 API d_t1_on; | |
1437 API d_t1_off; | |
1438 API d_t2_on; | |
1439 API d_t2_off; | |
1440 API d_k_x1_kt0; | |
1441 API d_k_x1_kt1; | |
1442 API d_dur_kb; | |
1443 API d_shiftdl; | |
1444 API d_shiftul; | |
1445 | |
1446 API d_aec_ctrl; | |
1447 | |
1448 API d_es_level_api; | |
1449 API d_mu_api; | |
1450 | |
1451 // Melody Ringer module | |
1452 API d_melo_osc_used; | |
1453 API d_melo_osc_active; | |
1454 API a_melo_note0[4]; | |
1455 API a_melo_note1[4]; | |
1456 API a_melo_note2[4]; | |
1457 API a_melo_note3[4]; | |
1458 API a_melo_note4[4]; | |
1459 API a_melo_note5[4]; | |
1460 API a_melo_note6[4]; | |
1461 API a_melo_note7[4]; | |
1462 | |
1463 // selection of the melody format | |
1464 API d_melody_selection; | |
1465 | |
1466 // Holes due to the format melody E1 | |
1467 API a_melo_holes[3]; | |
1468 | |
1469 // Speech Recognition module | |
1470 API d_sr_status; // status of the DSP speech reco task | |
1471 API d_sr_param; // paramters for the DSP speech reco task: OOV threshold. | |
1472 API d_sr_bit_exact_test; // bit exact test | |
1473 API d_sr_nb_words; // number of words used in the speech recognition task | |
1474 API d_sr_db_level; // estimate voice level in dB | |
1475 API d_sr_db_noise; // estimate noise in dB | |
1476 API d_sr_mod_size; // size of the model | |
1477 API a_n_best_words[4]; // array of the 4 best words | |
1478 API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length) | |
1479 | |
1480 // Audio buffer | |
1481 API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1. | |
1482 API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1. | |
1483 | |
1484 // V42bis module | |
1485 API d_v42b_nego0; | |
1486 API d_v42b_nego1; | |
1487 API d_v42b_control; | |
1488 API d_v42b_ratio_ind; | |
1489 API d_mcu_control; | |
1490 API d_mcu_control_sema; | |
1491 | |
1492 // Background tasks | |
1493 API d_background_enable; | |
1494 API d_background_abort; | |
1495 API d_background_state; | |
1496 API d_max_background; | |
1497 API a_background_tasks[16]; | |
1498 API a_back_task_io[16]; | |
1499 | |
1500 // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory) | |
1501 API d_gea_mode_ovly; | |
1502 API a_gea_kc_ovly[4]; | |
1503 | |
1504 #if (ANALOG == 3) | |
1505 // SYREN specific registers | |
1506 API d_vbpop; | |
1507 API d_vau_delay_init; | |
1508 API d_vaud_cfg; | |
1509 API d_vauo_onoff; | |
1510 API d_vaus_vol; | |
1511 API d_vaud_pll; | |
1512 API d_togbr2; | |
1513 #elif ((ANALOG == 1) || (ANALOG == 2)) | |
1514 API d_hole3_ndb[7]; | |
1515 #endif | |
1516 | |
1517 // word used for the init of USF threshold | |
1518 API d_thr_usf_detect; | |
1519 | |
1520 // Encryption module | |
1521 API d_a5mode; // Encryption Mode. | |
1522 | |
1523 API d_sched_mode_gprs_ovly; | |
1524 | |
1525 // 7 words are reserved for any possible mapping modification | |
1526 API d_hole4_ndb[5]; | |
1527 | |
1528 // Ramp definition for Omega device | |
1529 API a_ramp[16]; | |
1530 | |
1531 // CCCH/SACCH downlink information...(!!) | |
1532 API a_cd[15]; // Header + CCCH/SACCH downlink information. | |
1533 | |
1534 // FACCH downlink information........(!!) | |
1535 API a_fd[15]; // Header + FACCH downlink information. | |
1536 | |
1537 // Traffic downlink data frames......(!!) | |
1538 API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0. | |
1539 | |
1540 // CCCH/SACCH uplink information.....(!!) | |
1541 API a_cu[15]; // Header + CCCH/SACCH uplink information. | |
1542 | |
1543 // FACCH downlink information........(!!) | |
1544 API a_fu[15]; // Header + FACCH uplink information | |
1545 | |
1546 // Traffic downlink data frames......(!!) | |
1547 API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0. | |
1548 | |
1549 // Random access.....................(MCU -> DSP). | |
1550 API d_rach; // RACH information. | |
1551 | |
1552 //...................................(MCU -> DSP). | |
1553 API a_kc[4]; // Encryption Key Code. | |
1554 | |
1555 // Integrated Data Services module | |
1556 API d_ra_conf; | |
1557 API d_ra_act; | |
1558 API d_ra_test; | |
1559 API d_ra_statu; | |
1560 API d_ra_statd; | |
1561 API d_fax; | |
1562 API a_data_buf_ul[21]; | |
1563 API a_data_buf_dl[37]; | |
1564 | |
1565 // GTT API mapping for DSP code 34 (for test only) | |
1566 #if (L1_GTT == 1) | |
1567 API d_tty_status; | |
1568 API d_ctm_detect_shift; | |
1569 API d_tty2x_baudot_mod_amplitude_scale; | |
1570 API d_tty2x_samples_per_baudot_stop_bit; | |
1571 API d_tty_reset_buffer_ul; | |
1572 API d_tty_loop_ctrl; | |
1573 API p_tty_loop_buffer; | |
1574 API d_ctm_mod_norm; | |
1575 API d_tty2x_offset_normalization; | |
1576 API d_tty2x_threshold_startbit; | |
1577 API d_tty2x_threshold_diff; | |
1578 API d_tty2x_duration_startdetect; | |
1579 API d_tty2x_startbit_thres; | |
1580 #else | |
1581 API a_tty_holes[13]; | |
1582 #endif | |
1583 | |
1584 API a_sr_holes0[409]; | |
1585 | |
1586 | |
1587 #if (L1_NEW_AEC) | |
1588 // new AEC | |
1589 API d_cont_filter; | |
1590 API d_granularity_att; | |
1591 API d_coef_smooth; | |
1592 API d_es_level_max; | |
1593 API d_fact_vad; | |
1594 API d_thrs_abs; | |
1595 API d_fact_asd_fil; | |
1596 API d_fact_asd_mut; | |
1597 API d_far_end_pow_h; | |
1598 API d_far_end_pow_l; | |
1599 API d_far_end_noise_h; | |
1600 API d_far_end_noise_l; | |
1601 #else | |
1602 API a_new_aec_holes[12]; | |
1603 #endif // L1_NEW_AEC | |
1604 | |
1605 // Speech recognition model | |
1606 API a_sr_holes1[145]; | |
1607 | |
1608 // Correction of PR G23M/L1_MCU-SPR-15494 | |
1609 #if ((CHIPSET == 12) || (CHIPSET == 4) || (CODE_VERSION == SIMULATION)) | |
1610 API d_cport_init; | |
1611 API d_cport_ctrl; | |
1612 API a_cport_cfr[2]; | |
1613 API d_cport_tcl_tadt; | |
1614 API d_cport_tdat; | |
1615 API d_cport_tvs; | |
1616 API d_cport_status; | |
1617 API d_cport_reg_value; | |
1618 | |
1619 API a_cport_holes[1011]; | |
1620 #else // CHIPSET != 12 | |
1621 API a_cport_holes[1020]; | |
1622 #endif // CHIPSET == 12 | |
1623 | |
1624 API a_model[1041]; | |
1625 | |
1626 // EOTD buffer | |
1627 #if (L1_EOTD==1) | |
1628 API d_eotd_first; | |
1629 API d_eotd_max; | |
1630 API d_eotd_nrj_high; | |
1631 API d_eotd_nrj_low; | |
1632 API a_eotd_crosscor[18]; | |
1633 #else | |
1634 API a_eotd_holes[22]; | |
1635 #endif | |
1636 // AMR ver 1.0 buffers | |
1637 API a_amr_config[4]; | |
1638 API a_ratscch_ul[6]; | |
1639 API a_ratscch_dl[6]; | |
1640 API d_amr_snr_est; // estimation of the SNR of the AMR speech block | |
1641 #if (L1_VOICE_MEMO_AMR) | |
1642 API d_amms_ul_voc; | |
1643 #else | |
1644 API a_voice_memo_amr_holes[1]; | |
1645 #endif | |
1646 API d_thr_onset_afs; // thresh detection ONSET AFS | |
1647 API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS | |
1648 API d_thr_ratscch_afs; // thresh detection RATSCCH AFS | |
1649 API d_thr_update_afs; // thresh detection SID_UPDATE AFS | |
1650 API d_thr_onset_ahs; // thresh detection ONSET AHS | |
1651 API d_thr_sid_ahs; // thresh detection SID frames AHS | |
1652 API d_thr_ratscch_marker; // thresh detection RATSCCH MARKER | |
1653 API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA | |
1654 API d_thr_soft_bits; | |
1655 | |
1656 #if ((CODE_VERSION == SIMULATION) || (DSP != 37)) | |
1657 #if (MELODY_E2) | |
1658 API d_melody_e2_osc_stop; | |
1659 API d_melody_e2_osc_active; | |
1660 API d_melody_e2_semaphore; | |
1661 API a_melody_e2_osc[16][3]; | |
1662 API d_melody_e2_globaltimefactor; | |
1663 API a_melody_e2_instrument_ptr[8]; | |
1664 API d_melody_e2_deltatime; | |
1665 #else | |
1666 API d_melody_e2_holes[61]; | |
1667 #endif | |
1668 #else // (DSP == 37) | |
1669 API a_amrschd_debug[30]; // 0x1500 | |
1670 #if (W_A_AMR_THRESHOLDS) | |
1671 API a_d_macc_thr_afs[8]; // 0x151E | |
1672 API a_d_macc_thr_ahs[6]; // 0x1526 | |
1673 #else | |
1674 API a_d_macc_thr_holes[14]; // 0x151E | |
1675 #endif | |
1676 API d_melody_e2_holes[17]; //0x152C - This is not a melody E2 hole; But named like that; | |
1677 #endif | |
1678 | |
1679 #if ((CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1)) || (CODE_VERSION == SIMULATION)) // Calypso+ or Perseus2 or Samson | |
1680 API d_vol_ul_level; | |
1681 API d_vol_dl_level; | |
1682 API d_vol_speed; | |
1683 API d_sidetone_level; | |
1684 | |
1685 // Audio control area | |
1686 API d_es_ctrl; | |
1687 API d_anr_ul_ctrl; | |
1688 | |
1689 #if ((DSP == 36) || (DSP == 37)) | |
1690 | |
1691 API d_aqi_ctrl_hole1_1[3]; | |
1692 #if (L1_SAIC != 0) | |
1693 API d_swh_flag_ndb; | |
1694 API d_swh_Clipping_Threshold_ndb; | |
1695 #else | |
1696 API d_swh_hole[2]; | |
1697 #endif | |
1698 API d_aqi_ctrl_hole1_2[1]; | |
1699 #else | |
1700 API d_aqi_ctrl_hole1[6]; // Reserved for future UL modules | |
1701 #endif | |
1702 API d_iir_dl_ctrl; | |
1703 API d_lim_dl_ctrl; | |
1704 API d_aqi_ctrl_hole2[4]; // Reserved for future DL modules | |
1705 API d_aqi_status; | |
1706 | |
1707 #if (L1_IIR == 1) | |
1708 API d_iir_input_scaling; | |
1709 API d_iir_fir_scaling; | |
1710 API d_iir_input_gain_scaling; | |
1711 API d_iir_output_gain_scaling; | |
1712 API d_iir_output_gain; | |
1713 API d_iir_feedback; | |
1714 API d_iir_nb_iir_blocks; | |
1715 API d_iir_nb_fir_coefs; | |
1716 API a_iir_iir_coefs[80]; | |
1717 API a_iir_fir_coefs[32]; | |
1718 #else | |
1719 API d_iir_hole[120]; | |
1720 #endif | |
1721 | |
1722 #if (L1_ANR == 1) | |
1723 API d_anr_min_gain; | |
1724 API d_anr_vad_thr; | |
1725 API d_anr_gamma_slow; | |
1726 API d_anr_gamma_fast; | |
1727 API d_anr_gamma_gain_slow; | |
1728 API d_anr_gamma_gain_fast; | |
1729 API d_anr_thr2; | |
1730 API d_anr_thr4; | |
1731 API d_anr_thr5; | |
1732 API d_anr_mean_ratio_thr1; | |
1733 API d_anr_mean_ratio_thr2; | |
1734 API d_anr_mean_ratio_thr3; | |
1735 API d_anr_mean_ratio_thr4; | |
1736 API d_anr_div_factor_shift; | |
1737 API d_anr_ns_level; | |
1738 #else | |
1739 API d_anr_hole[15]; | |
1740 #endif | |
1741 | |
1742 #if (L1_LIMITER == 1) | |
1743 API a_lim_mul_low[2]; | |
1744 API a_lim_mul_high[2]; | |
1745 API d_lim_gain_fall_q15; | |
1746 API d_lim_gain_rise_q15; | |
1747 API d_lim_block_size; | |
1748 API d_lim_nb_fir_coefs; | |
1749 API d_lim_slope_update_period; | |
1750 API a_lim_filter_coefs[16]; | |
1751 #else | |
1752 API d_lim_hole[25]; | |
1753 #endif | |
1754 #if (L1_ES == 1) | |
1755 API d_es_mode; | |
1756 API d_es_gain_dl; | |
1757 API d_es_gain_ul_1; | |
1758 API d_es_gain_ul_2; | |
1759 API d_es_tcl_fe_ls_thr; | |
1760 API d_es_tcl_dt_ls_thr; | |
1761 API d_es_tcl_fe_ns_thr; | |
1762 API d_es_tcl_dt_ns_thr; | |
1763 API d_es_tcl_ne_thr; | |
1764 API d_es_ref_ls_pwr; | |
1765 API d_es_switching_time; | |
1766 API d_es_switching_time_dt; | |
1767 API d_es_hang_time; | |
1768 API a_es_gain_lin_dl_vect[4]; | |
1769 API a_es_gain_lin_ul_vect[4]; | |
1770 #else | |
1771 API d_es_hole[21]; | |
1772 #endif | |
1773 | |
1774 #else // CALYPSO+ or PERSEUS2 | |
1775 API a_calplus_holes[200]; | |
1776 #endif | |
1777 | |
1778 #if (W_A_AMR_THRESHOLDS) | |
1779 API d_holes[492]; | |
1780 #if (CODE_VERSION == SIMULATION) || (DSP != 37) | |
1781 API a_d_macc_thr_afs[8]; // In ROM37 this is moved from 0x17F1 to 0x151E | |
1782 API a_d_macc_thr_ahs[6]; | |
1783 #else | |
1784 API d_holes_rom37[14]; // In ROM37 this is moved from 0x17F1 to 0x151E | |
1785 #endif | |
1786 API d_one_hole[1]; | |
1787 #else | |
1788 API d_holes[507]; | |
1789 #endif | |
1790 | |
1791 #if (MELODY_E2) | |
1792 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE]; | |
1793 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT]; | |
1794 #endif | |
1795 } | |
1796 T_NDB_MCU_DSP; | |
1797 #elif (DSP == 33) // NDB GSM | |
1798 typedef struct | |
1799 { | |
1800 // MISC Tasks | |
1801 API d_dsp_page; | |
1802 | |
1803 // DSP status returned (DSP --> MCU). | |
1804 API d_error_status; | |
1805 | |
1806 // RIF control (MCU -> DSP). | |
1807 API d_spcx_rif; | |
1808 | |
1809 API d_tch_mode; // TCH mode register. | |
1810 // bit [0..1] -> b_dai_mode. | |
1811 // bit [2] -> b_dtx. | |
1812 | |
1813 API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega | |
1814 | |
1815 API d_dsp_test; | |
1816 | |
1817 // Words dedicated to Software version (DSP code + Patch) | |
1818 API d_version_number1; | |
1819 API d_version_number2; | |
1820 | |
1821 API d_debug_ptr; | |
1822 API d_debug_bk; | |
1823 | |
1824 API d_pll_config; | |
1825 | |
1826 // GSM/GPRS DSP Debug trace support | |
1827 API p_debug_buffer; | |
1828 API d_debug_buffer_size; | |
1829 API d_debug_trace_type; | |
1830 | |
1831 #if (W_A_DSP_IDLE3 == 1) | |
1832 // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3. | |
1833 API d_dsp_state; | |
1834 // 10 words are reserved for any possible mapping modification | |
1835 API d_hole1_ndb[5]; | |
1836 #else | |
1837 // 11 words are reserved for any possible mapping modification | |
1838 API d_hole1_ndb[6]; | |
1839 #endif | |
1840 | |
1841 // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations | |
1842 API d_apcdel1_bis; | |
1843 API d_apcdel2_bis; | |
1844 | |
1845 | |
1846 // New registers due to IOTA analog base band | |
1847 API d_apcdel2; | |
1848 API d_vbctrl2; | |
1849 API d_bulgcal; | |
1850 | |
1851 // Analog Based Band | |
1852 API d_afcctladd; | |
1853 | |
1854 API d_vbuctrl; | |
1855 API d_vbdctrl; | |
1856 API d_apcdel1; | |
1857 API d_apcoff; | |
1858 API d_bulioff; | |
1859 API d_bulqoff; | |
1860 API d_dai_onoff; | |
1861 API d_auxdac; | |
1862 | |
1863 #if (ANALOG == 1) | |
1864 API d_vbctrl; | |
1865 #elif ((ANALOG == 2) || (ANALOG == 3)) | |
1866 API d_vbctrl1; | |
1867 #endif | |
1868 | |
1869 API d_bbctrl; | |
1870 | |
1871 // Monitoring tasks control (MCU <- DSP) | |
1872 // FB task | |
1873 API d_fb_det; // FB detection result. (1 for FOUND). | |
1874 API d_fb_mode; // Mode for FB detection algorithm. | |
1875 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR). | |
1876 | |
1877 // SB Task | |
1878 API a_sch26[5]; // Header + SB information, array of 5 words. | |
1879 | |
1880 API d_audio_gain_ul; | |
1881 API d_audio_gain_dl; | |
1882 | |
1883 // Controller of the melody E2 audio compressor | |
1884 API d_audio_compressor_ctrl; | |
1885 | |
1886 // AUDIO module | |
1887 API d_audio_init; | |
1888 API d_audio_status; | |
1889 | |
1890 // Audio tasks | |
1891 // TONES (MCU -> DSP) | |
1892 API d_toneskb_init; | |
1893 API d_toneskb_status; | |
1894 API d_k_x1_t0; | |
1895 API d_k_x1_t1; | |
1896 API d_k_x1_t2; | |
1897 API d_pe_rep; | |
1898 API d_pe_off; | |
1899 API d_se_off; | |
1900 API d_bu_off; | |
1901 API d_t0_on; | |
1902 API d_t0_off; | |
1903 API d_t1_on; | |
1904 API d_t1_off; | |
1905 API d_t2_on; | |
1906 API d_t2_off; | |
1907 API d_k_x1_kt0; | |
1908 API d_k_x1_kt1; | |
1909 API d_dur_kb; | |
1910 API d_shiftdl; | |
1911 API d_shiftul; | |
1912 | |
1913 API d_aec_ctrl; | |
1914 | |
1915 API d_es_level_api; | |
1916 API d_mu_api; | |
1917 | |
1918 // Melody Ringer module | |
1919 API d_melo_osc_used; | |
1920 API d_melo_osc_active; | |
1921 API a_melo_note0[4]; | |
1922 API a_melo_note1[4]; | |
1923 API a_melo_note2[4]; | |
1924 API a_melo_note3[4]; | |
1925 API a_melo_note4[4]; | |
1926 API a_melo_note5[4]; | |
1927 API a_melo_note6[4]; | |
1928 API a_melo_note7[4]; | |
1929 | |
1930 // selection of the melody format | |
1931 API d_melody_selection; | |
1932 | |
1933 // Holes due to the format melody E1 | |
1934 API a_melo_holes[3]; | |
1935 | |
1936 // Speech Recognition module | |
1937 API d_sr_status; // status of the DSP speech reco task | |
1938 API d_sr_param; // paramters for the DSP speech reco task: OOV threshold. | |
1939 API d_sr_bit_exact_test; // bit exact test | |
1940 API d_sr_nb_words; // number of words used in the speech recognition task | |
1941 API d_sr_db_level; // estimate voice level in dB | |
1942 API d_sr_db_noise; // estimate noise in dB | |
1943 API d_sr_mod_size; // size of the model | |
1944 API a_n_best_words[4]; // array of the 4 best words | |
1945 API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length) | |
1946 | |
1947 // Audio buffer | |
1948 API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1. | |
1949 API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1. | |
1950 | |
1951 // V42bis module | |
1952 API d_v42b_nego0; | |
1953 API d_v42b_nego1; | |
1954 API d_v42b_control; | |
1955 API d_v42b_ratio_ind; | |
1956 API d_mcu_control; | |
1957 API d_mcu_control_sema; | |
1958 | |
1959 // Background tasks | |
1960 API d_background_enable; | |
1961 API d_background_abort; | |
1962 API d_background_state; | |
1963 API d_max_background; | |
1964 API a_background_tasks[16]; | |
1965 API a_back_task_io[16]; | |
1966 | |
1967 // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory) | |
1968 API d_gea_mode_ovly; | |
1969 API a_gea_kc_ovly[4]; | |
1970 | |
1971 API d_hole3_ndb[8]; | |
1972 | |
1973 // Encryption module | |
1974 API d_a5mode; // Encryption Mode. | |
1975 | |
1976 API d_sched_mode_gprs_ovly; | |
1977 | |
1978 // 7 words are reserved for any possible mapping modification | |
1979 API d_hole4_ndb[5]; | |
1980 | |
1981 // Ramp definition for Omega device | |
1982 API a_ramp[16]; | |
1983 | |
1984 // CCCH/SACCH downlink information...(!!) | |
1985 API a_cd[15]; // Header + CCCH/SACCH downlink information. | |
1986 | |
1987 // FACCH downlink information........(!!) | |
1988 API a_fd[15]; // Header + FACCH downlink information. | |
1989 | |
1990 // Traffic downlink data frames......(!!) | |
1991 API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0. | |
1992 | |
1993 // CCCH/SACCH uplink information.....(!!) | |
1994 API a_cu[15]; // Header + CCCH/SACCH uplink information. | |
1995 | |
1996 // FACCH downlink information........(!!) | |
1997 API a_fu[15]; // Header + FACCH uplink information | |
1998 | |
1999 // Traffic downlink data frames......(!!) | |
2000 API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0. | |
2001 | |
2002 // Random access.....................(MCU -> DSP). | |
2003 API d_rach; // RACH information. | |
2004 | |
2005 //...................................(MCU -> DSP). | |
2006 API a_kc[4]; // Encryption Key Code. | |
2007 | |
2008 // Integrated Data Services module | |
2009 API d_ra_conf; | |
2010 API d_ra_act; | |
2011 API d_ra_test; | |
2012 API d_ra_statu; | |
2013 API d_ra_statd; | |
2014 API d_fax; | |
2015 API a_data_buf_ul[21]; | |
2016 API a_data_buf_dl[37]; | |
2017 | |
2018 #if (L1_NEW_AEC) | |
2019 // new AEC | |
2020 API a_new_aec_holes[422]; | |
2021 API d_cont_filter; | |
2022 API d_granularity_att; | |
2023 API d_coef_smooth; | |
2024 API d_es_level_max; | |
2025 API d_fact_vad; | |
2026 API d_thrs_abs; | |
2027 API d_fact_asd_fil; | |
2028 API d_fact_asd_mut; | |
2029 API d_far_end_pow_h; | |
2030 API d_far_end_pow_l; | |
2031 API d_far_end_noise_h; | |
2032 API d_far_end_noise_l; | |
2033 #endif | |
2034 | |
2035 // Speech recognition model | |
2036 #if (L1_NEW_AEC) | |
2037 API a_sr_holes[1165]; | |
2038 #else | |
2039 API a_sr_holes[1599]; | |
2040 #endif // L1_NEW_AEC | |
2041 API a_model[1041]; | |
2042 | |
2043 // EOTD buffer | |
2044 #if (L1_EOTD==1) | |
2045 API d_eotd_first; | |
2046 API d_eotd_max; | |
2047 API d_eotd_nrj_high; | |
2048 API d_eotd_nrj_low; | |
2049 API a_eotd_crosscor[18]; | |
2050 #else | |
2051 API a_eotd_holes[22]; | |
2052 #endif | |
2053 | |
2054 #if (MELODY_E2) | |
2055 API a_melody_e2_holes0[27]; | |
2056 API d_melody_e2_osc_used; | |
2057 API d_melody_e2_osc_active; | |
2058 API d_melody_e2_semaphore; | |
2059 API a_melody_e2_osc[16][3]; | |
2060 API d_melody_e2_globaltimefactor; | |
2061 API a_melody_e2_instrument_ptr[8]; | |
2062 API a_melody_e2_holes1[708]; | |
2063 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE]; | |
2064 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT]; | |
2065 #endif | |
2066 } | |
2067 T_NDB_MCU_DSP; | |
2068 | |
2069 #elif ((DSP == 32) || (DSP == 31)) | |
2070 typedef struct | |
2071 { | |
2072 // Monitoring tasks control..........(MCU <- DSP) | |
2073 API d_fb_det; // FB detection result. (1 for FOUND). | |
2074 API d_fb_mode; // Mode for FB detection algorithm. | |
2075 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR). | |
2076 | |
2077 // CCCH/SACCH downlink information...(!!) | |
2078 API a_cd[15]; // Header + CCCH/SACCH downlink information. | |
2079 | |
2080 // FACCH downlink information........(!!) | |
2081 API a_fd[15]; // Header + FACCH downlink information. | |
2082 | |
2083 // Traffic downlink data frames......(!!) | |
2084 API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0. | |
2085 API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1. | |
2086 | |
2087 // CCCH/SACCH uplink information.....(!!) | |
2088 API a_cu[15]; // Header + CCCH/SACCH uplink information. | |
2089 | |
2090 #if (SPEECH_RECO) | |
2091 // FACCH downlink information........(!!) | |
2092 API a_fu[3]; // Header + FACCH uplink information | |
2093 // The size of this buffer is 15 word but some speech reco words | |
2094 // are overlayer with this buffer. This is the reason why the size is 3 instead of 15. | |
2095 API d_sr_status; // status of the DSP speech reco task | |
2096 API d_sr_param; // paramters for the DSP speech reco task: OOV threshold. | |
2097 API sr_hole1; // hole | |
2098 API d_sr_bit_exact_test; // bit exact test | |
2099 API d_sr_nb_words; // number of words used in the speech recognition task | |
2100 API d_sr_db_level; // estimate voice level in dB | |
2101 API d_sr_db_noise; // estimate noise in dB | |
2102 API d_sr_mod_size; // size of the model | |
2103 API sr_holes_1[4]; // hole | |
2104 #else | |
2105 // FACCH downlink information........(!!) | |
2106 API a_fu[15]; // Header + FACCH uplink information | |
2107 #endif | |
2108 | |
2109 // Traffic uplink data frames........(!!) | |
2110 API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0. | |
2111 API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1. | |
2112 | |
2113 // Random access.....................(MCU -> DSP). | |
2114 API d_rach; // RACH information. | |
2115 | |
2116 //...................................(MCU -> DSP). | |
2117 API d_a5mode; // Encryption Mode. | |
2118 API a_kc[4]; // Encryption Key Code. | |
2119 API d_tch_mode; // TCH mode register. | |
2120 // bit [0..1] -> b_dai_mode. | |
2121 // bit [2] -> b_dtx. | |
2122 | |
2123 // OMEGA...........................(MCU -> DSP). | |
2124 #if ((ANALOG == 1) || (ANALOG == 2)) | |
2125 API a_ramp[16]; | |
2126 #if (MELODY_E1) | |
2127 API d_melo_osc_used; | |
2128 API d_melo_osc_active; | |
2129 API a_melo_note0[4]; | |
2130 API a_melo_note1[4]; | |
2131 API a_melo_note2[4]; | |
2132 API a_melo_note3[4]; | |
2133 API a_melo_note4[4]; | |
2134 API a_melo_note5[4]; | |
2135 API a_melo_note6[4]; | |
2136 API a_melo_note7[4]; | |
2137 #if (DSP==31) | |
2138 // selection of the melody format | |
2139 API d_melody_selection; | |
2140 API holes[9]; | |
2141 #else // DSP==32 | |
2142 API d_dco_type; // Tide | |
2143 API p_start_IQ; | |
2144 API d_level_off; | |
2145 API d_dco_dbg; | |
2146 API d_tide_resa; | |
2147 API d_asynch_margin; // Perseus Asynch Audio Workaround | |
2148 API hole[4]; | |
2149 #endif // DSP 32 | |
2150 | |
2151 #else // NO MELODY E1 | |
2152 #if (DSP==31) | |
2153 // selection of the melody format | |
2154 API d_melody_selection; | |
2155 API holes[43]; // 43 unused holes. | |
2156 #else // DSP==32 | |
2157 API holes[34]; // 34 unused holes. | |
2158 API d_dco_type; // Tide | |
2159 API p_start_IQ; | |
2160 API d_level_off; | |
2161 API d_dco_dbg; | |
2162 API d_tide_resa; | |
2163 API d_asynch_margin; // Perseus Asynch Audio Workaround | |
2164 API hole[4]; | |
2165 #endif //DSP == 32 | |
2166 #endif // NO MELODY E1 | |
2167 | |
2168 API d_debug3; | |
2169 API d_debug2; | |
2170 API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega | |
2171 API d_afcctladd; | |
2172 API d_vbuctrl; | |
2173 API d_vbdctrl; | |
2174 API d_apcdel1; | |
2175 API d_aec_ctrl; | |
2176 API d_apcoff; | |
2177 API d_bulioff; | |
2178 API d_bulqoff; | |
2179 API d_dai_onoff; | |
2180 API d_auxdac; | |
2181 | |
2182 #if (ANALOG == 1) | |
2183 API d_vbctrl; | |
2184 #elif (ANALOG == 2) | |
2185 API d_vbctrl1; | |
2186 #endif | |
2187 | |
2188 API d_bbctrl; | |
2189 #else | |
2190 #error DSPCODE not supported with given ANALOG | |
2191 #endif //(ANALOG)1, 2 | |
2192 //...................................(MCU -> DSP). | |
2193 API a_sch26[5]; // Header + SB information, array of 5 words. | |
2194 | |
2195 // TONES.............................(MCU -> DSP) | |
2196 API d_toneskb_init; | |
2197 API d_toneskb_status; | |
2198 API d_k_x1_t0; | |
2199 API d_k_x1_t1; | |
2200 API d_k_x1_t2; | |
2201 API d_pe_rep; | |
2202 API d_pe_off; | |
2203 API d_se_off; | |
2204 API d_bu_off; | |
2205 API d_t0_on; | |
2206 API d_t0_off; | |
2207 API d_t1_on; | |
2208 API d_t1_off; | |
2209 API d_t2_on; | |
2210 API d_t2_off; | |
2211 API d_k_x1_kt0; | |
2212 API d_k_x1_kt1; | |
2213 API d_dur_kb; | |
2214 | |
2215 // PLL...............................(MCU -> DSP). | |
2216 API d_pll_clkmod1; | |
2217 API d_pll_clkmod2; | |
2218 | |
2219 // DSP status returned..........(DSP --> MCU). | |
2220 API d_error_status; | |
2221 | |
2222 // RIF control.......................(MCU -> DSP). | |
2223 API d_spcx_rif; | |
2224 | |
2225 API d_shiftdl; | |
2226 API d_shiftul; | |
2227 | |
2228 API p_saec_prog; | |
2229 API p_aec_prog; | |
2230 API p_spenh_prog; | |
2231 | |
2232 API a_ovly[75]; | |
2233 API d_ra_conf; | |
2234 API d_ra_act; | |
2235 API d_ra_test; | |
2236 API d_ra_statu; | |
2237 API d_ra_statd; | |
2238 API d_fax; | |
2239 #if (SPEECH_RECO) | |
2240 API a_data_buf_ul[3]; | |
2241 API a_n_best_words[4]; // array of the 4 best words | |
2242 API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length) | |
2243 API sr_holes_2[6]; | |
2244 API a_data_buf_dl[37]; | |
2245 | |
2246 API a_hole[24]; | |
2247 | |
2248 API d_sched_mode_gprs_ovly; | |
2249 | |
2250 API fir_holes1[384]; | |
2251 API a_fir31_uplink[31]; | |
2252 API a_fir31_downlink[31]; | |
2253 API d_audio_init; | |
2254 API d_audio_status; | |
2255 | |
2256 API a_model[1041]; // array of the speech reco model | |
2257 #else | |
2258 API a_data_buf_ul[21]; | |
2259 API a_data_buf_dl[37]; | |
2260 | |
2261 API a_hole[24]; | |
2262 | |
2263 API d_sched_mode_gprs_ovly; | |
2264 | |
2265 API fir_holes1[384]; | |
2266 API a_fir31_uplink[31]; | |
2267 API a_fir31_downlink[31]; | |
2268 API d_audio_init; | |
2269 API d_audio_status; | |
2270 | |
2271 #if (L1_EOTD ==1) | |
2272 API a_eotd_hole[369]; | |
2273 | |
2274 API d_eotd_first; | |
2275 API d_eotd_max; | |
2276 API d_eotd_nrj_high; | |
2277 API d_eotd_nrj_low; | |
2278 API a_eotd_crosscor[18]; | |
2279 #endif | |
2280 #endif | |
2281 } | |
2282 T_NDB_MCU_DSP; | |
2283 | |
2284 | |
2285 #else // OTHER DSP CODE like 17 | |
2286 | |
2287 typedef struct | |
2288 { | |
2289 // Monitoring tasks control..........(MCU <- DSP) | |
2290 API d_fb_det; // FB detection result. (1 for FOUND). | |
2291 API d_fb_mode; // Mode for FB detection algorithm. | |
2292 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR). | |
2293 | |
2294 // CCCH/SACCH downlink information...(!!) | |
2295 API a_cd[15]; // Header + CCCH/SACCH downlink information. | |
2296 | |
2297 // FACCH downlink information........(!!) | |
2298 API a_fd[15]; // Header + FACCH downlink information. | |
2299 | |
2300 // Traffic downlink data frames......(!!) | |
2301 #if (DATA14_4 == 0) | |
2302 API a_dd_0[20]; // Header + DATA traffic downlink information, sub. chan. 0. | |
2303 API a_dd_1[20]; // Header + DATA traffic downlink information, sub. chan. 1. | |
2304 #endif | |
2305 #if (DATA14_4 == 1) | |
2306 API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0. | |
2307 API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1. | |
2308 #endif | |
2309 | |
2310 // CCCH/SACCH uplink information.....(!!) | |
2311 API a_cu[15]; // Header + CCCH/SACCH uplink information. | |
2312 | |
2313 #if (SPEECH_RECO) | |
2314 // FACCH downlink information........(!!) | |
2315 API a_fu[3]; // Header + FACCH uplink information | |
2316 // The size of this buffer is 15 word but some speech reco words | |
2317 // are overlayer with this buffer. This is the reason why the size is 3 instead of 15. | |
2318 API d_sr_status; // status of the DSP speech reco task | |
2319 API d_sr_param; // paramters for the DSP speech reco task: OOV threshold. | |
2320 API sr_hole1; // hole | |
2321 API d_sr_bit_exact_test; // bit exact test | |
2322 API d_sr_nb_words; // number of words used in the speech recognition task | |
2323 API d_sr_db_level; // estimate voice level in dB | |
2324 API d_sr_db_noise; // estimate noise in dB | |
2325 API d_sr_mod_size; // size of the model | |
2326 API sr_holes_1[4]; // hole | |
2327 #else | |
2328 // FACCH downlink information........(!!) | |
2329 API a_fu[15]; // Header + FACCH uplink information | |
2330 #endif | |
2331 | |
2332 // Traffic uplink data frames........(!!) | |
2333 #if (DATA14_4 == 0) | |
2334 API a_du_0[20]; // Header + DATA traffic uplink information, sub. chan. 0. | |
2335 API a_du_1[20]; // Header + DATA traffic uplink information, sub. chan. 1. | |
2336 #endif | |
2337 #if (DATA14_4 == 1) | |
2338 API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0. | |
2339 API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1. | |
2340 #endif | |
2341 | |
2342 // Random access.....................(MCU -> DSP). | |
2343 API d_rach; // RACH information. | |
2344 | |
2345 //...................................(MCU -> DSP). | |
2346 API d_a5mode; // Encryption Mode. | |
2347 API a_kc[4]; // Encryption Key Code. | |
2348 API d_tch_mode; // TCH mode register. | |
2349 // bit [0..1] -> b_dai_mode. | |
2350 // bit [2] -> b_dtx. | |
2351 | |
2352 // OMEGA...........................(MCU -> DSP). | |
2353 | |
2354 #if ((ANALOG == 1) || (ANALOG == 2)) | |
2355 API a_ramp[16]; | |
2356 #if (MELODY_E1) | |
2357 API d_melo_osc_used; | |
2358 API d_melo_osc_active; | |
2359 API a_melo_note0[4]; | |
2360 API a_melo_note1[4]; | |
2361 API a_melo_note2[4]; | |
2362 API a_melo_note3[4]; | |
2363 API a_melo_note4[4]; | |
2364 API a_melo_note5[4]; | |
2365 API a_melo_note6[4]; | |
2366 API a_melo_note7[4]; | |
2367 #if (DSP == 17) | |
2368 // selection of the melody format | |
2369 API d_dco_type; // Tide | |
2370 API p_start_IQ; | |
2371 API d_level_off; | |
2372 API d_dco_dbg; | |
2373 API d_tide_resa; | |
2374 API d_asynch_margin; // Perseus Asynch Audio Workaround | |
2375 API hole[4]; | |
2376 #else | |
2377 API d_melody_selection; | |
2378 API holes[9]; | |
2379 #endif | |
2380 #else // NO MELODY E1 | |
2381 // selection of the melody format | |
2382 #if (DSP == 17) | |
2383 API holes[34]; // 34 unused holes. | |
2384 API d_dco_type; // Tide | |
2385 API p_start_IQ; | |
2386 API d_level_off; | |
2387 API d_dco_dbg; | |
2388 API d_tide_resa; | |
2389 API d_asynch_margin; // Perseus Asynch Audio Workaround | |
2390 API hole[4] | |
2391 #else | |
2392 // selection of the melody format | |
2393 API d_melody_selection; | |
2394 API holes[43]; // 43 unused holes. | |
2395 #endif | |
2396 #endif | |
2397 API d_debug3; | |
2398 API d_debug2; | |
2399 API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega | |
2400 API d_afcctladd; | |
2401 API d_vbuctrl; | |
2402 API d_vbdctrl; | |
2403 API d_apcdel1; | |
2404 API d_aec_ctrl; | |
2405 API d_apcoff; | |
2406 API d_bulioff; | |
2407 API d_bulqoff; | |
2408 API d_dai_onoff; | |
2409 API d_auxdac; | |
2410 #if (ANALOG == 1) | |
2411 API d_vbctrl; | |
2412 #elif (ANALOG == 2) | |
2413 API d_vbctrl1; | |
2414 #endif | |
2415 API d_bbctrl; | |
2416 | |
2417 #else | |
2418 #error DSPCODE not supported with given ANALOG | |
2419 #endif //(ANALOG)1, 2 | |
2420 //...................................(MCU -> DSP). | |
2421 API a_sch26[5]; // Header + SB information, array of 5 words. | |
2422 | |
2423 // TONES.............................(MCU -> DSP) | |
2424 API d_toneskb_init; | |
2425 API d_toneskb_status; | |
2426 API d_k_x1_t0; | |
2427 API d_k_x1_t1; | |
2428 API d_k_x1_t2; | |
2429 API d_pe_rep; | |
2430 API d_pe_off; | |
2431 API d_se_off; | |
2432 API d_bu_off; | |
2433 API d_t0_on; | |
2434 API d_t0_off; | |
2435 API d_t1_on; | |
2436 API d_t1_off; | |
2437 API d_t2_on; | |
2438 API d_t2_off; | |
2439 API d_k_x1_kt0; | |
2440 API d_k_x1_kt1; | |
2441 API d_dur_kb; | |
2442 | |
2443 // PLL...............................(MCU -> DSP). | |
2444 API d_pll_clkmod1; | |
2445 API d_pll_clkmod2; | |
2446 | |
2447 // DSP status returned..........(DSP --> MCU). | |
2448 API d_error_status; | |
2449 | |
2450 // RIF control.......................(MCU -> DSP). | |
2451 API d_spcx_rif; | |
2452 | |
2453 API d_shiftdl; | |
2454 API d_shiftul; | |
2455 | |
2456 #if (AEC == 1) | |
2457 // AEC control.......................(MCU -> DSP). | |
2458 #if (VOC == FR_EFR) | |
2459 API p_aec_init; | |
2460 API p_aec_prog; | |
2461 API p_spenh_init; | |
2462 API p_spenh_prog; | |
2463 #endif | |
2464 | |
2465 #if (VOC == FR_HR_EFR) | |
2466 API p_saec_prog; | |
2467 API p_aec_prog; | |
2468 API p_spenh_prog; | |
2469 #endif | |
2470 #endif | |
2471 | |
2472 API a_ovly[75]; | |
2473 API d_ra_conf; | |
2474 API d_ra_act; | |
2475 API d_ra_test; | |
2476 API d_ra_statu; | |
2477 API d_ra_statd; | |
2478 API d_fax; | |
2479 #if (SPEECH_RECO) | |
2480 API a_data_buf_ul[3]; | |
2481 API a_n_best_words[4]; // array of the 4 best words | |
2482 API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length) | |
2483 API sr_holes_2[6]; | |
2484 API a_data_buf_dl[37]; | |
2485 | |
2486 API fir_holes1[409]; | |
2487 API a_fir31_uplink[31]; | |
2488 API a_fir31_downlink[31]; | |
2489 API d_audio_init; | |
2490 API d_audio_status; | |
2491 API a_model[1041]; // array of the speech reco model | |
2492 #else | |
2493 API a_data_buf_ul[21]; | |
2494 API a_data_buf_dl[37]; | |
2495 | |
2496 API fir_holes1[409]; | |
2497 API a_fir31_uplink[31]; | |
2498 API a_fir31_downlink[31]; | |
2499 API d_audio_init; | |
2500 API d_audio_status; | |
2501 #endif | |
2502 } | |
2503 T_NDB_MCU_DSP; | |
2504 #endif | |
2505 | |
2506 #if (DSP >= 34) | |
2507 typedef struct | |
2508 { | |
2509 API_SIGNED d_transfer_rate; // 0x0C31 | |
2510 | |
2511 // Common GSM/GPRS | |
2512 // These words specified the latencies to applies on some peripherics | |
2513 API_SIGNED d_lat_mcu_bridge; | |
2514 API_SIGNED d_lat_mcu_hom2sam; | |
2515 API_SIGNED d_lat_mcu_bef_fast_access; | |
2516 API_SIGNED d_lat_dsp_after_sam; | |
2517 | |
2518 // DSP Start address | |
2519 API_SIGNED d_gprs_install_address; | |
2520 | |
2521 API_SIGNED d_misc_config; | |
2522 | |
2523 API_SIGNED d_cn_sw_workaround; | |
2524 | |
2525 API_SIGNED d_hole2_param[4]; // 0x0C39 | |
2526 | |
2527 //...................................Frequency Burst. | |
2528 API_SIGNED d_fb_margin_beg; // 0x0C3D | |
2529 API_SIGNED d_fb_margin_end; | |
2530 API_SIGNED d_nsubb_idle; | |
2531 API_SIGNED d_nsubb_dedic; | |
2532 API_SIGNED d_fb_thr_det_iacq; | |
2533 API_SIGNED d_fb_thr_det_track; | |
2534 //...................................Demodulation. | |
2535 API_SIGNED d_dc_off_thres; | |
2536 API_SIGNED d_dummy_thres; | |
2537 API_SIGNED d_dem_pond_gewl; | |
2538 API_SIGNED d_dem_pond_red; | |
2539 | |
2540 //...................................TCH Full Speech. | |
2541 API_SIGNED d_maccthresh1; | |
2542 API_SIGNED d_mldt; | |
2543 API_SIGNED d_maccthresh; | |
2544 API_SIGNED d_gu; | |
2545 API_SIGNED d_go; | |
2546 API_SIGNED d_attmax; | |
2547 API_SIGNED d_sm; | |
2548 API_SIGNED d_b; | |
2549 | |
2550 // V42Bis module | |
2551 API_SIGNED d_v42b_switch_hyst; | |
2552 API_SIGNED d_v42b_switch_min; | |
2553 API_SIGNED d_v42b_switch_max; | |
2554 API_SIGNED d_v42b_reset_delay; | |
2555 | |
2556 //...................................TCH Half Speech. | |
2557 API_SIGNED d_ldT_hr; // 0x0C53 | |
2558 API_SIGNED d_maccthresh_hr; | |
2559 API_SIGNED d_maccthresh1_hr; | |
2560 API_SIGNED d_gu_hr; | |
2561 API_SIGNED d_go_hr; | |
2562 API_SIGNED d_b_hr; | |
2563 API_SIGNED d_sm_hr; | |
2564 API_SIGNED d_attmax_hr; | |
2565 | |
2566 //...................................TCH Enhanced FR Speech. | |
2567 API_SIGNED c_mldt_efr; | |
2568 API_SIGNED c_maccthresh_efr; | |
2569 API_SIGNED c_maccthresh1_efr; | |
2570 API_SIGNED c_gu_efr; | |
2571 API_SIGNED c_go_efr; | |
2572 API_SIGNED c_b_efr; | |
2573 API_SIGNED c_sm_efr; | |
2574 API_SIGNED c_attmax_efr; | |
2575 | |
2576 //...................................CHED | |
2577 API_SIGNED d_sd_min_thr_tchfs; // 0x0C63 | |
2578 API_SIGNED d_ma_min_thr_tchfs; | |
2579 API_SIGNED d_md_max_thr_tchfs; | |
2580 API_SIGNED d_md1_max_thr_tchfs; | |
2581 | |
2582 API_SIGNED d_sd_min_thr_tchhs; | |
2583 API_SIGNED d_ma_min_thr_tchhs; | |
2584 API_SIGNED d_sd_av_thr_tchhs; | |
2585 API_SIGNED d_md_max_thr_tchhs; | |
2586 API_SIGNED d_md1_max_thr_tchhs; | |
2587 | |
2588 API_SIGNED d_sd_min_thr_tchefs; | |
2589 API_SIGNED d_ma_min_thr_tchefs; | |
2590 API_SIGNED d_md_max_thr_tchefs; | |
2591 API_SIGNED d_md1_max_thr_tchefs; | |
2592 | |
2593 API_SIGNED d_wed_fil_ini; | |
2594 API_SIGNED d_wed_fil_tc; | |
2595 API_SIGNED d_x_min; | |
2596 API_SIGNED d_x_max; | |
2597 API_SIGNED d_slope; | |
2598 API_SIGNED d_y_min; | |
2599 API_SIGNED d_y_max; | |
2600 API_SIGNED d_wed_diff_threshold; | |
2601 API_SIGNED d_mabfi_min_thr_tchhs; | |
2602 | |
2603 // FACCH module | |
2604 API_SIGNED d_facch_thr; // 0x0C79 | |
2605 | |
2606 // IDS module | |
2607 API_SIGNED d_max_ovsp_ul; // | |
2608 API_SIGNED d_sync_thres; | |
2609 API_SIGNED d_idle_thres; | |
2610 API_SIGNED d_m1_thres; | |
2611 API_SIGNED d_max_ovsp_dl; | |
2612 API_SIGNED d_gsm_bgd_mgt; | |
2613 | |
2614 // FIR coefficients | |
2615 API a_fir_holes[4]; | |
2616 API a_fir31_uplink[31]; // 0x0C84 | |
2617 API a_fir31_downlink[31]; | |
2618 } | |
2619 T_PARAM_MCU_DSP; | |
2620 #elif (DSP == 33) | |
2621 typedef struct | |
2622 { | |
2623 API_SIGNED d_transfer_rate; | |
2624 | |
2625 // Common GSM/GPRS | |
2626 // These words specified the latencies to applies on some peripherics | |
2627 API_SIGNED d_lat_mcu_bridge; | |
2628 API_SIGNED d_lat_mcu_hom2sam; | |
2629 API_SIGNED d_lat_mcu_bef_fast_access; | |
2630 API_SIGNED d_lat_dsp_after_sam; | |
2631 | |
2632 // DSP Start address | |
2633 API_SIGNED d_gprs_install_address; | |
2634 | |
2635 API_SIGNED d_misc_config; | |
2636 | |
2637 API_SIGNED d_cn_sw_workaround; | |
2638 | |
2639 #if DCO_ALGO | |
2640 API_SIGNED d_cn_dco_param; | |
2641 | |
2642 API_SIGNED d_hole2_param[3]; | |
2643 #else | |
2644 API_SIGNED d_hole2_param[4]; | |
2645 #endif | |
2646 | |
2647 //...................................Frequency Burst. | |
2648 API_SIGNED d_fb_margin_beg; | |
2649 API_SIGNED d_fb_margin_end; | |
2650 API_SIGNED d_nsubb_idle; | |
2651 API_SIGNED d_nsubb_dedic; | |
2652 API_SIGNED d_fb_thr_det_iacq; | |
2653 API_SIGNED d_fb_thr_det_track; | |
2654 //...................................Demodulation. | |
2655 API_SIGNED d_dc_off_thres; | |
2656 API_SIGNED d_dummy_thres; | |
2657 API_SIGNED d_dem_pond_gewl; | |
2658 API_SIGNED d_dem_pond_red; | |
2659 | |
2660 //...................................TCH Full Speech. | |
2661 API_SIGNED d_maccthresh1; | |
2662 API_SIGNED d_mldt; | |
2663 API_SIGNED d_maccthresh; | |
2664 API_SIGNED d_gu; | |
2665 API_SIGNED d_go; | |
2666 API_SIGNED d_attmax; | |
2667 API_SIGNED d_sm; | |
2668 API_SIGNED d_b; | |
2669 | |
2670 // V42Bis module | |
2671 API_SIGNED d_v42b_switch_hyst; | |
2672 API_SIGNED d_v42b_switch_min; | |
2673 API_SIGNED d_v42b_switch_max; | |
2674 API_SIGNED d_v42b_reset_delay; | |
2675 | |
2676 //...................................TCH Half Speech. | |
2677 API_SIGNED d_ldT_hr; | |
2678 API_SIGNED d_maccthresh_hr; | |
2679 API_SIGNED d_maccthresh1_hr; | |
2680 API_SIGNED d_gu_hr; | |
2681 API_SIGNED d_go_hr; | |
2682 API_SIGNED d_b_hr; | |
2683 API_SIGNED d_sm_hr; | |
2684 API_SIGNED d_attmax_hr; | |
2685 | |
2686 //...................................TCH Enhanced FR Speech. | |
2687 API_SIGNED c_mldt_efr; | |
2688 API_SIGNED c_maccthresh_efr; | |
2689 API_SIGNED c_maccthresh1_efr; | |
2690 API_SIGNED c_gu_efr; | |
2691 API_SIGNED c_go_efr; | |
2692 API_SIGNED c_b_efr; | |
2693 API_SIGNED c_sm_efr; | |
2694 API_SIGNED c_attmax_efr; | |
2695 | |
2696 //...................................CHED | |
2697 API_SIGNED d_sd_min_thr_tchfs; | |
2698 API_SIGNED d_ma_min_thr_tchfs; | |
2699 API_SIGNED d_md_max_thr_tchfs; | |
2700 API_SIGNED d_md1_max_thr_tchfs; | |
2701 | |
2702 API_SIGNED d_sd_min_thr_tchhs; | |
2703 API_SIGNED d_ma_min_thr_tchhs; | |
2704 API_SIGNED d_sd_av_thr_tchhs; | |
2705 API_SIGNED d_md_max_thr_tchhs; | |
2706 API_SIGNED d_md1_max_thr_tchhs; | |
2707 | |
2708 API_SIGNED d_sd_min_thr_tchefs; | |
2709 API_SIGNED d_ma_min_thr_tchefs; | |
2710 API_SIGNED d_md_max_thr_tchefs; | |
2711 API_SIGNED d_md1_max_thr_tchefs; | |
2712 | |
2713 API_SIGNED d_wed_fil_ini; | |
2714 API_SIGNED d_wed_fil_tc; | |
2715 API_SIGNED d_x_min; | |
2716 API_SIGNED d_x_max; | |
2717 API_SIGNED d_slope; | |
2718 API_SIGNED d_y_min; | |
2719 API_SIGNED d_y_max; | |
2720 API_SIGNED d_wed_diff_threshold; | |
2721 API_SIGNED d_mabfi_min_thr_tchhs; | |
2722 | |
2723 // FACCH module | |
2724 API_SIGNED d_facch_thr; | |
2725 | |
2726 // IDS module | |
2727 API_SIGNED d_max_ovsp_ul; | |
2728 API_SIGNED d_sync_thres; | |
2729 API_SIGNED d_idle_thres; | |
2730 API_SIGNED d_m1_thres; | |
2731 API_SIGNED d_max_ovsp_dl; | |
2732 API_SIGNED d_gsm_bgd_mgt; | |
2733 | |
2734 // FIR coefficients | |
2735 API a_fir_holes[4]; | |
2736 API a_fir31_uplink[31]; | |
2737 API a_fir31_downlink[31]; | |
2738 } | |
2739 T_PARAM_MCU_DSP; | |
2740 | |
2741 #else | |
2742 | |
2743 typedef struct | |
2744 { | |
2745 //...................................Frequency Burst. | |
2746 API_SIGNED d_nsubb_idle; | |
2747 API_SIGNED d_nsubb_dedic; | |
2748 API_SIGNED d_fb_thr_det_iacq; | |
2749 API_SIGNED d_fb_thr_det_track; | |
2750 //...................................Demodulation. | |
2751 API_SIGNED d_dc_off_thres; | |
2752 API_SIGNED d_dummy_thres; | |
2753 API_SIGNED d_dem_pond_gewl; | |
2754 API_SIGNED d_dem_pond_red; | |
2755 API_SIGNED hole[1]; | |
2756 API_SIGNED d_transfer_rate; | |
2757 //...................................TCH Full Speech. | |
2758 API_SIGNED d_maccthresh1; | |
2759 API_SIGNED d_mldt; | |
2760 API_SIGNED d_maccthresh; | |
2761 API_SIGNED d_gu; | |
2762 API_SIGNED d_go; | |
2763 API_SIGNED d_attmax; | |
2764 API_SIGNED d_sm; | |
2765 API_SIGNED d_b; | |
2766 | |
2767 #if (VOC == FR_HR) || (VOC == FR_HR_EFR) | |
2768 //...................................TCH Half Speech. | |
2769 API_SIGNED d_ldT_hr; | |
2770 API_SIGNED d_maccthresh_hr; | |
2771 API_SIGNED d_maccthresh1_hr; | |
2772 API_SIGNED d_gu_hr; | |
2773 API_SIGNED d_go_hr; | |
2774 API_SIGNED d_b_hr; | |
2775 API_SIGNED d_sm_hr; | |
2776 API_SIGNED d_attmax_hr; | |
2777 #endif | |
2778 | |
2779 #if (VOC == FR_EFR) || (VOC == FR_HR_EFR) | |
2780 //...................................TCH Enhanced FR Speech. | |
2781 API_SIGNED c_mldt_efr; | |
2782 API_SIGNED c_maccthresh_efr; | |
2783 API_SIGNED c_maccthresh1_efr; | |
2784 API_SIGNED c_gu_efr; | |
2785 API_SIGNED c_go_efr; | |
2786 API_SIGNED c_b_efr; | |
2787 API_SIGNED c_sm_efr; | |
2788 API_SIGNED c_attmax_efr; | |
2789 #endif | |
2790 | |
2791 //...................................TCH Full Speech. | |
2792 API_SIGNED d_sd_min_thr_tchfs; | |
2793 API_SIGNED d_ma_min_thr_tchfs; | |
2794 API_SIGNED d_md_max_thr_tchfs; | |
2795 API_SIGNED d_md1_max_thr_tchfs; | |
2796 | |
2797 #if (VOC == FR) || (VOC == FR_HR) || (VOC == FR_HR_EFR) | |
2798 //...................................TCH Half Speech. | |
2799 API_SIGNED d_sd_min_thr_tchhs; | |
2800 API_SIGNED d_ma_min_thr_tchhs; | |
2801 API_SIGNED d_sd_av_thr_tchhs; | |
2802 API_SIGNED d_md_max_thr_tchhs; | |
2803 API_SIGNED d_md1_max_thr_tchhs; | |
2804 #endif | |
2805 | |
2806 #if (VOC == FR_EFR) || (VOC == FR_HR_EFR) | |
2807 //...................................TCH Enhanced FR Speech. | |
2808 API_SIGNED d_sd_min_thr_tchefs; //(24L *C_POND_RED) | |
2809 API_SIGNED d_ma_min_thr_tchefs; //(1200L *C_POND_RED) | |
2810 API_SIGNED d_md_max_thr_tchefs; //(2000L *C_POND_RED) | |
2811 API_SIGNED d_md1_max_thr_tchefs; //(160L *C_POND_RED) | |
2812 API_SIGNED d_hole1; | |
2813 #endif | |
2814 | |
2815 API_SIGNED d_wed_fil_ini; | |
2816 API_SIGNED d_wed_fil_tc; | |
2817 API_SIGNED d_x_min; | |
2818 API_SIGNED d_x_max; | |
2819 API_SIGNED d_slope; | |
2820 API_SIGNED d_y_min; | |
2821 API_SIGNED d_y_max; | |
2822 API_SIGNED d_wed_diff_threshold; | |
2823 API_SIGNED d_mabfi_min_thr_tchhs; | |
2824 API_SIGNED d_facch_thr; | |
2825 API_SIGNED d_dsp_test; | |
2826 | |
2827 | |
2828 #if (DATA14_4 == 0 ) || (VOC == FR_HR_EFR) | |
2829 API_SIGNED d_patch_addr1; | |
2830 API_SIGNED d_patch_data1; | |
2831 API_SIGNED d_patch_addr2; | |
2832 API_SIGNED d_patch_data2; | |
2833 API_SIGNED d_patch_addr3; | |
2834 API_SIGNED d_patch_data3; | |
2835 API_SIGNED d_patch_addr4; | |
2836 API_SIGNED d_patch_data4; | |
2837 #endif | |
2838 | |
2839 //................................... | |
2840 API_SIGNED d_version_number; // DSP patch version | |
2841 API_SIGNED d_ti_version; // customer number. No more used since 1.5 | |
2842 | |
2843 API_SIGNED d_dsp_page; | |
2844 | |
2845 #if IDS | |
2846 API_SIGNED d_max_ovsp_ul; | |
2847 API_SIGNED d_sync_thres; | |
2848 API_SIGNED d_idle_thres; | |
2849 API_SIGNED d_m1_thres; | |
2850 API_SIGNED d_max_ovsp_dl; | |
2851 #endif | |
2852 | |
2853 | |
2854 } | |
2855 T_PARAM_MCU_DSP; | |
2856 #endif | |
2857 | |
2858 #if (DSP_DEBUG_TRACE_ENABLE == 1) | |
2859 typedef struct | |
2860 { | |
2861 API d_debug_ptr_begin; | |
2862 API d_debug_ptr_end; | |
2863 } | |
2864 T_DB2_DSP_TO_MCU; | |
2865 #endif | |
2866 | |
2867 /*************************************************************/ | |
2868 /* Time informations... */ | |
2869 /*************************************************************/ | |
2870 /* */ | |
2871 /*************************************************************/ | |
2872 typedef struct | |
2873 { | |
2874 UWORD32 fn; // FN count | |
2875 UWORD16 t1; // FN div (26*51), (0..2047). | |
2876 UWORD8 t2; // FN modulo 26. | |
2877 UWORD8 t3; // FN modulo 51. | |
2878 UWORD8 tc; // Scell: TC | |
2879 UWORD8 fn_in_report; // FN modulo 102 or 104. | |
2880 UWORD16 fn_mod42432; // FN modulo 42432. | |
2881 UWORD8 fn_mod13; // FN modulo 13. | |
2882 UWORD8 fn_mod13_mod4; // FN modulo 13 modulo 4. | |
2883 #if L1_GPRS | |
2884 UWORD8 fn_mod52; // FN modulo 52. | |
2885 UWORD8 fn_mod104; // FN modulo 104. | |
2886 UWORD32 block_id; // Block ID | |
2887 #endif | |
2888 } | |
2889 T_TIME_INFO; | |
2890 | |
2891 /*************************************************************/ | |
2892 /* Idle mode tasks information... */ | |
2893 /*************************************************************/ | |
2894 /* must be filled according to Idle parameters... */ | |
2895 /* ... */ | |
2896 /*************************************************************/ | |
2897 typedef struct | |
2898 { | |
2899 UWORD8 pg_position; // Paging block starting frame. | |
2900 UWORD8 extpg_position; // Extended Paging block starting frame. | |
2901 } | |
2902 T_IDLE_TASK_INFO; | |
2903 | |
2904 /*************************************************************/ | |
2905 /* SDCCH information structure. */ | |
2906 /*************************************************************/ | |
2907 /* */ | |
2908 /* */ | |
2909 /*************************************************************/ | |
2910 typedef struct | |
2911 { | |
2912 UWORD8 dl_sdcch_position; | |
2913 UWORD8 dl_sacch_position; | |
2914 UWORD8 ul_sdcch_position; | |
2915 UWORD8 ul_sacch_position; | |
2916 UWORD8 mon_area_position; | |
2917 } | |
2918 T_SDCCH_DESC; | |
2919 | |
2920 /*************************************************************/ | |
2921 /* Random Access Task information structure. */ | |
2922 /*************************************************************/ | |
2923 /* */ | |
2924 /* */ | |
2925 /*************************************************************/ | |
2926 typedef struct | |
2927 { | |
2928 WORD32 rand; // 16 bit signed !! | |
2929 UWORD8 channel_request; | |
2930 UWORD8 ra_to_ctrl; | |
2931 UWORD8 ra_num; | |
2932 } | |
2933 T_RA_TASK_INFO; | |
2934 | |
2935 /***************************************************************************************/ | |
2936 /* Measurement info element for last input level table */ | |
2937 /***************************************************************************************/ | |
2938 typedef struct | |
2939 { | |
2940 UWORD8 lna_off; // 1 if lna switch is off. | |
2941 UWORD8 input_level; // last measured input level in dbm. | |
2942 } | |
2943 T_INPUT_LEVEL; | |
2944 | |
2945 /***************************************************************************************/ | |
2946 /* Measurement info element for Neighbor cell lists. */ | |
2947 /***************************************************************************************/ | |
2948 typedef struct | |
2949 { | |
2950 UWORD16 radio_freq; // carrier id. | |
2951 WORD32 acc; // Accumulation of measurements already performed. | |
2952 UWORD8 nbr_meas; | |
2953 } | |
2954 T_MEAS_INFO; | |
2955 | |
2956 typedef struct | |
2957 { | |
2958 UWORD16 bcch_freq; | |
2959 WORD16 rxlev_acc; | |
2960 UWORD8 rxlev_nbr_meas; | |
2961 } | |
2962 T5_CELL_MEAS; | |
2963 | |
2964 typedef struct | |
2965 { | |
2966 T5_CELL_MEAS A[33]; | |
2967 } | |
2968 T5_NCELL_MEAS; | |
2969 | |
2970 /***************************************************************************************/ | |
2971 /* Measurement info element serving cell in dedicated mode */ | |
2972 /***************************************************************************************/ | |
2973 typedef struct | |
2974 { | |
2975 WORD32 acc_sub; // Subset: accu. rxlev meas. | |
2976 UWORD32 nbr_meas_sub; // Subset: nbr meas. of rxlev. | |
2977 UWORD32 qual_acc_full; // Fullset: accu. rxqual meas. | |
2978 UWORD32 qual_acc_sub; // Subset: accu. rxqual meas. | |
2979 UWORD32 qual_nbr_meas_full; // Fullset: nbr meas. of rxqual. | |
2980 UWORD32 qual_nbr_meas_sub; // Subset: nbr meas. of rxqual. | |
2981 UWORD8 dtx_used; // Set when DTX as been used in current reporting period. | |
2982 } | |
2983 T_SMEAS; | |
2984 | |
2985 | |
2986 #if REL99 | |
2987 #if FF_EMR | |
2988 typedef struct | |
2989 { | |
2990 | |
2991 WORD16 rxlev_val_acc; // Accumulated value of RXLEV_VAL | |
2992 UWORD8 rxlev_val_nbr_meas; // Number of RXLEV_VAL value accumulated on block bases | |
2993 UWORD8 nbr_rcvd_blocks; // Number of correctly decoded blocks excluding SACCH FACCH etc Refer 05.08 | |
2994 UWORD32 mean_bep_block_acc; // Accumulated value of MEAN_BEP | |
2995 UWORD16 cv_bep_block_acc; // Accumulated value of CV_BEP | |
2996 UWORD8 mean_bep_block_num; // Number of blocks over MEAN_BEP is accumulated. | |
2997 UWORD8 cv_bep_block_num; // Number of blocks over CV_BEP is accumulated. | |
2998 } | |
2999 T_SMEAS_EMR; | |
3000 | |
3001 typedef struct | |
3002 { | |
3003 UWORD8 task; // task id (TCHTH, TCHTF, DDL, ADL, TCHA) | |
3004 UWORD8 burst_id; // burst ID only used for SDCCH. | |
3005 UWORD8 channel_mode; // channel mode in case of half / full rate | |
3006 UWORD8 subchannel; // subchannel number | |
3007 UWORD32 normalised_fn_mod13_mod4; // used to find block boundary in case of half rate | |
3008 BOOL facch_present; // necessary for processing to indicate reception of Facch | |
3009 BOOL facch_fire1; // necessary for processing to indicate good/bad reception of Facch | |
3010 UWORD8 a_ntd; // used for Data : FCS OK/FCS KO | |
3011 UWORD8 a_dd_0_blud; // check data/speech block presence on sub 0 | |
3012 UWORD8 a_dd_0_bfi; // check data/speech block integrity on sub 0 | |
3013 UWORD8 a_dd_1_blud; // check data/speech block presence on sub 1 | |
3014 UWORD8 a_dd_1_bfi; // check data/speech block integrity on sub 1 | |
3015 UWORD8 b_m1; // used for Data 14.4 M1 = 1 for second half block RLP | |
3016 UWORD8 b_f48blk_dl; // used for Data 4.8 : = 1 for second half block RLP | |
3017 UWORD8 b_ce; // used for Data : transparent / not transparent | |
3018 UWORD8 a_cd_fire1; // check SDCCH bloch integrity | |
3019 UWORD8 sid_present_sub0; // check sid present on sub 0 | |
3020 UWORD8 sid_present_sub1; // check sid present on sub 1 | |
3021 #if (AMR ==1) | |
3022 BOOL amr_facch_present; // necessary for AMR processing to indicate reception of Facch | |
3023 BOOL amr_facch_fire1; // necessary for AMR processing to indicate good/bad reception of Facch | |
3024 UWORD8 b_ratscch_blud; // check ratscch present | |
3025 UWORD8 ratscch_rxtype; // check type of AMR block | |
3026 UWORD8 amr_rx_type_sub0; // AMR type on sub 0 | |
3027 UWORD8 amr_rx_type_sub1; // AMR type on sub 1 | |
3028 #endif | |
3029 } | |
3030 T_EMR_PARAMS; | |
3031 #endif //FF_EMR | |
3032 #endif //REL99 | |
3033 | |
3034 /***************************************************************************************/ | |
3035 /* */ | |
3036 /***************************************************************************************/ | |
3037 typedef struct | |
3038 { | |
3039 UWORD8 new_status; | |
3040 UWORD8 current_status; | |
3041 WORD32 time_to_exec; | |
3042 } | |
3043 T_TASK_STATUS; | |
3044 | |
3045 /***************************************************************************************/ | |
3046 /* Cell/Carrier info: identity, RX level measurement, time info, gain controle info. */ | |
3047 /***************************************************************************************/ | |
3048 typedef struct | |
3049 { | |
3050 // Carrier/Cell Identity. | |
3051 UWORD16 radio_freq; // carrier id. | |
3052 WORD32 bsic; // BSIC. | |
3053 | |
3054 // Time difference information. | |
3055 UWORD32 fn_offset; // offset between fn of this NCELL and the SCELL fn. | |
3056 UWORD32 time_alignmt; // time alignment. | |
3057 | |
3058 // Receive Level Measurement info. structure. | |
3059 T_MEAS_INFO meas; | |
3060 T_INPUT_LEVEL traffic_meas; | |
3061 T_INPUT_LEVEL traffic_meas_beacon; | |
3062 | |
3063 // Beacon frequency FIFO | |
3064 UWORD8 buff_beacon[4]; | |
3065 | |
3066 #if L1_GPRS | |
3067 // Receive Level measurements in packet transfer mode | |
3068 // Daughter frequencies info. | |
3069 T_INPUT_LEVEL transfer_meas; | |
3070 | |
3071 // Power reduction on serving cell PCCCH / PBCCH | |
3072 UWORD8 pb; | |
3073 #endif | |
3074 | |
3075 // Number of unsuccessfull attempt on SB reading. | |
3076 UWORD8 attempt_count; | |
3077 | |
3078 // System information bitmap. | |
3079 UWORD32 si_bit_map; // System info. bitmap used for BCCH reading. | |
3080 } | |
3081 T_CELL_INFO; | |
3082 | |
3083 | |
3084 typedef struct | |
3085 { | |
3086 UWORD16 A[32+1]; | |
3087 } | |
3088 TC_CHAN_LIST; | |
3089 | |
3090 | |
3091 typedef struct | |
3092 { | |
3093 UWORD8 num_of_chans; | |
3094 TC_CHAN_LIST chan_list; | |
3095 BOOL pwrc; | |
3096 BOOL dtx_allowed; | |
3097 UWORD8 ba_id; | |
3098 } | |
3099 T_NEW_BA_LIST; | |
3100 | |
3101 | |
3102 typedef struct | |
3103 { | |
3104 UWORD8 ba_id; // BA list identifier. | |
3105 | |
3106 UWORD32 nbr_carrier; // number of carriers in the BA list. | |
3107 UWORD8 np_ctrl; // Tels the meas_manager which PCH burst has been controled. | |
3108 | |
3109 UWORD8 first_index; // First BA index measured in current session. | |
3110 | |
3111 UWORD8 next_to_ctrl; // Carrier for next power measurement result. | |
3112 UWORD8 next_to_read; // Measurement session time spent. | |
3113 | |
3114 UWORD8 ms_ctrl; | |
3115 UWORD8 ms_ctrl_d; | |
3116 UWORD8 ms_ctrl_dd; | |
3117 | |
3118 UWORD8 used_il [C_BA_PM_MEAS]; | |
3119 UWORD8 used_il_d [C_BA_PM_MEAS]; | |
3120 UWORD8 used_il_dd[C_BA_PM_MEAS]; | |
3121 | |
3122 UWORD8 used_lna [C_BA_PM_MEAS]; | |
3123 UWORD8 used_lna_d [C_BA_PM_MEAS]; | |
3124 UWORD8 used_lna_dd[C_BA_PM_MEAS]; | |
3125 | |
3126 T_MEAS_INFO A[32+1]; // list of 32 neighbors + 1 serving. | |
3127 | |
3128 BOOL new_list_present; | |
3129 T_NEW_BA_LIST new_list; | |
3130 } | |
3131 T_BA_LIST; | |
3132 | |
3133 typedef struct | |
3134 { | |
3135 UWORD16 radio_freq; | |
3136 WORD16 accum_power_result; | |
3137 } | |
3138 T_POWER_ARRAY; | |
3139 | |
3140 typedef struct | |
3141 { | |
3142 UWORD16 power_array_size; | |
3143 T_POWER_ARRAY power_array[NBMAX_CARRIER]; | |
3144 } | |
3145 T_FULL_LIST_MEAS; | |
3146 | |
3147 typedef struct | |
3148 { | |
3149 UWORD32 nbr_sat_carrier_ctrl; // Nb of saturated carriers after a pm session in ctrl. | |
3150 UWORD32 nbr_sat_carrier_read; // Nb of saturated carriers after a pm session in read. | |
3151 | |
3152 UWORD8 meas_1st_pass_ctrl; // flag for 1st pass during a pm session in ctrl. | |
3153 UWORD8 meas_1st_pass_read; // flag for 1st pass during a pm session in read. | |
3154 | |
3155 UWORD32 next_to_ctrl; // Carrier for next power measurement result. | |
3156 UWORD32 next_to_read; // Measurement session time spent. | |
3157 | |
3158 UWORD8 ms_ctrl; | |
3159 UWORD8 ms_ctrl_d; | |
3160 UWORD8 ms_ctrl_dd; | |
3161 | |
3162 UWORD8 sat_flag[NBMAX_CARRIER]; | |
3163 // last measure was saturated, so not valid | |
3164 } | |
3165 T_FULL_LIST; | |
3166 | |
3167 /*************************************************************/ | |
3168 /* Dedicated channel information structure... */ | |
3169 /*************************************************************/ | |
3170 /* */ | |
3171 /*************************************************************/ | |
3172 typedef struct | |
3173 { | |
3174 T_CHANNEL_DESCRIPTION *desc_ptr; // Ptr to the Active channel description | |
3175 T_CHANNEL_DESCRIPTION desc; // Channel description for AFTER STI. | |
3176 T_CHANNEL_DESCRIPTION desc_bef_sti; // Channel description for BEFORE STI. | |
3177 UWORD8 mode; // Channel mode. | |
3178 UWORD8 tch_loop; // TCH loop mode. | |
3179 } | |
3180 T_CHANNEL_INFO; | |
3181 | |
3182 /*************************************************************/ | |
3183 /* Mobile allocation information structure... */ | |
3184 /*************************************************************/ | |
3185 /* */ | |
3186 /*************************************************************/ | |
3187 typedef struct | |
3188 { | |
3189 T_MOBILE_ALLOCATION *alist_ptr; // Ptr to the Active frequency list | |
3190 T_MOBILE_ALLOCATION freq_list; | |
3191 T_MOBILE_ALLOCATION freq_list_bef_sti; | |
3192 } | |
3193 T_MA_INFO; | |
3194 | |
3195 /*************************************************************/ | |
3196 /* Dedicated channel parameter structure... */ | |
3197 /*************************************************************/ | |
3198 /* */ | |
3199 /*************************************************************/ | |
3200 typedef struct | |
3201 { | |
3202 T_CHANNEL_INFO *achan_ptr; // Ptr to the Active channel (chan1 or chan2) | |
3203 T_CHANNEL_INFO chan1; | |
3204 T_CHANNEL_INFO chan2; | |
3205 | |
3206 T_MA_INFO ma; | |
3207 | |
3208 WORD32 serv_sti_fn; // Chan. desc. change time, serving domain.(-1 for not in use). | |
3209 WORD32 neig_sti_fn; // Chan. desc. change time, neighbor domain.(-1 for not in use). | |
3210 | |
3211 // Frequency redefinition ongoing flag. | |
3212 //------------------------------------- | |
3213 UWORD8 freq_redef_flag; // Set to TRUE when a Freq. Redef. must be confirmed. | |
3214 | |
3215 // Timing Advance management. | |
3216 //--------------------------- | |
3217 UWORD8 timing_advance; // Currently used TA. | |
3218 UWORD8 new_timing_advance; // New timing advance value to be used on 1st frame | |
3219 // of the next reporting period. | |
3220 // TXPWR management. | |
3221 //------------------- | |
3222 UWORD8 new_target_txpwr; // New Target value for TXPWR control algo. | |
3223 | |
3224 | |
3225 T_CELL_INFO cell_desc; // Ptr to the new serving cell to download. | |
3226 | |
3227 // DAI test mode... DTX allowed... | |
3228 UWORD8 dai_mode; // Dai test mode. | |
3229 BOOL dtx_allowed; // DTX allowed (flag). | |
3230 | |
3231 // Encryption... | |
3232 T_ENCRYPTION_KEY ciph_key; | |
3233 UWORD8 a5mode; | |
3234 | |
3235 // For handover... | |
3236 UWORD8 ho_acc; // Handover access (part of HO reference) | |
3237 WORD32 ho_acc_to_send; // Set to 4 for SYNC HO and to -1 for ASYNC HO. | |
3238 UWORD8 t3124; // Timer used in Async. Ho. | |
3239 | |
3240 #if ((REL99 == 1) && (FF_BHO == 1)) | |
3241 // For blind handover... | |
3242 BOOL report_time_diff; | |
3243 BOOL nci; | |
3244 UWORD8 real_time_difference; | |
3245 WORD32 HO_SignalCode; | |
3246 #endif | |
3247 | |
3248 // For DPAGC algorithms purpose | |
3249 UWORD8 G_all[DPAGC_FIFO_LEN]; | |
3250 UWORD8 G_DTX[DPAGC_FIFO_LEN]; | |
3251 #if (AMR == 1) | |
3252 UWORD8 G_amr[DPAGC_AMR_FIFO_LEN]; | |
3253 #endif | |
3254 | |
3255 #if IDS | |
3256 // IDS mode configuration | |
3257 UWORD8 ids_mode; // Information transfert capability coded on 2 bits | |
3258 // 0: speech | |
3259 // 1: data service | |
3260 // 2: fax service | |
3261 #endif | |
3262 #if (AMR == 1) | |
3263 T_AMR_CONFIGURATION amr_configuration; | |
3264 UWORD8 cmip; | |
3265 #endif | |
3266 } | |
3267 T_DEDIC_SET; | |
3268 | |
3269 /*************************************************************/ | |
3270 /* Dedicated channel parameter structure... */ | |
3271 /*************************************************************/ | |
3272 /* */ | |
3273 /*************************************************************/ | |
3274 typedef struct | |
3275 { | |
3276 T_DEDIC_SET *aset; // Ptr to the Active parameter set | |
3277 T_DEDIC_SET *fset; // Ptr to the Free parameter set | |
3278 T_DEDIC_SET set[2]; // Table of parameter set | |
3279 | |
3280 T_MPHC_CHANNEL_MODE_MODIFY_REQ mode_modif; // New mode for a given subchannel. | |
3281 WORD32 SignalCode; // Message name, set when a new param. set is given | |
3282 | |
3283 #if (FF_L1_TCH_VOCODER_CONTROL == 1) | |
3284 UWORD8 reset_sacch; // Flag to control SACCH reset (set during CHAN ASSIGN and Hand-overs) | |
3285 UWORD8 vocoder_on; // Flag to control execution of vocoder | |
3286 UWORD8 start_vocoder; // Flag to trigger start of vocoder (vocoder must be started with a synchro start) | |
3287 #endif | |
3288 | |
3289 UWORD8 sync_tch; // Flag used to synchronize TCH/F or TCH/H. | |
3290 UWORD8 reset_facch; // Flag used to reset FACCH buffer header on new IAS/CAS/handover | |
3291 UWORD8 stop_tch; // Flag used to stop TCH/F or TCH/H (VEGA pwrdown). | |
3292 | |
3293 UWORD16 radio_freq; // ARFCN buffer (returned by hopping algo). | |
3294 UWORD16 radio_freq_d; // 1 frame delayed ARFCN. | |
3295 UWORD16 radio_freq_dd; // 2 frames delayed ARFCN. | |
3296 | |
3297 BOOL pwrc; // Flag used to reject serving pwr meas. on beacon. | |
3298 | |
3299 BOOL handover_fail_mode; // Flag used to indicate that the L1 wait for an handover fail request | |
3300 #if (AMR == 1) | |
3301 BOOL sync_amr; // Flag used to tell to the DSP that a new AMR paramters is ready in the NDB. | |
3302 #endif // (AMR == 1) | |
3303 | |
3304 #if ((REL99 == 1) && (FF_BHO == 1)) | |
3305 // For blind handover... | |
3306 BOOL handover_type; | |
3307 BOOL long_rem_handover_type; | |
3308 UWORD16 bcch_carrier_of_nbr_cell; | |
3309 UWORD32 fn_offset; | |
3310 UWORD32 time_alignment; | |
3311 #endif | |
3312 } | |
3313 T_DEDIC_PARAM; | |
3314 | |
3315 /*************************************************************/ | |
3316 /* Power Management structure... */ | |
3317 /*************************************************************/ | |
3318 typedef struct | |
3319 { | |
3320 // fields of TST_SLEEP_REQ primitive .... | |
3321 UWORD8 mode_authorized; // NONE,SMALL,BIG,DEEP,ALL | |
3322 UWORD32 clocks; // clocks disabled in Big sleep | |
3323 | |
3324 // 32 Khz gauging .... | |
3325 UWORD8 gauging_task; // ACTIVE, INACTIVE,WAIT-IQ | |
3326 UWORD8 gaug_duration; // gauging task duration | |
3327 UWORD8 gaug_count; // gauging task duration compteur | |
3328 UWORD32 histo[SIZE_HIST][2];// gauging histogram | |
3329 UWORD8 enough_gaug; // enough good gauging | |
3330 UWORD8 paging_scheduled; // first Paging Frame | |
3331 | |
3332 // flags and variables for wake-up .... | |
3333 UWORD8 Os_ticks_required; // TRUE : Os ticks to recover | |
3334 UWORD8 frame_adjust; // TRUE : adjust 1 frame | |
3335 UWORD32 sleep_duration; // sleep duration computed at wakeup | |
3336 UWORD32 wakeup_time; // frame number of last wakeup | |
3337 UWORD16 wake_up_int_id; // Interrupt waking up the target | |
3338 UWORD8 wakeup_type; // Type of the interrupt | |
3339 UWORD8 why_big_sleep; // Type of the big sleep | |
3340 | |
3341 // flag for sleep .... | |
3342 UWORD8 sleep_performed; // NONE,SMALL,BIG,DEEP,ALL | |
3343 | |
3344 // status of clocks modules .... | |
3345 UWORD32 modules_status; // modules clocks status | |
3346 | |
3347 // constantes for 32Khz filtering | |
3348 UWORD32 c_clk_min; // INIT state | |
3349 UWORD32 c_clk_init_min; // INIT state | |
3350 UWORD32 c_clk_max; // INIT state | |
3351 UWORD32 c_clk_init_max; // INIT state | |
3352 UWORD32 c_delta_hf_acquis; // ACQUIS state | |
3353 UWORD32 c_delta_hf_update; // UPDATE state | |
3354 | |
3355 // trace gauging parameters | |
3356 UWORD8 state; // state of the gauging | |
3357 UWORD32 lf; // Number of the 32KHz | |
3358 UWORD32 hf; // HF: nb_hf( Number of the 13MHz *6 ) | |
3359 UWORD32 root; // root & frac: the ratio of the HF & LF in each state. | |
3360 UWORD32 frac; | |
3361 } | |
3362 T_POWER_MNGT; | |
3363 | |
3364 /*************************************************************/ | |
3365 /* code version structure... */ | |
3366 /*************************************************************/ | |
3367 typedef struct | |
3368 { | |
3369 // DSP versions & checksum | |
3370 UWORD16 dsp_code_version; | |
3371 UWORD16 dsp_patch_version; | |
3372 UWORD16 dsp_checksum; // DSP checksum : patch+code | |
3373 | |
3374 // MCU versions | |
3375 UWORD16 mcu_tcs_program_release; | |
3376 UWORD16 mcu_tcs_official; | |
3377 UWORD16 mcu_tcs_internal; | |
3378 UWORD16 mcu_tm_version; | |
3379 } | |
3380 T_VERSION; | |
3381 | |
3382 #if L1_RECOVERY | |
3383 typedef struct | |
3384 { | |
3385 UWORD32 frame_count; | |
3386 } | |
3387 T_L1S_RECOVER; | |
3388 #endif | |
3389 | |
3390 #if (TOA_ALGO == 2) | |
3391 typedef struct | |
3392 { | |
3393 WORD16 toa_shift; // TOA, value used to update the TOA | |
3394 UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results. | |
3395 BOOL toa_update_flag; // FLAG used to indicate when to the TOA module when to update TOA. | |
3396 // NOTE: Flag set to TRUE in l1s_synch() and reset to FALSE in l1ctl_toa() | |
3397 UWORD16 toa_frames_counter; // TOA Frames counter - Number of the TDMA frames (or bursts) which are used for TOA | |
3398 // updation OR number of times l1ctl_toa() function is invoked | |
3399 // Reset every TOA_PERIOD_LEN[l1_mode] frames | |
3400 UWORD16 toa_accumul_counter; // Number of TDMA frames (or bursts) which are actually used for TOA tracking | |
3401 // <= toa_frames_counter, as only if SNR>0.46875 TOA estimated by DSP is used to | |
3402 // update the tracking algorithm | |
3403 WORD16 toa_accumul_value; // TOA_tracking_value accumulated over 'toa_accumul_counter' frames | |
3404 // Based on this value the shift to be applied is decided | |
3405 UWORD32 toa_update_fn; // a counter which is in direct relation to l1s.actual_time.fn | |
3406 // and used for TOA tracking in ALL MODES every 433 MF's (approx. 2 seconds) | |
3407 | |
3408 }T_TOA_ALGO; | |
3409 #endif | |
3410 | |
3411 | |
3412 /***************************************************************************************/ | |
3413 /* L1S global variable structure... */ | |
3414 /***************************************************************************************/ | |
3415 typedef struct | |
3416 { | |
3417 //++++++++++++++++++++ | |
3418 // Power Management... | |
3419 //++++++++++++++++++++ | |
3420 | |
3421 T_POWER_MNGT pw_mgr; // data base for power management | |
3422 | |
3423 // Time for debug & Simulation purpose... | |
3424 // -> used as base time for BTS simulation. | |
3425 //----------------------------------------- | |
3426 UWORD32 debug_time; // time counter used by L3 scenario... | |
3427 | |
3428 // L1S Tasks management... | |
3429 //----------------------------------------- | |
3430 T_TASK_STATUS task_status[NBR_DL_L1S_TASKS]; // ...in L1S, scheduler. | |
3431 UWORD8 frame_count; // ...nb frames to go. | |
3432 UWORD8 forbid_meas; // ...frames where meas. ctrl is not allowed. | |
3433 | |
3434 // MFTAB management variables... | |
3435 //----------------------------------------- | |
3436 UWORD8 afrm; // active frame ID. | |
3437 T_MFTAB FAR mftab; // Multiframe table. | |
3438 | |
3439 // Control parameters... | |
3440 //----------------------------------------- | |
3441 UWORD32 afc_frame_count; // AFC, Frame count between 2 calls to afc control function. | |
3442 WORD16 afc; // AFC, Common Frequency controle. | |
3443 #if (TOA_ALGO == 2) | |
3444 T_TOA_ALGO toa_var; | |
3445 #else | |
3446 WORD16 toa_shift; // TOA, value used to update the TOA | |
3447 UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results. | |
3448 | |
3449 UWORD16 toa_period_count; // TOA frame period used in PACKET TRANSFER MODE | |
3450 BOOL toa_update; // TOA, is set at the end of the update period, toa update occurs on next valid frame | |
3451 #endif | |
3452 | |
3453 // Flag registers for RF task controle... | |
3454 //----------------------------------------- | |
3455 // Made these control registers short's as more than 8-bits required. | |
3456 UWORD16 tpu_ctrl_reg; // (x,x,x,x,SYNC,RX,TX,MS) RX/TX/MS/SYNC bit ON whenever an | |
3457 // according "controle" has been setup in the current frame. | |
3458 UWORD16 dsp_ctrl_reg; // (x,x,x,x,x,RX,TX,MS) RX/TX/MS bit ON whenever an | |
3459 // according "controle" has been setup in the current frame. | |
3460 | |
3461 //+++++++++++++++++++ | |
3462 // Serving... | |
3463 //+++++++++++++++++++ | |
3464 | |
3465 // Serving frame number management. | |
3466 //--------------------------------- | |
3467 T_TIME_INFO actual_time; // Time info: current FN, T1, T2, T3... | |
3468 T_TIME_INFO next_time; // Time info: next FN, T1, T2, T3... | |
3469 T_TIME_INFO next_plus_time; // Time info: next FN, T1, T2, T3... | |
3470 | |
3471 // TXPWR management. | |
3472 //------------------- | |
3473 UWORD8 reported_txpwr; // Reported value for TXPWR. | |
3474 UWORD8 applied_txpwr; // Current value for TXPWR. | |
3475 | |
3476 // Last RXQUAL value. | |
3477 //------------------- | |
3478 UWORD8 rxqual; // last rxqual value. | |
3479 | |
3480 // Hardware info. | |
3481 //--------------- | |
3482 UWORD32 tpu_offset; // Current TPU offset register value safeguard. | |
3483 UWORD32 tpu_offset_hw; // Current TPU offset register value copied in the TPU. | |
3484 UWORD16 tpu_win; // tpu window identifier inside a TDMA. | |
3485 | |
3486 // code versions | |
3487 T_VERSION version; | |
3488 | |
3489 #if (L1_GTT == 1) | |
3490 UWORD8 tty_state; // state for L1S GTT manager. | |
3491 #if L2_L3_SIMUL | |
3492 // GTT test | |
3493 T_GTT_TEST_L1S gtt_test; | |
3494 #endif | |
3495 #endif | |
3496 #if (L1_DYN_DSP_DWNLD == 1) | |
3497 UWORD8 dyn_dwnld_state; // state for L1S DYN DWNLD manager | |
3498 #endif // L1_DYN_DSP_DWNLD | |
3499 #if (AUDIO_TASK == 1) | |
3500 // Audio task. | |
3501 //----------------------------------------- | |
3502 BOOL l1_audio_it_com; // Flag to enable the ITCOM. | |
3503 UWORD8 audio_state[NBR_AUDIO_MANAGER]; // state for L1S audio manager. | |
3504 #if (MELODY_E1) | |
3505 T_L1S_MELODY_TASK melody0; | |
3506 T_L1S_MELODY_TASK melody1; | |
3507 #endif | |
3508 #if (VOICE_MEMO) | |
3509 T_L1S_VM_TASK voicememo; | |
3510 #endif | |
3511 #if (L1_PCM_EXTRACTION) | |
3512 T_L1S_PCM_TASK pcm; | |
3513 #endif | |
3514 #if (L1_VOICE_MEMO_AMR) | |
3515 T_L1S_VM_AMR_TASK voicememo_amr; | |
3516 #endif | |
3517 #if (SPEECH_RECO) | |
3518 T_L1S_SR_TASK speechreco; | |
3519 #endif | |
3520 #if (L1_AEC == 1) | |
3521 T_L1S_AEC_TASK aec; | |
3522 #endif | |
3523 #if (MELODY_E2) | |
3524 T_L1S_MELODY_E2_COMMON_VAR melody_e2; | |
3525 T_L1S_MELODY_E2_TASK melody0_e2; | |
3526 T_L1S_MELODY_E2_TASK melody1_e2; | |
3527 #endif | |
3528 #if (L1_EXT_AUDIO_MGT == 1) | |
3529 T_L1S_EXT_AUDIO_MGT_VAR ext_audio_mgt; | |
3530 #endif | |
3531 #if (L1_WCM == 1) | |
3532 T_WCM_ACTION wcm_action; | |
3533 #endif | |
3534 #if (L1_AGC_UL == 1) | |
3535 T_AGC_ACTION agc_ul_action; | |
3536 #endif | |
3537 #if (L1_AGC_DL == 1) | |
3538 T_AGC_ACTION agc_dl_action; | |
3539 #endif | |
3540 #if (L1_ANR == 2) | |
3541 T_ANR_ACTION anr_ul_action; | |
3542 #endif | |
3543 #if (L1_IIR == 2) | |
3544 T_IIR_ACTION iir_dl_action; | |
3545 #endif | |
3546 #if (L1_DRC == 1) | |
3547 T_DRC_ACTION drc_dl_action; | |
3548 #endif | |
3549 | |
3550 #endif | |
3551 | |
3552 UWORD8 last_used_txpwr; | |
3553 | |
3554 #if L1_GPRS | |
3555 BOOL ctrl_synch_before; //control of synchro for CCCH reading en TN-2 | |
3556 UWORD32 next_gauging_scheduled_for_PNP; // gauging for Packet Idle | |
3557 #endif | |
3558 | |
3559 #if L1_RECOVERY | |
3560 T_L1S_RECOVER recovery; | |
3561 #endif | |
3562 BOOL spurious_fb_detected; | |
3563 | |
3564 // Handling DTX mode | |
3565 BOOL dtx_ul_on; //earlier name was- dtx_on | |
3566 WORD8 facch_bursts; | |
3567 // DTX mode in AMR | |
3568 BOOL dtx_amr_dl_on; // set to TRUE when the AMR is in DTX mode in downlink | |
3569 | |
3570 //+++++++++++++++++ | |
3571 // GSM IDLE IN RAM | |
3572 //+++++++++++++++++ | |
3573 | |
3574 #if (GSM_IDLE_RAM != 0) | |
3575 T_L1S_GSM_IDLE_INTRAM gsm_idle_ram_ctl; | |
3576 | |
3577 #if (GSM_IDLE_RAM == 1) | |
3578 // Used to avoid allocation of ext mem data while in L1S_meas_manager (allocate signal long time before sending) | |
3579 T_RXLEV_MEAS A[8]; | |
3580 #endif | |
3581 #endif | |
3582 | |
3583 //+++++++++++++++++ | |
3584 // Triton Audio ON/OFF Changes | |
3585 //+++++++++++++++++ | |
3586 #if (L1_AUDIO_MCU_ONOFF == 1) | |
3587 T_L1S_AUDIO_ONOFF_MANAGER audio_on_off_ctl; | |
3588 #endif | |
3589 | |
3590 #if (ANALOG == 11) | |
3591 UWORD8 abb_write_done; | |
3592 #endif | |
3593 UWORD8 tcr_prog_done; | |
3594 | |
3595 #if (L1_RF_KBD_FIX == 1) | |
3596 UWORD16 total_kbd_on_time; | |
3597 UWORD8 correction_ratio; //KPD_CORRECTION_RATIO correction_ratio;//omaps00090550 | |
3598 #endif | |
3599 #if (L1_GPRS == 1) | |
3600 BOOL algo_change_synchro_active; | |
3601 #endif /* FF_L1_FAST_DECODING */ | |
3602 #if (FF_REPEATED_SACCH == 1) | |
3603 // Repeated SACCH mode | |
3604 T_REPEAT_SACCH repeated_sacch; | |
3605 #endif /* FF_REPEATED_SACCH */ | |
3606 #if (FF_REPEATED_DL_FACCH == 1) | |
3607 // Repeated FACCH mode | |
3608 T_REPEAT_FACCH repeated_facch; | |
3609 #endif /* FF_REPEATED_DL_FACCH == 1 */ | |
3610 /* 0 indicates success, non zero value indicates failure */ | |
3611 UWORD8 boot_result; | |
3612 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging | |
3613 UWORD8 force_gauging_next_paging_due_to_CCHR; | |
3614 | |
3615 } | |
3616 T_L1S_GLOBAL; | |
3617 | |
3618 #if (AUDIO_TASK == 1) | |
3619 #if (L1_VOCODER_IF_CHANGE == 1) | |
3620 typedef struct | |
3621 { | |
3622 BOOL enabled; // TRUE if enabled, FALSE if disabled | |
3623 BOOL automatic_disable; // TRUE if vocoders are automatically disabld via a MPHC_STOP_DEDICATED_REQ, FALSE otherwise. | |
3624 } T_L1A_VOCODER_CFG_GLOBAL; | |
3625 #endif // L1_VOCODER_IF_CHANGE == 1 | |
3626 typedef struct | |
3627 { | |
3628 UWORD8 outen1; | |
3629 UWORD8 outen2; | |
3630 UWORD8 outen3; | |
3631 UWORD8 classD; | |
3632 UWORD8 command_requested; /* updated in L1a task context*/ | |
3633 UWORD8 command_commited; /* updated in I2c ISR callback context*/ | |
3634 } T_OUTEN_CFG_TASK; | |
3635 | |
3636 #endif // AUDIO_TASK == 1 | |
3637 /***************************************************************************************/ | |
3638 /* L1A global variable structure... */ | |
3639 /***************************************************************************************/ | |
3640 typedef struct | |
3641 { | |
3642 // State for L1A state machines... | |
3643 //----------------------------------------- | |
3644 UWORD8 state[NBR_L1A_PROCESSES]; | |
3645 | |
3646 // Measurement tasks management... | |
3647 //----------------------------------------- | |
3648 UWORD32 l1a_en_meas[NBR_L1A_PROCESSES]; | |
3649 | |
3650 // Flag for forward/delete message management. | |
3651 //--------------------------------------------- | |
3652 UWORD8 l1_msg_forwarded; | |
3653 | |
3654 #if (L1_DYN_DSP_DWNLD == 1) | |
3655 // Dynamic donload global variables | |
3656 T_L1A_DYN_DWNLD_GLOBAL dyn_dwnld; | |
3657 #endif | |
3658 | |
3659 // New Vocoder IF global L1A variable: L1A checks if the vocoder has already been enabled/disabled | |
3660 // in order to robust to possible multiples enabling/disabling messages coming from PS | |
3661 | |
3662 #if (L1_VOCODER_IF_CHANGE == 1) | |
3663 T_L1A_VOCODER_CFG_GLOBAL vocoder_state; | |
3664 #endif // L1_VOCODER_IF_CHANGE == 1 | |
3665 | |
3666 // signal code indicating the reason of L1C_DEDIC_DONE | |
3667 UWORD32 confirm_SignalCode; | |
3668 | |
3669 #if (L1_MP3 == 1) | |
3670 T_L1_MP3_L1A mp3_task; | |
3671 //ADDED FOR AAC | |
3672 #endif | |
3673 | |
3674 #if (L1_AAC == 1) | |
3675 T_L1_AAC_L1A aac_task; | |
3676 #endif | |
3677 #if(L1_IIR == 2) | |
3678 xSignalHeaderRec *iir_req_msg_ptr; | |
3679 #endif | |
3680 | |
3681 #if(L1_DRC == 1) | |
3682 xSignalHeaderRec *drc_req_msg_ptr; | |
3683 #endif | |
3684 | |
3685 #if(L1_WCM == 1) | |
3686 xSignalHeaderRec *wcm_req_msg_ptr; | |
3687 #endif | |
3688 | |
3689 #if(L1_CHECK_COMPATIBLE == 1) | |
3690 BOOL vcr_wait; | |
3691 BOOL stop_req; | |
3692 BOOL vcr_msg_param; | |
3693 BOOL vch_auto_disable; | |
3694 #endif | |
3695 | |
3696 } | |
3697 T_L1A_GLOBAL; | |
3698 | |
3699 /***************************************************************************************/ | |
3700 /* L1A -> L1S communication structure... */ | |
3701 /***************************************************************************************/ | |
3702 typedef struct | |
3703 { | |
3704 //+++++++++++++++++++ | |
3705 // Serving Cell... | |
3706 //+++++++++++++++++++ | |
3707 | |
3708 // Serving Cell identity and information. | |
3709 //--------------------------------------- | |
3710 T_CELL_INFO Scell_info; | |
3711 T_SMEAS Smeas_dedic; | |
3712 | |
3713 UWORD8 Scell_IL_for_rxlev; | |
3714 T_INPUT_LEVEL Scell_used_IL; | |
3715 T_INPUT_LEVEL Scell_used_IL_d; | |
3716 T_INPUT_LEVEL Scell_used_IL_dd; | |
3717 | |
3718 T_BCCHS nbcchs; | |
3719 T_BCCHS ebcchs; | |
3720 | |
3721 // Synchro information. | |
3722 //--------------------------------------- | |
3723 #if L1_FF_WA_OMAPS00099442 | |
3724 BOOL change_tpu_offset_flag; | |
3725 #endif | |
3726 | |
3727 WORD8 tn_difference; // Timeslot difference for next synchro. | |
3728 UWORD8 dl_tn; // Current timeslot for downlink stuffs. | |
3729 #if L1_GPRS | |
3730 UWORD8 dsp_scheduler_mode; // DSP Scheduler mode (GPRS or GSM). | |
3731 #endif | |
3732 | |
3733 // Idle parameters. | |
3734 //----------------- | |
3735 BOOL bcch_combined; // BS_CCCH_SDCCH_COMB flag. | |
3736 UWORD8 bs_pa_mfrms; // BS_PA_MFRMS parameter. | |
3737 UWORD8 bs_ag_blks_res; // BS_AG_BLKS_RES parameter. | |
3738 UWORD8 ccch_group; // CCCH_GROUP parameter. | |
3739 UWORD8 page_group; // PAGING_GROUP parameter. | |
3740 UWORD8 page_block_index; // Paging block index paramter. | |
3741 T_IDLE_TASK_INFO idle_task_info; // Idle task positions... | |
3742 UWORD8 nb_pch_per_mf51; // nbr paging blocks per mf51. | |
3743 | |
3744 // CBCH parameters. | |
3745 // ---------------- | |
3746 UWORD32 offset_tn0; // TPU offset for TN=0 (used for SMSCB only). | |
3747 T_CHANNEL_DESCRIPTION cbch_desc; // CBCH (SMSCB) channel description. | |
3748 T_MOBILE_ALLOCATION cbch_freq_list; // CBCH frequency list (hopping freq list). | |
3749 UWORD32 mf51_fn; // Starting FN (for CBCH reading. | |
3750 UWORD8 cbch_start_in_mf51; // Starting position of CBCH in the MF51. | |
3751 T_CBCH_HEAD_SCHEDULE norm_cbch_schedule; // Normal CBCH scheduling structure. | |
3752 T_CBCH_HEAD_SCHEDULE ext_cbch_schedule; // Extended CBCH scheduling structure. | |
3753 T_CBCH_INFO_SCHEDULE cbch_info_req; | |
3754 BOOL pre_scheduled_cbch; // CBCH task has to be scheduled 1 FN in advance | |
3755 BOOL change_synchro_cbch;// A Pseudo Synchro is needed to read CBCH block | |
3756 UWORD8 tn_smscb; // CBCH TN taking into account new Synchro | |
3757 | |
3758 // Random Access information. | |
3759 // ---------------------------- | |
3760 T_RA_TASK_INFO ra_info; | |
3761 | |
3762 // ADC management. | |
3763 //------------------- | |
3764 UWORD16 adc_mode; | |
3765 UWORD8 adc_idle_period; | |
3766 UWORD8 adc_traffic_period; | |
3767 UWORD8 adc_cpt; | |
3768 | |
3769 // TXPWR management. | |
3770 //------------------- | |
3771 #if (L1_FF_MULTIBAND == 0) | |
3772 UWORD8 powerclass_band1; // Power class for the MS, given in ACCESS LINK mode (GSM Band). | |
3773 UWORD8 powerclass_band2; // Power class for the MS, given in ACCESS LINK mode (DCS Band). | |
3774 #else | |
3775 UWORD8 powerclass[RF_NB_SUPPORTED_BANDS]; | |
3776 #endif | |
3777 | |
3778 | |
3779 // Dedicated parameters. | |
3780 //---------------------- | |
3781 T_DEDIC_PARAM dedic_set; // Dedicated channel parameters. | |
3782 | |
3783 //+++++++++++++++++++ | |
3784 // Neighbour Cells... | |
3785 //+++++++++++++++++++ | |
3786 | |
3787 T_BCCHN_LIST bcchn; | |
3788 T_NSYNC_LIST nsync; | |
3789 | |
3790 // BA list / FULL list. | |
3791 //--------------------- | |
3792 T_BA_LIST ba_list; | |
3793 T_FULL_LIST full_list; | |
3794 T_FULL_LIST_MEAS *full_list_ptr; | |
3795 | |
3796 #if ((REL99 == 1) && (FF_BHO == 1)) | |
3797 // For blind handover... | |
3798 T_BHO_PARAM nsync_fbsb; | |
3799 #endif | |
3800 | |
3801 //+++++++++++++++++++ | |
3802 // L1S scheduler... | |
3803 //+++++++++++++++++++ | |
3804 | |
3805 // L1S tasks management... | |
3806 //----------------------------------------- | |
3807 BOOL task_param[NBR_DL_L1S_TASKS]; // ...synchro semaphores. | |
3808 BOOL l1s_en_task[NBR_DL_L1S_TASKS]; // ...enable register. | |
3809 UWORD32 time_to_next_l1s_task; // time to wait to reach starting frame of next task. | |
3810 UWORD8 l1a_activity_flag; // Activity flag. | |
3811 | |
3812 // Measurement tasks management... | |
3813 //----------------------------------------- | |
3814 UWORD32 meas_param; // Synchro semaphore bit register. | |
3815 UWORD32 l1s_en_meas; // Enable task bit register. | |
3816 | |
3817 // L1 mode... | |
3818 //----------------------------------------- | |
3819 UWORD32 mode; // functional mode: CS_MODE, I_MODE... | |
3820 | |
3821 //++++++++++++++++++++++++ | |
3822 // Controle parameters... | |
3823 //++++++++++++++++++++++++ | |
3824 UWORD32 fb_mode; // Mode for fb detection algorithm. | |
3825 UWORD8 toa_reset; // Flag for TOA algo. reset. | |
3826 | |
3827 // Input level memory for AGC management. | |
3828 //--------------------------------------- | |
3829 T_INPUT_LEVEL last_input_level[NBMAX_CARRIER+1]; | |
3830 | |
3831 BOOL recovery_flag; // in case of the system is down and needs to be recovered | |
3832 | |
3833 //++++++++++++++++++++++++ | |
3834 // Audio task... | |
3835 //++++++++++++++++++++++++ | |
3836 #if (AUDIO_TASK == 1) | |
3837 #if (KEYBEEP) | |
3838 T_KEYBEEP_TASK keybeep_task; | |
3839 #endif | |
3840 #if (TONE) | |
3841 T_TONE_TASK tone_task; | |
3842 #endif | |
3843 #if (MELODY_E1) | |
3844 T_MELODY_TASK melody0_task; | |
3845 T_MELODY_TASK melody1_task; | |
3846 #endif | |
3847 #if (VOICE_MEMO) | |
3848 T_VM_TASK voicememo_task; | |
3849 #endif | |
3850 #if (L1_PCM_EXTRACTION) | |
3851 T_PCM_TASK pcm_task; | |
3852 #endif | |
3853 #if (L1_VOICE_MEMO_AMR) | |
3854 T_VM_AMR_TASK voicememo_amr_task; | |
3855 #endif | |
3856 #if (SPEECH_RECO) | |
3857 T_SR_TASK speechreco_task; | |
3858 #endif | |
3859 #if (L1_AEC == 1) | |
3860 T_AEC_TASK aec_task; | |
3861 #endif | |
3862 #if (L1_AEC == 2) | |
3863 T_AEC_TASK aec_task; | |
3864 #endif | |
3865 #if (FIR) | |
3866 T_FIR_TASK fir_task; | |
3867 #endif | |
3868 #if (AUDIO_MODE) | |
3869 T_AUDIO_MODE_TASK audio_mode_task; | |
3870 #endif | |
3871 #if (MELODY_E2) | |
3872 T_MELODY_E2_TASK melody0_e2_task; | |
3873 T_MELODY_E2_TASK melody1_e2_task; | |
3874 #endif | |
3875 #if (L1_CPORT == 1) | |
3876 T_CPORT_TASK cport_task; | |
3877 #endif | |
3878 | |
3879 #if (L1_EXTERNAL_AUDIO_VOICE_ONOFF == 1 || L1_EXT_MCU_AUDIO_VOICE_ONOFF == 1) | |
3880 T_AUDIO_ONOFF_TASK audio_onoff_task; | |
3881 #endif | |
3882 | |
3883 BOOL audio_forced_by_l1s; /* This value is used to indicate if the L1S is forcing the audio_on_off feature in the DSP CQ21718 */ | |
3884 | |
3885 #if (L1_STEREOPATH == 1) | |
3886 T_STEREOPATH_DRV_TASK stereopath_drv_task; | |
3887 #endif | |
3888 | |
3889 #if (L1_MP3 == 1) | |
3890 T_MP3_TASK mp3_task; | |
3891 #endif | |
3892 | |
3893 #if (L1_MIDI == 1) | |
3894 T_MIDI_TASK midi_task; | |
3895 #endif | |
3896 //ADDED FOR AAC | |
3897 #if (L1_AAC == 1) | |
3898 T_AAC_TASK aac_task; | |
3899 #endif | |
3900 | |
3901 #if (L1_ANR == 1) | |
3902 T_ANR_TASK anr_task; | |
3903 #endif | |
3904 | |
3905 #if (L1_ANR == 2) | |
3906 T_AQI_ANR_TASK anr_task; | |
3907 #endif | |
3908 | |
3909 #if (L1_IIR == 1) | |
3910 T_IIR_TASK iir_task; | |
3911 #endif | |
3912 | |
3913 #if (L1_AGC_UL == 1) | |
3914 T_AQI_AGC_UL_TASK agc_ul_task; | |
3915 #endif | |
3916 | |
3917 #if (L1_AGC_DL == 1) | |
3918 T_AQI_AGC_DL_TASK agc_dl_task; | |
3919 #endif | |
3920 | |
3921 #if (L1_IIR == 2) | |
3922 T_AQI_IIR_TASK iir_task; | |
3923 #endif | |
3924 | |
3925 #if (L1_DRC == 1) | |
3926 T_AQI_DRC_TASK drc_task; | |
3927 #endif | |
3928 | |
3929 #if (L1_LIMITER == 1) | |
3930 T_LIMITER_TASK limiter_task; | |
3931 #endif | |
3932 | |
3933 #if (L1_ES == 1) | |
3934 T_ES_TASK es_task; | |
3935 #endif | |
3936 | |
3937 #if (L1_WCM == 1) | |
3938 T_AQI_WCM_TASK wcm_task; | |
3939 #endif | |
3940 | |
3941 //++++++++++++++++++++++++++++++++++++ | |
3942 // Fake L1S sm for audio IT generation | |
3943 //++++++++++++++++++++++++++++++++++++ | |
3944 T_AUDIOIT_TASK audioIt_task; | |
3945 | |
3946 /* | |
3947 * FreeCalypso change: I had to move this part here, or else | |
3948 * compilation fails w/o AUDIO_TASK | |
3949 */ | |
3950 T_OUTEN_CFG_TASK outen_cfg_task; | |
3951 #endif | |
3952 | |
3953 | |
3954 //+++++++++++++ | |
3955 // GTT task | |
3956 //+++++++++++++ | |
3957 | |
3958 #if (L1_GTT == 1) | |
3959 T_GTT_TASK gtt_task; | |
3960 #endif | |
3961 | |
3962 // Dynamic DSP download task | |
3963 #if (L1_DYN_DSP_DWNLD == 1) | |
3964 T_DYN_DWNLD_TASK_COMMAND dyn_dwnld_task; | |
3965 #endif | |
3966 | |
3967 #if REL99 | |
3968 #if FF_EMR | |
3969 T_SMEAS_EMR Smeas_dedic_emr; | |
3970 #endif | |
3971 #endif | |
3972 | |
3973 #if (FF_L1_FAST_DECODING == 1) | |
3974 UWORD8 last_fast_decoding; | |
3975 #endif /* if (FF_L1_FAST_DECODING == 1) */ | |
3976 | |
3977 } | |
3978 T_L1A_L1S_COM; | |
3979 | |
3980 /***************************************************************************************/ | |
3981 /* L1A -> DSP communication structure... */ | |
3982 /***************************************************************************************/ | |
3983 typedef struct | |
3984 { | |
3985 UWORD8 dsp_w_page; // Active page for ARM "writting" to DSP {0,1}. | |
3986 UWORD8 dsp_r_page; // Active page for ARM "reading" from DSP {0,1}. | |
3987 UWORD8 dsp_r_page_used; // Used in "l1_synch" to know if the read page must be chged. | |
3988 | |
3989 T_DB_DSP_TO_MCU *dsp_db_r_ptr; // MCU<->DSP comm. read page (Double Buffered comm. memory). | |
3990 T_DB_MCU_TO_DSP *dsp_db_w_ptr; // MCU<->DSP comm. write page (Double Buffered comm. memory). | |
3991 #if (DSP ==38) || (DSP == 39) | |
3992 T_DB_COMMON_MCU_TO_DSP *dsp_db_common_w_ptr; // MCU<->DSP comm. common write page (Double Buffered comm. memory). | |
3993 #endif | |
3994 T_NDB_MCU_DSP *dsp_ndb_ptr; // MCU<->DSP comm. read/write (Non Double Buffered comm. memory). | |
3995 | |
3996 T_PARAM_MCU_DSP *dsp_param_ptr; // MCU<->DSP comm. read/write (Param comm. memory). | |
3997 | |
3998 #if (DSP_DEBUG_TRACE_ENABLE == 1) | |
3999 T_DB2_DSP_TO_MCU *dsp_db2_current_r_ptr; | |
4000 T_DB2_DSP_TO_MCU *dsp_db2_other_r_ptr; | |
4001 #endif | |
4002 | |
4003 /* DSP CPU load measurement */ | |
4004 /* FreeCalypso change: the necessary #if was missing */ | |
4005 #if (DSP == 38) || (DSP == 39) | |
4006 T_DB_MCU_TO_DSP_CPU_LOAD *dsp_cpu_load_db_w_ptr; | |
4007 #endif | |
4008 } | |
4009 T_L1S_DSP_COM; | |
4010 | |
4011 /***************************************************************************************/ | |
4012 /* L1A -> TPU communication structure... */ | |
4013 /***************************************************************************************/ | |
4014 typedef struct | |
4015 { | |
4016 UWORD8 tpu_w_page; // Active page for ARM "writting" to TPU {0,1}. | |
4017 UWORD32 *tpu_page_ptr; // Current Pointer within the active "tpu_page". | |
4018 #if (CODE_VERSION == SIMULATION) | |
4019 T_reg_cmd *reg_cmd; // command register for TPU & DSP enabling and pages pgmation | |
4020 #else | |
4021 UWORD16 *reg_cmd; // command register for TPU & DSP enabling and pages pgmation | |
4022 #endif | |
4023 UWORD32 *reg_com_int; // communication int. register | |
4024 UWORD32 *offset; // offset register | |
4025 } | |
4026 T_L1S_TPU_COM; | |
4027 | |
4028 /***************************************************************************************/ | |
4029 /* L1 configuration structure */ | |
4030 /***************************************************************************************/ | |
4031 #if (L1_FF_MULTIBAND == 0) | |
4032 | |
4033 typedef struct | |
4034 { | |
4035 UWORD8 id; //standard identifier | |
4036 | |
4037 | |
4038 | |
4039 UWORD16 radio_band_support; | |
4040 | |
4041 | |
4042 UWORD8 swap_iq_band1; | |
4043 UWORD8 swap_iq_band2; | |
4044 | |
4045 UWORD32 first_radio_freq; | |
4046 UWORD32 first_radio_freq_band2; | |
4047 UWORD32 radio_freq_index_offset; | |
4048 UWORD32 nbmax_carrier; | |
4049 UWORD32 nbmeas; | |
4050 UWORD32 max_txpwr_band1; | |
4051 UWORD32 max_txpwr_band2; | |
4052 UWORD32 txpwr_turning_point; | |
4053 | |
4054 UWORD16 cal_freq1_band1; | |
4055 UWORD16 cal_freq1_band2; | |
4056 UWORD16 g_magic_band1; | |
4057 UWORD16 g_magic_band2; | |
4058 UWORD16 lna_att_band1; | |
4059 UWORD16 lna_att_band2; | |
4060 UWORD16 lna_switch_thr_low_band1; | |
4061 UWORD16 lna_switch_thr_low_band2; | |
4062 UWORD16 lna_switch_thr_high_band1; | |
4063 UWORD16 lna_switch_thr_high_band2; | |
4064 } | |
4065 T_L1_STD_CNFG; | |
4066 | |
4067 #endif // #if (L1_FF_MULTIBAND == 0) | |
4068 | |
4069 #if (L1_FF_MULTIBAND == 1) | |
4070 | |
4071 #if 0 | |
4072 typedef struct | |
4073 { | |
4074 UWORD16 nbmax_carrier; | |
4075 UWORD16 first_radio_freq; | |
4076 UWORD16 first_tpu_radio_freq; | |
4077 UWORD16 first_operative_radio_freq; | |
4078 UWORD8 physical_band_id; | |
4079 } | |
4080 T_MULTIBAND_CONVERSION_DATA; | |
4081 | |
4082 typedef struct | |
4083 { | |
4084 UWORD16 lna_switch_thr_high; | |
4085 UWORD16 lna_switch_thr_low; | |
4086 UWORD16 lna_att; | |
4087 UWORD16 g_magic; | |
4088 UWORD8 swap_iq; | |
4089 UWORD16 cal_freq1; | |
4090 UWORD8 tx_turning_point; | |
4091 UWORD8 max_txpwr; | |
4092 UWORD8 gsm_band_identifier; | |
4093 } | |
4094 T_MULTIBAND_RF_DATA; | |
4095 #endif // if 0 | |
4096 typedef struct | |
4097 { | |
4098 UWORD8 radio_band; | |
4099 UWORD8 power_class; | |
4100 UWORD8 _align0; | |
4101 UWORD8 _align1; | |
4102 } | |
4103 T_L1_MULTIBAND_POWER_CLASS; | |
4104 | |
4105 | |
4106 #endif /*if (L1_FF_MULTIBAND == 1)*/ | |
4107 | |
4108 | |
4109 //RF dependent parameter definitions | |
4110 typedef struct | |
4111 { | |
4112 UWORD16 rx_synth_setup_time; | |
4113 UWORD8 rx_synth_load_split; | |
4114 WORD16 rx_synth_start_time; | |
4115 WORD16 rx_change_offset_time; | |
4116 WORD16 rx_change_synchro_time; | |
4117 UWORD8 rx_tpu_scenario_ending; | |
4118 | |
4119 UWORD16 tx_synth_setup_time; | |
4120 UWORD8 tx_synth_load_split; | |
4121 WORD16 tx_synth_start_time; | |
4122 WORD16 tx_change_offset_time; | |
4123 WORD16 tx_nb_duration; | |
4124 WORD16 tx_ra_duration; | |
4125 UWORD8 tx_nb_load_split; | |
4126 UWORD8 tx_ra_load_split; | |
4127 UWORD8 tx_tpu_scenario_ending; | |
4128 | |
4129 WORD16 fb26_anchoring_time; | |
4130 WORD16 fb26_change_offset_time; | |
4131 | |
4132 UWORD32 prg_tx_gsm; | |
4133 UWORD32 prg_tx_dcs; | |
4134 | |
4135 UWORD16 low_agc_noise_thr; | |
4136 UWORD16 high_agc_sat_thr; | |
4137 | |
4138 UWORD16 low_agc; | |
4139 UWORD16 high_agc; | |
4140 | |
4141 UWORD16 il_min; | |
4142 | |
4143 UWORD16 fixed_txpwr; | |
4144 WORD16 eeprom_afc; | |
4145 WORD8 setup_afc_and_rf; | |
4146 WORD8 rf_wakeup_tpu_scenario_duration; // Duration (in TDMA frames) of TPU scenario for RF wakeup | |
4147 | |
4148 UWORD32 psi_sta_inv; | |
4149 UWORD32 psi_st; | |
4150 UWORD32 psi_st_32; | |
4151 UWORD32 psi_st_inv; | |
4152 | |
4153 #if (VCXO_ALGO==1) | |
4154 WORD16 afc_dac_center; | |
4155 WORD16 afc_dac_min; | |
4156 WORD16 afc_dac_max; | |
4157 WORD16 afc_snr_thr; | |
4158 UWORD8 afc_algo; | |
4159 UWORD8 afc_win_avg_size_M; | |
4160 UWORD8 rgap_algo; | |
4161 UWORD8 rgap_bad_snr_count_B; | |
4162 #endif | |
4163 | |
4164 UWORD8 guard_bits; | |
4165 | |
4166 #if DCO_ALGO | |
4167 BOOL dco_enabled; | |
4168 #endif | |
4169 | |
4170 #if (ANALOG == 1) | |
4171 UWORD16 debug1; | |
4172 UWORD16 afcctladd; | |
4173 UWORD16 vbuctrl; | |
4174 UWORD16 vbdctrl; | |
4175 UWORD16 bbctrl; | |
4176 UWORD16 apcoff; | |
4177 UWORD16 bulioff; | |
4178 UWORD16 bulqoff; | |
4179 UWORD16 dai_onoff; | |
4180 UWORD16 auxdac; | |
4181 UWORD16 vbctrl; | |
4182 UWORD16 apcdel1; | |
4183 #endif | |
4184 #if (ANALOG == 2) | |
4185 UWORD16 debug1; | |
4186 UWORD16 afcctladd; | |
4187 UWORD16 vbuctrl; | |
4188 UWORD16 vbdctrl; | |
4189 UWORD16 bbctrl; | |
4190 UWORD16 bulgcal; | |
4191 UWORD16 apcoff; | |
4192 UWORD16 bulioff; | |
4193 UWORD16 bulqoff; | |
4194 UWORD16 dai_onoff; | |
4195 UWORD16 auxdac; | |
4196 UWORD16 vbctrl1; | |
4197 UWORD16 vbctrl2; | |
4198 UWORD16 apcdel1; | |
4199 UWORD16 apcdel2; | |
4200 #endif | |
4201 #if (ANALOG == 3) | |
4202 UWORD16 debug1; | |
4203 UWORD16 afcctladd; | |
4204 UWORD16 vbuctrl; | |
4205 UWORD16 vbdctrl; | |
4206 UWORD16 bbctrl; | |
4207 UWORD16 bulgcal; | |
4208 UWORD16 apcoff; | |
4209 UWORD16 bulioff; | |
4210 UWORD16 bulqoff; | |
4211 UWORD16 dai_onoff; | |
4212 UWORD16 auxdac; | |
4213 UWORD16 vbctrl1; | |
4214 UWORD16 vbctrl2; | |
4215 UWORD16 apcdel1; | |
4216 UWORD16 apcdel2; | |
4217 UWORD16 vbpop; | |
4218 UWORD16 vau_delay_init; | |
4219 UWORD16 vaud_cfg; | |
4220 UWORD16 vauo_onoff; | |
4221 UWORD16 vaus_vol; | |
4222 UWORD16 vaud_pll; | |
4223 #endif | |
4224 #if (ANALOG == 11) | |
4225 UWORD8 vulgain; | |
4226 UWORD8 vdlgain; | |
4227 UWORD8 sidetone; | |
4228 UWORD8 ctrl1; | |
4229 UWORD8 ctrl2; | |
4230 UWORD8 ctrl3; | |
4231 UWORD8 ctrl4; | |
4232 UWORD8 ctrl5; | |
4233 UWORD8 ctrl6; | |
4234 UWORD8 popauto; | |
4235 UWORD8 outen1; | |
4236 UWORD8 outen2; | |
4237 UWORD8 outen3; | |
4238 UWORD8 aulga; | |
4239 UWORD8 aurga; | |
4240 #endif | |
4241 #if (RF_FAM == 61) | |
4242 UWORD16 apcdel1; | |
4243 UWORD16 apcdel2; | |
4244 UWORD16 apcctrl2; | |
4245 #endif | |
4246 #if L1_GPRS | |
4247 UWORD16 toa_pm_thres; // PM threshold for TOA algorithm feeding in packet transfer mode | |
4248 #endif | |
4249 } | |
4250 T_L1_PARAMS; | |
4251 | |
4252 typedef struct | |
4253 { | |
4254 #if (L1_FF_MULTIBAND == 0) | |
4255 T_L1_STD_CNFG std; //standard: GSM,GSM_E,GSM850,DCS,PCS,DUAL,DUALEXT | |
4256 #endif // L1_FF_MULTIBAND == 0 | |
4257 | |
4258 UWORD8 pwr_mngt; //power management active | |
4259 UWORD8 tx_pwr_code; | |
4260 #if IDS | |
4261 UWORD8 ids_enable; | |
4262 #endif | |
4263 UWORD16 dwnld; | |
4264 T_L1_PARAMS params; | |
4265 double dpll; //dpll factor | |
4266 | |
4267 #if TESTMODE | |
4268 //Define the TestMode flag and TestMode parameters | |
4269 UWORD8 TestMode; | |
4270 | |
4271 UWORD8 agc_enable; | |
4272 UWORD8 afc_enable; | |
4273 UWORD8 adc_enable; | |
4274 #if (FF_REPEATED_SACCH == 1) | |
4275 UWORD8 repeat_sacch_enable; | |
4276 #endif /* FF_REPEATED_SACCH == 1 */ | |
4277 #if (FF_REPEATED_DL_FACCH == 1) | |
4278 UWORD8 repeat_facch_dl_enable; | |
4279 #endif /* (FF_REPEATED_DL_FACCH == 1)*/ | |
4280 | |
4281 T_TM_PARAMS tmode; //TestMode parameters structure | |
4282 #endif | |
4283 | |
4284 T_FACCH_TEST_PARAMS facch_test; | |
4285 } | |
4286 T_L1_CONFIG; | |
4287 // SAPI identifier : 0 (Signalling), 3 (Short Messages Services) | |
4288 #if FF_REPEATED_SACCH | |
4289 typedef enum | |
4290 { | |
4291 SAPI_0 = 0, | |
4292 SAPI_3 = 3 | |
4293 } T_L1_SAPI_ID; | |
4294 #endif /* FF_REPEATED_SACCH */ | |
4295 | |
4296 /***************************************************************************************/ | |
4297 /* API HISR -> L1A communication structure... */ | |
4298 /***************************************************************************************/ | |
4299 #if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) || (FF_L1_IT_DSP_USF == 1) ) // equivalent to an API_HISR flag | |
4300 | |
4301 #if FF_L1_IT_DSP_USF | |
4302 typedef struct | |
4303 { | |
4304 // Fast USF HISR pending | |
4305 BOOL pending; | |
4306 } T_L1A_USF_HISR_COM; | |
4307 #endif | |
4308 | |
4309 #if FF_L1_IT_DSP_DTX | |
4310 typedef struct | |
4311 { | |
4312 // Fast DTX HISR pending | |
4313 BOOL pending; | |
4314 // TX activity programmed in TCH block | |
4315 BOOL tx_active; | |
4316 // Fast DTX service is available | |
4317 BOOL fast_dtx_ready; | |
4318 // Fast DTX service latency timer | |
4319 UWORD8 fast_dtx_ready_timer; | |
4320 // Fast DTX state variable | |
4321 UWORD8 dtx_status; | |
4322 } T_L1A_DTX_HISR_COM; | |
4323 #endif | |
4324 | |
4325 #if (FF_L1_FAST_DECODING == 1) | |
4326 typedef struct | |
4327 { | |
4328 /* Fast Decoding HISR pending */ | |
4329 BOOL pending; | |
4330 /* Current CRC */ | |
4331 BOOL crc_error; | |
4332 /* Status (IT awaited?) */ | |
4333 UWORD8 status; | |
4334 /* Control required during incoming fast API IT? */ | |
4335 BOOL deferred_control_req; | |
4336 /* Task using fast decoding */ | |
4337 UWORD8 task; | |
4338 /* Burst ID of the task */ | |
4339 UWORD8 burst_id; | |
4340 /* Is the decoding of a contiguous block starting? */ | |
4341 BOOL contiguous_decoding; | |
4342 } T_L1A_FAST_DECODING_HISR_COM; | |
4343 #endif /* FF_L1_FAST_DECODING */ | |
4344 | |
4345 typedef struct | |
4346 { | |
4347 #if (L1_MP3 == 1) | |
4348 T_L1A_MP3_HISR_COM mp3; | |
4349 #endif | |
4350 #if (L1_MIDI == 1) | |
4351 T_L1A_MIDI_HISR_COM midi; | |
4352 //ADDED FOR AAC | |
4353 #endif | |
4354 #if (L1_AAC == 1) | |
4355 T_L1A_AAC_HISR_COM aac; | |
4356 #endif | |
4357 #if (L1_DYN_DSP_DWNLD == 1) | |
4358 T_L1A_DYN_DWNLD_HISR_COM dyn_dwnld; | |
4359 #endif // L1_DYN_DSP_DWNLD | |
4360 #if (FF_L1_IT_DSP_USF == 1) | |
4361 T_L1A_USF_HISR_COM usf; | |
4362 #endif | |
4363 #if (FF_L1_IT_DSP_DTX == 1) | |
4364 T_L1A_DTX_HISR_COM dtx; | |
4365 #endif | |
4366 #if (FF_L1_FAST_DECODING == 1) | |
4367 T_L1A_FAST_DECODING_HISR_COM fast_decoding; | |
4368 #endif /* FF_L1_FAST_DECODING */ | |
4369 } T_L1A_API_HISR_COM; | |
4370 | |
4371 #if (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) | |
4372 typedef struct | |
4373 { | |
4374 #if (L1_MP3 == 1) | |
4375 T_L1_MP3_API_HISR mp3; | |
4376 #endif | |
4377 #if (L1_MIDI == 1) | |
4378 T_L1_MIDI_API_HISR midi; | |
4379 #endif | |
4380 //ADDED FOR AAC | |
4381 #if (L1_AAC == 1) | |
4382 T_L1_AAC_API_HISR aac; | |
4383 #endif | |
4384 #if (L1_DYN_DSP_DWNLD == 1) | |
4385 T_L1_DYN_DWNLD_API_HISR dyn_dwnld; | |
4386 #endif // L1_DYN_DSP_DWNLD | |
4387 } T_L1_API_HISR; | |
4388 #endif // #if (L1_MP3 == 1) || (L1_MIDI == 1) || || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) | |
4389 | |
4390 #endif //(L1_MP3 == 1) || (L1_MIDI == 1) || (L1_DYN_DSP_DWNLD == 1) || (FF_L1_IT_DSP_USF == 1) | |
4391 | |
4392 typedef struct | |
4393 { | |
4394 /* 0 indicates success 1 indicates failure */ | |
4395 UWORD16 boot_result; | |
4396 UWORD16 drp_maj_ver; | |
4397 UWORD16 drp_min_ver; | |
4398 // MCU versions | |
4399 UWORD16 mcu_tcs_program_release; | |
4400 UWORD16 mcu_tcs_official; | |
4401 UWORD16 mcu_tcs_internal; | |
4402 // DSP versions & checksum | |
4403 UWORD16 dsp_code_version; | |
4404 UWORD16 dsp_patch_version; | |
4405 }T_L1_BOOT_VERSION_CODE; | |
4406 | |
4407 |