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comparison L1/include/l1_tabs.h @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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children f93dab57b032
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-1:000000000000 0:75a11d740a02
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_TABS.H
4 *
5 * Filename l1_tabs.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9 /***********************************************************
10 * Content:
11 * This file contains the miscelaneous ROM tables.
12 ***********************************************************/
13
14 #ifndef L1_TABS_H
15 #define L1_TABS_H
16
17 #ifdef L1_ASYNC_C
18 /*-----------------------------------------------------------------*/
19 /* Idle Tasks info. (Paging position, extended Paging position...) */
20 /*-----------------------------------------------------------------*/
21 /* REM: */
22 /* The "working area" field gives the starting position of an area */
23 /* it will be used for neighbour: - FB search, */
24 /* - SB reading, */
25 /* The value given for each parameter set takes into account the */
26 /* size of the "FB search" task and the CBCH task. */
27 /*-----------------------------------------------------------------*/
28 // NP or EP task size: 1 + 4 + 1 = 6.
29 // BCCHS task size: 1 + 4 + 1 = 6.
30 // FB task size: 1 + 12 + 1 = 14. --+-- FB + SB task take 15 TDMA (pipeline overlay).
31 // SB task size: 1 + 2 + 1 = 4. --+
32 // CNF, SB task size: 1 + 2 + 1 = 4.
33 // BC (Broad. Channel): 1 + 4 + 1 = 6
34
35 const T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)] =
36 // BS_CCCH_SDCCH_COMB = False, BCCH not combined.
37 {
38 // BS_AG_BLKS_RES = 0.
39 // -------------------
40 // Paging, Ext Paging
41 { CCCH_0, CCCH_2 }, // Paging Block Index = 0.
42 { CCCH_1, CCCH_3 }, // Paging Block Index = 1.
43 { CCCH_2, CCCH_4 }, // Paging Block Index = 2.
44 { CCCH_3, CCCH_5 }, // Paging Block Index = 3.
45 { CCCH_4, CCCH_6 }, // Paging Block Index = 4.
46 { CCCH_5, CCCH_7 }, // Paging Block Index = 5.
47 { CCCH_6, CCCH_8 }, // Paging Block Index = 6.
48 { CCCH_7, CCCH_0 }, // Paging Block Index = 7.
49 { CCCH_8, CCCH_1 }, // Paging Block Index = 8.
50
51 // BS_AG_BLKS_RES = 1.
52 // -------------------
53 // Paging, Ext Paging
54 { CCCH_1, CCCH_3 }, // Paging Block Index = 0.
55 { CCCH_2, CCCH_4 }, // Paging Block Index = 1.
56 { CCCH_3, CCCH_5 }, // Paging Block Index = 2.
57 { CCCH_4, CCCH_6 }, // Paging Block Index = 3.
58 { CCCH_5, CCCH_7 }, // Paging Block Index = 4.
59 { CCCH_6, CCCH_8 }, // Paging Block Index = 5.
60 { CCCH_7, CCCH_1 }, // Paging Block Index = 6.
61 { CCCH_8, CCCH_2 }, // Paging Block Index = 7.
62 { NULL, NULL }, // Paging Block Index = 8.
63
64 // BS_AG_BLKS_RES = 2.
65 // -------------------
66 // Paging, Ext Paging
67 { CCCH_2, CCCH_4 }, // Paging Block Index = 0.
68 { CCCH_3, CCCH_5 }, // Paging Block Index = 1.
69 { CCCH_4, CCCH_6 }, // Paging Block Index = 2.
70 { CCCH_5, CCCH_7 }, // Paging Block Index = 3.
71 { CCCH_6, CCCH_8 }, // Paging Block Index = 4.
72 { CCCH_7, CCCH_2 }, // Paging Block Index = 5.
73 { CCCH_8, CCCH_3 }, // Paging Block Index = 6.
74 { NULL, NULL }, // Paging Block Index = 7.
75 { NULL, NULL }, // Paging Block Index = 8.
76
77 // BS_AG_BLKS_RES = 3.
78 // -------------------
79 // Paging, Ext Paging,
80 { CCCH_3, CCCH_5 }, // Paging Block Index = 0.
81 { CCCH_4, CCCH_6 }, // Paging Block Index = 1.
82 { CCCH_5, CCCH_7 }, // Paging Block Index = 2.
83 { CCCH_6, CCCH_8 }, // Paging Block Index = 3.
84 { CCCH_7, CCCH_3 }, // Paging Block Index = 4.
85 { CCCH_8, CCCH_4 }, // Paging Block Index = 5.
86 { NULL, NULL }, // Paging Block Index = 6.
87 { NULL, NULL }, // Paging Block Index = 7.
88 { NULL, NULL }, // Paging Block Index = 8.
89
90 // BS_AG_BLKS_RES = 4.
91 // -------------------
92 // Paging, Ext Paging
93 { CCCH_4, CCCH_6 }, // Paging Block Index = 0.
94 { CCCH_5, CCCH_7 }, // Paging Block Index = 1.
95 { CCCH_6, CCCH_8 }, // Paging Block Index = 2.
96 { CCCH_7, CCCH_4 }, // Paging Block Index = 3.
97 { CCCH_8, CCCH_5 }, // Paging Block Index = 4.
98 { NULL, NULL }, // Paging Block Index = 5.
99 { NULL, NULL }, // Paging Block Index = 6.
100 { NULL, NULL }, // Paging Block Index = 7.
101 { NULL, NULL }, // Paging Block Index = 8.
102
103 // BS_AG_BLKS_RES = 5.
104 // -------------------
105 // Paging, Ext Paging
106 { CCCH_5, CCCH_7 }, // Paging Block Index = 0.
107 { CCCH_6, CCCH_8 }, // Paging Block Index = 1.
108 { CCCH_7, CCCH_5 }, // Paging Block Index = 2.
109 { CCCH_8, CCCH_6 }, // Paging Block Index = 3.
110 { NULL, NULL }, // Paging Block Index = 4.
111 { NULL, NULL }, // Paging Block Index = 5.
112 { NULL, NULL }, // Paging Block Index = 6.
113 { NULL, NULL }, // Paging Block Index = 7.
114 { NULL, NULL }, // Paging Block Index = 8.
115
116 // BS_AG_BLKS_RES = 6.
117 // -------------------
118 // Paging, Ext Paging,
119 { CCCH_6, CCCH_8 }, // Paging Block Index = 0.
120 { CCCH_7, CCCH_6 }, // Paging Block Index = 1.
121 { CCCH_8, CCCH_7 }, // Paging Block Index = 2.
122 { NULL, NULL }, // Paging Block Index = 3.
123 { NULL, NULL }, // Paging Block Index = 4.
124 { NULL, NULL }, // Paging Block Index = 5.
125 { NULL, NULL }, // Paging Block Index = 6.
126 { NULL, NULL }, // Paging Block Index = 7.
127 { NULL, NULL }, // Paging Block Index = 8.
128
129 // BS_AG_BLKS_RES = 7.
130 // -------------------
131 // Paging, Ext Paging
132 { CCCH_7, CCCH_7 }, // Paging Block Index = 0.
133 { CCCH_8, CCCH_8 }, // Paging Block Index = 1.
134 { NULL, NULL }, // Paging Block Index = 2.
135 { NULL, NULL }, // Paging Block Index = 3.
136 { NULL, NULL }, // Paging Block Index = 4.
137 { NULL, NULL }, // Paging Block Index = 5.
138 { NULL, NULL }, // Paging Block Index = 6.
139 { NULL, NULL }, // Paging Block Index = 7.
140 { NULL, NULL } // Paging Block Index = 8.
141 };
142
143 const T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)] =
144 // BS_CCCH_SDCCH_COMB = TRUE, BCCH combined.
145 {
146 // BS_AG_BLKS_RES = 0.
147 // -------------------
148 // Paging, Ext Paging, offset, working_area
149 { CCCH_0, CCCH_2 }, // Paging Block Index = 0.
150 { CCCH_1, CCCH_0 }, // Paging Block Index = 1.
151 { CCCH_2, CCCH_1 }, // Paging Block Index = 2.
152
153 // BS_AG_BLKS_RES = 1.
154 // -------------------
155 // Paging, Ext Paging, offset, working_area
156 { CCCH_1, CCCH_1 }, // Paging Block Index = 0.
157 { CCCH_2, CCCH_2 }, // Paging Block Index = 1.
158 { NULL, NULL }, // Paging Block Index = 2.
159
160 // BS_AG_BLKS_RES = 2.
161 // -------------------
162 // Paging, Ext Paging, offset, working_area
163 { CCCH_2, CCCH_2 }, // Paging Block Index = 0.
164 { NULL, NULL }, // Paging Block Index = 1.
165 { NULL, NULL } // Paging Block Index = 2.
166 };
167
168
169 /*-------------------------------------*/
170 /* Table giving the number of Paging */
171 /* blocks in a MF51. */
172 /* (called "N div BS_PA_MFRMS" in */
173 /* GSM05.02, Page 21). */
174 /*-------------------------------------*/
175
176 // BS_CCCH_SDCCH_COMB = False, BCCH not combined.
177 const UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)] =
178 {
179 9, // BS_AG_BLKS_RES = 0.
180 8, // BS_AG_BLKS_RES = 1.
181 7, // BS_AG_BLKS_RES = 2.
182 6, // BS_AG_BLKS_RES = 3.
183 5, // BS_AG_BLKS_RES = 4.
184 4, // BS_AG_BLKS_RES = 5.
185 3, // BS_AG_BLKS_RES = 6.
186 2 // BS_AG_BLKS_RES = 7.
187 };
188
189 // BS_CCCH_SDCCH_COMB = True, BCCH combined.
190 const UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)] =
191 {
192 3, // BS_AG_BLKS_RES = 0.
193 2, // BS_AG_BLKS_RES = 1.
194 1 // BS_AG_BLKS_RES = 2.
195 };
196
197 // Initial value for Downlink Signalling failure Counter (DSC).
198 const UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-1] =
199 {
200 45, // BS_PA_MFRMS = 2.
201 30, // BS_PA_MFRMS = 3.
202 23, // BS_PA_MFRMS = 4.
203 18, // BS_PA_MFRMS = 5.
204 15, // BS_PA_MFRMS = 6.
205 13, // BS_PA_MFRMS = 7.
206 11, // BS_PA_MFRMS = 8.
207 10 // BS_PA_MFRMS = 9.
208 };
209
210 // REM: 2nd block of SDCCH is always at the same position as the first block
211 // but 1 mf51 later.
212 // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks).
213 // Here is given the area starting position. This position is chosen
214 // to allow the equations for SBCNF51 occurence as it is in the l1s
215 // scheduler (the area do not overlap the end of 102 multiframe
216 // structure).
217 // Table for SDCCH description, Down Link & Up link, Not combined case.
218 const T_SDCCH_DESC SDCCH_DESC_NCOMB[8] =
219 {
220 // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area"
221 { 51 - 12 , 32 - 12 , 15 - 12 , 47 - 12 , 70 - 12 }, // SDCCH, D0
222 { 55 - 12 , 36 - 12 , 19 - 12 , 51 - 12 , 74 - 12 }, // SDCCH, D1
223 { 59 - 12 , 40 - 12 , 23 - 12 , 55 - 12 , 78 - 12 }, // SDCCH, D2
224 { 12 - 12 , 44 - 12 , 27 - 12 , 59 - 12 , 82 - 12 }, // SDCCH, D3
225 { 16 - 12 , 83 - 12 , 31 - 12 , 98 - 12 , 35 - 12 }, // SDCCH, D4
226 { 20 - 12 , 87 - 12 , 35 - 12 , 102 - 12 , 39 - 12 }, // SDCCH, D5
227 { 24 - 12 , 91 - 12 , 39 - 12 , 4 - 12 + 102 , 43 - 12 }, // SDCCH, D6
228 { 28 - 12 , 95 - 12 , 43 - 12 , 8 - 12 + 102 , 47 - 12 } // SDCCH, D7
229 };
230
231 // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks).
232 // Here is given the area starting position. This position is chosen
233 // to allow the equations for SBCNF51 occurence as it is in the l1s
234 // scheduler (the area do not overlap the end of 102 multiframe
235 // structure).
236 // Table for SDCCH description, Down Link & Up link, Combined case.
237 const T_SDCCH_DESC SDCCH_DESC_COMB[4] =
238 {
239 // "dl_D" , "dl_A" , "ul_D" , "ul_A". , "monit. area"
240 { 73 - 37 , 42 - 37 , 37 - 37 , 57 - 37 , 92 - 37 }, // SDCCH, D0
241 { 77 - 37 , 46 - 37 , 41 - 37 , 61 - 37 , 96 - 37 }, // SDCCH, D1
242 { 83 - 37 , 93 - 37 , 47 - 37 , 6 - 37 + 102 , 51 - 37 }, // SDCCH, D2
243 { 87 - 37 , 97 - 37 , 51 - 37 , 10 - 37 + 102 , 55 - 37 } // SDCCH, D3
244 };
245
246 // Table for HOPPING SEQUENCE GENERATION ALGORITHM.
247 const UWORD8 RNTABLE[114] =
248 {
249 48, 98, 63, 1, 36, 95, 78, 102, 94, 73,
250 0, 64, 25, 81, 76, 59, 124, 23, 104, 100,
251 101, 47, 118, 85, 18, 56, 96, 86, 54, 2,
252 80, 34, 127, 13, 6, 89, 57, 103, 12, 74,
253 55, 111, 75, 38, 109, 71, 112, 29, 11, 88,
254 87, 19, 3, 68, 110, 26, 33, 31, 8, 45,
255 82, 58, 40, 107, 32, 5, 106, 92, 62, 67,
256 77, 108, 122, 37, 60, 66, 121, 42, 51, 126,
257 117, 114, 4, 90, 43, 52, 53, 113, 120, 72,
258 16, 49, 7, 79, 119, 61, 22, 84, 9, 97,
259 91, 15, 21, 24, 46, 39, 93, 105, 65, 70,
260 125, 99, 17, 123
261 };
262
263
264 // Table giving the RACH slot positions when COMBINED.
265 // Rem: all is shifted left by 1 to map the position of the possible "contoles".
266 const UWORD8 COMBINED_RA_DISTRIB[51] =
267 {
268 0, 0, 0,
269 1, 1,
270 0, 0, 0, 0, 0, 0, 0, 0,
271 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
272 0, 0, 0, 0, 0, 0, 0, 0,
273 1, 1,
274 0, 0, 0, 0, 0
275 };
276
277 #if !L1_GPRS
278 const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] =
279 {
280 { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST
281 { BLOC_ADC , BLOC_ADC_SIZE }, // ADC in CS_MODE0
282 { NULL, 0 }, // DEDIC (not meaningfull)
283 { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC
284 { NULL, 0 }, // RAHO (not meaningfull)
285 { NULL, 0 }, // NSYNC (not meaningfull)
286 { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW
287 { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF
288 { BLOC_SB2, BLOC_SB2_SIZE }, // SB2
289 { BLOC_FB26, BLOC_FB26_SIZE }, // FB26
290 { BLOC_SB26, BLOC_SB26_SIZE }, // SB26
291 { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26
292 { BLOC_FB51, BLOC_FB51_SIZE }, // FB51
293 { BLOC_SB51, BLOC_SB51_SIZE }, // SB51
294 { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51
295 { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN
296 { BLOC_ALLC, S_RECT4_SIZE }, // ALLC
297 { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS
298 { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS
299 { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB
300 { BLOC_NP, S_RECT4_SIZE }, // NP
301 { BLOC_EP, S_RECT4_SIZE }, // EP
302 { BLOC_ADL, S_RECT4_SIZE }, // ADL
303 { BLOC_AUL, S_RECT4_SIZE }, // AUL
304 { BLOC_DDL, S_RECT4_SIZE }, // DDL
305 { BLOC_DUL, S_RECT4_SIZE }, // DUL
306 { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD
307 { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA
308 { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF
309 { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH
310 { BLOC_BCCHN_TOP,BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP
311 #if ((REL99 == 1) && (FF_BHO == 1))
312 { BLOC_FBSB, BLOC_FBSB_SIZE }, // FBSB
313 #endif
314 { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO
315 };
316
317 const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] =
318 {
319 CHECKSUM_DSP_TASK,// HWTEST
320 0, // DEDIC (not meaningfull)
321 0, // ADC (not meaningfull)
322 RACH_DSP_TASK, // RAACC
323 RACH_DSP_TASK, // RAHO
324 0, // NSYNC (not meaningfull)
325 FB_DSP_TASK, // FBNEW
326 SB_DSP_TASK, // SBCONF
327 SB_DSP_TASK, // SB2
328 TCH_FB_DSP_TASK, // FB26
329 TCH_SB_DSP_TASK, // SB26
330 TCH_SB_DSP_TASK, // SBCNF26
331 FB_DSP_TASK, // FB51
332 SB_DSP_TASK, // SB51
333 SB_DSP_TASK, // SBCNF51
334 NBN_DSP_TASK, // BCCHN
335 ALLC_DSP_TASK, // ALLC
336 NBS_DSP_TASK, // EBCCHS
337 NBS_DSP_TASK, // NBCCHS
338 DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB
339 NP_DSP_TASK, // NP
340 EP_DSP_TASK, // EP
341 ADL_DSP_TASK, // ADL
342 AUL_DSP_TASK, // AUL
343 DDL_DSP_TASK, // DDL
344 DUL_DSP_TASK, // DUL
345 TCHD_DSP_TASK, // TCHD
346 TCHA_DSP_TASK, // TCHA
347 TCHT_DSP_TASK, // TCHTF
348 TCHT_DSP_TASK, // TCHTH
349 NBN_DSP_TASK, // BCCHN_TOP == BCCHN
350 #if ((REL99 == 1) && (FF_BHO == 1))
351 FBSB_DSP_TASK, // FBSB
352 #endif
353 0, // SYNCHRO (not meaningfull)
354 };
355 #else
356 const T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] =
357 {
358 { BLOC_HWTEST, BLOC_HWTEST_SIZE }, // HWTEST
359 { BLOC_ADC, BLOC_ADC_SIZE }, // ADC in CS_MODE0
360 { NULL, 0 }, // DEDIC (not meaningfull)
361 { BLOC_RAACC, BLOC_RAACC_SIZE }, // RAACC
362 { NULL, 0 }, // RAHO (not meaningfull)
363 { NULL, 0 }, // NSYNC (not meaningfull)
364 { BLOC_POLL , BLOC_POLL_SIZE }, // POLL
365 { BLOC_PRACH, BLOC_PRACH_SIZE }, // PRACH
366 { BLOC_ITMEAS, BLOC_ITMEAS_SIZE }, // ITMEAS
367 { BLOC_FBNEW, BLOC_FBNEW_SIZE }, // FBNEW
368 { BLOC_SBCONF, BLOC_SBCONF_SIZE }, // SBCONF
369 { BLOC_SB2, BLOC_SB2_SIZE }, // SB2
370 { BLOC_PTCCH, BLOC_PTCCH_SIZE }, // PTCCH
371 { BLOC_FB26, BLOC_FB26_SIZE }, // FB26
372 { BLOC_SB26, BLOC_SB26_SIZE }, // SB26
373 { BLOC_SBCNF26, BLOC_SBCNF26_SIZE }, // SBCNF26
374 { BLOC_FB51, BLOC_FB51_SIZE }, // FB51
375 { BLOC_SB51, BLOC_SB51_SIZE }, // SB51
376 { BLOC_SBCNF51, BLOC_SBCNF51_SIZE }, // SBCNF51
377 { BLOC_PDTCH, BLOC_PDTCH_SIZE }, // PDTCH
378 { BLOC_BCCHN, BLOC_BCCHN_SIZE }, // BCCHN
379 { BLOC_ALLC, S_RECT4_SIZE }, // ALLC
380 { BLOC_EBCCHS, S_RECT4_SIZE }, // EBCCHS
381 { BLOC_NBCCHS, S_RECT4_SIZE }, // NBCCHS
382 { BLOC_ADL, S_RECT4_SIZE }, // ADL
383 { BLOC_AUL, S_RECT4_SIZE }, // AUL
384 { BLOC_DDL, S_RECT4_SIZE }, // DDL
385 { BLOC_DUL, S_RECT4_SIZE }, // DUL
386 { BLOC_TCHD, BLOC_TCHT_SIZE }, // TCHD
387 { BLOC_TCHA, BLOC_TCHA_SIZE }, // TCHA
388 { BLOC_TCHTF, BLOC_TCHT_SIZE }, // TCHTF
389 { BLOC_TCHTH, BLOC_TCHT_SIZE }, // TCHTH
390 { BLOC_PALLC, BLOC_PCCCH_SIZE }, // PALLC
391 { BLOC_SMSCB, BLOC_SMSCB_SIZE }, // SMSCB
392 { BLOC_PBCCHS, BLOC_PBCCHS_SIZE }, // PBCCHS
393 { BLOC_PNP, BLOC_PCCCH_SIZE }, // PNP
394 { BLOC_PEP, BLOC_PCCCH_SIZE }, // PEP
395 { BLOC_SINGLE, BLOC_SINGLE_SIZE }, // SINGLE
396 { BLOC_PBCCHN_TRAN, BLOC_PBCCHN_TRAN_SIZE }, // PBCCHN_TRAN
397 { BLOC_PBCCHN_IDLE, BLOC_PBCCHN_IDLE_SIZE }, // PBCCHN_IDLE
398 { BLOC_BCCHN_TRAN, BLOC_BCCHN_TRAN_SIZE }, // BCCHN_TRAN
399 { BLOC_NP, S_RECT4_SIZE }, // NP
400 { BLOC_EP, S_RECT4_SIZE }, // EP
401 { BLOC_BCCHN_TOP, BLOC_BCCHN_TOP_SIZE}, // BCCHN_TOP
402 #if ((REL99 == 1) && (FF_BHO == 1))
403 { BLOC_FBSB, BLOC_FBSB_SIZE }, // FBSB
404 #endif
405 { BLOC_SYNCHRO, BLOC_SYNCHRO_SIZE } // SYNCHRO
406 };
407
408 const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] =
409 {
410 CHECKSUM_DSP_TASK,// HWTEST
411 0, // ADC (not meaningfull)
412 0, // DEDIC (not meaningfull)
413 RACH_DSP_TASK, // RAACC
414 RACH_DSP_TASK, // RAHO
415 0, // NSYNC (not meaningfull)
416 0, // POLL (not meaningfull)
417 0, // PRACH (not meaningfull)
418 0, // ITMEAS
419 FB_DSP_TASK, // FBNEW
420 SB_DSP_TASK, // SBCONF
421 SB_DSP_TASK, // SB2
422 PTCCHU_DSP_TASK, // PTCCH
423 TCH_FB_DSP_TASK, // FB26
424 TCH_SB_DSP_TASK, // SB26
425 TCH_SB_DSP_TASK, // SBCNF26
426 FB_DSP_TASK, // FB51
427 SB_DSP_TASK, // SB51
428 SB_DSP_TASK, // SBCNF51
429 0, // PDTCH (not meaningfull)
430 NBN_DSP_TASK, // BCCHN
431 ALLC_DSP_TASK, // ALLC
432 NBS_DSP_TASK, // EBCCHS
433 NBS_DSP_TASK, // NBCCHS
434 ADL_DSP_TASK, // ADL
435 AUL_DSP_TASK, // AUL
436 DDL_DSP_TASK, // DDL
437 DUL_DSP_TASK, // DUL
438 TCHD_DSP_TASK, // TCHD
439 TCHA_DSP_TASK, // TCHA
440 TCHT_DSP_TASK, // TCHTF
441 TCHT_DSP_TASK, // TCHTH
442 0, // PALLC (not meaningfull)
443 DDL_DSP_TASK, // Temporary (BUG IN SIMULATOR) CB_DSP_TASK, // SMSCB
444 DDL_DSP_TASK, // PBCCHS (In order to allow PBCCHS running in CS or Idle mode, we have to specify a valid DSP task in order to request a PBCCHS with the GSM scheduler)
445 0, // PNP (not meaningfull)
446 0, // PEP (not meaningfull)
447 0, // SINGLE (not meaningfull)
448 0, // PBCCHN_TRAN (not meaningfull)
449 DDL_DSP_TASK, // PBCCHN_IDLE (only for GSM scheduler the task used is the same as SMSCB task)
450 NBN_DSP_TASK, // BCCHN_TRAN == BCCHN
451 NP_DSP_TASK, // NP
452 EP_DSP_TASK, // EP
453 NBN_DSP_TASK, // BCCHN_TOP == BCCHN
454 #if ((REL99 == 1) && (FF_BHO == 1))
455 FBSB_DSP_TASK, // FBSB
456 #endif
457 0 // SYNCHRO (not meaningfull)
458 };
459
460 #endif
461
462 const UWORD8 REPORTING_PERIOD[] =
463 {
464 255, // INVALID_CHANNEL -> invalid reporting period
465 104, // TCH_F
466 104, // TCH_H
467 102, // SDCCH_4
468 102 // SDCCH_8
469 };
470
471 const UWORD8 TOA_PERIOD_LEN[] =
472 {
473 0, // CS_MODE0 not used for histogram filling
474 12, // CS_MODE histogram length
475 12, // I_MODE histogram length
476 12, // CON_EST_MODE1 histogram length
477 144, // CON_EST_MODE2 histogram length
478 36, // DEDIC_MODE (Full rate) histogram length
479 42, // DEDIC_MODE (Half rate) histogram length
480 #if L1_GPRS
481 16, // PACKET TRANSFER MODE histogram length
482 #endif
483 };
484
485 // #if (STD == GSM)
486 const UWORD8 MIN_TXPWR_GSM[] =
487 {
488 0, // unused.
489 0, // Power class = 1, unused for GSM900
490 2, // Power class = 2.
491 3, // Power class = 3.
492 5, // Power class = 4.
493 7 // Power class = 5.
494 };
495 // #elif (STD == PCS1900)
496 const UWORD8 MIN_TXPWR_PCS[] =
497 {
498 0, // unused.
499 0, // Power class = 1.
500 3, // Power class = 2.
501 30 // Power class = 3.
502 };
503 // #elif (STD == DCS1800)
504 const UWORD8 MIN_TXPWR_DCS[] =
505 {
506 0, // unused.
507 0, // Power class = 1.
508 3, // Power class = 2.
509 29 // Power class = 3.
510 };
511
512 const UWORD8 MIN_TXPWR_GSM850[] =
513 {
514 0, // unused.
515 0, // Power class = 1, unused for GSM900
516 2, // Power class = 2.
517 3, // Power class = 3.
518 5, // Power class = 4.
519 7 // Power class = 5.
520 };
521
522 // #elif (STD == DUAL)
523 // const UWORD8 MIN_TXPWR_GSM[] =
524 // {
525 // 0, // unused.
526 // 0, // Power class = 1, unused for GSM900
527 // 2, // Power class = 2.
528 // 3, // Power class = 3.
529 // 5, // Power class = 4.
530 // 7 // Power class = 5.
531 // };
532 // const UWORD8 MIN_TXPWR_DCS[] =
533 // {
534 // 0, // unused.
535 // 0, // Power class = 1.
536 // 3, // Power class = 2.
537 // 29 // Power class = 3.
538 // };
539 // #endif
540
541 const UWORD8 GAUG_VS_PAGING_RATE[] =
542 {
543 4, // bs_pa_mfrms = 2, 1 gauging every 4 Paging blocs
544 3, // bs_pa_mfrms = 3, 1 gauging every 3 Paging blocs
545 2, // bs_pa_mfrms = 4, 1 gauging every 2 Paging blocs
546 1, // bs_pa_mfrms = 5, 1 gauging every 1 Paging bloc
547 1, // bs_pa_mfrms = 6, 1 gauging every 1 Paging bloc
548 1, // bs_pa_mfrms = 7, 1 gauging every 1 Paging bloc
549 1, // bs_pa_mfrms = 8, 1 gauging every 1 Paging bloc
550 1 // bs_pa_mfrms = 9, 1 gauging every 1 Paging bloc
551 };
552
553 #else
554 extern T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)];
555 extern T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)];
556 extern UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)];
557 extern UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)];
558 extern UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-2];
559 extern T_SDCCH_DESC SDCCH_DESC_NCOMB[];
560 extern T_SDCCH_DESC SDCCH_DESC_COMB[];
561 extern UWORD8 RNTABLE[114];
562 extern UWORD8 COMBINED_RA_DISTRIB[51];
563 extern T_TASK_MFTAB TASK_ROM_MFTAB[NBR_DL_L1S_TASKS];
564 extern UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS];
565 extern UWORD8 REPORTING_PERIOD[];
566 extern UWORD8 TOA_PERIOD_LEN[];
567 extern UWORD8 MIN_TXPWR_GSM[];
568 extern UWORD8 MIN_TXPWR_DCS[];
569 extern UWORD8 MIN_TXPWR_PCS[];
570 extern UWORD8 MIN_TXPWR_GSM850[];
571 extern UWORD8 GAUG_VS_PAGING_RATE[];
572 #endif
573 #endif //L1_TABS_H