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comparison L1/include/l1_time.h @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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children f93dab57b032
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-1:000000000000 0:75a11d740a02
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_TIME.H
4 *
5 * Filename l1_time.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 // *********************************************************************
11 // * *
12 // * This file contains only RF independant defines. *
13 // * *
14 // *********************************************************************
15 // Remarks:
16 // --------
17 // PRG_TX is RF dependant, it is therefore provided within
18 // "l1_rf#.h".
19 // **************************************************************************
20 //
21 // measurements
22 // ------------
23 //
24 // | +-----+
25 // | | PW |
26 // -------------------|--------+ +--------------
27 // clk=offset | |
28 // (frame int.) >|-----|<-PW_BURST_DURATION
29 // | | |
30 // | SYNTH_SETUP_TIME | |
31 // |<--------------------------|< |
32 // | | |
33 // | |
34 // >|--------|<-PROVISION_TIME
35 //
36 //
37 // Normal Burst reception
38 // ----------------------
39 //
40 // | +---------+
41 // | | RX WIN |
42 // ---------------------|--------+ +----------
43 // clk=offset | |
44 // (frame int.) >|---------|<-NB_BURST_DURATION_DL
45 // | | |
46 // | SYNTH_SETUP_TIME | |
47 // |<--------------------------|< |
48 // | | |
49 // | |
50 // >|--------|<-PROVISION_TIME
51 //
52 //
53 // Normal Burst transmission
54 // -------------------------
55 //
56 // .
57 // +---------+
58 // | TX WIN |
59 // --------------------------+ +----------
60 // . |
61 // clk=offset |
62 // . |
63 // . |<--STOP_TX_**
64 // | SYNTH_SETUP_TIME .
65 // |<---------------------->.<--START_TX
66 // | .
67 //
68 //
69 //
70 // Frequency Burst search in Dedicated TCH
71 // ---------------------------------------
72 //
73 // . +-----------(...)-------------+
74 // . | FB search in TCH |
75 // -------------------.--------+ +--------------
76 // . | |
77 // (FB26_ANCHORING_TIME)| |
78 // . | |
79 // SYNTH_SETUP_TIME | |
80 // |<------------------------->| |<-STOP_RX_FB26
81 // . |
82 // . |<-START_RX_FB26
83 // . |
84 // . |
85 // >.--------|<-PROVISION_TIME
86 //
87 //
88 // **************************************************************************
89
90
91 #define D_NSUBB_IDLE 296L // Nb of 48 samples window for FBNEW task.
92 #if (CODE_VERSION==SIMULATION)
93 #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task.
94 //To simulate the handling of the worst case (FB/SB task with class 12 allocation),
95 //this parameter used in the computation of FB26_ACQUIS_DURATION has to fit with the
96 //value used outside the PC simulation (D_NSUBB_DEDIC)
97 //This value will only be used for mac_mode = Extended Dynamic Allocation to minimize the
98 //impact on reference simulation files for other allocation modes
99 #if L1_EDA
100 #define D_NSUBB_DEDIC_EDA 30L // Nb of 48 samples window for FB26 task.
101 #endif
102 #else
103 #if (DSP >= 32)
104 #define D_NSUBB_DEDIC 30L // Nb of 48 samples window for FB26 task.
105 #else
106 #define D_NSUBB_DEDIC 31L // Nb of 48 samples window for FB26 task.
107 #endif
108 #endif
109
110
111 #define IMM ( 5000L ) // Immediate command for TPU.
112 #define TN_WIDTH ( 625L )
113 #define BP_DURATION TN_WIDTH
114 #define TAIL_WIDTH ( 3L * 4L ) // = 12
115 #define EXTENDED_TAIL_WIDTH ( 8L * 4L )
116 #define TPU_CLOCK_RANGE ( 5000L )
117 #define SWITCH_TIME ( TPU_CLOCK_RANGE - EPSILON_SYNC ) // = 4990, time for offset change.
118
119 #define PROVISION_TIME ( 66L )
120
121 #ifndef EPSILON_SYNC
122 #define EPSILON_SYNC ( 10L ) // synchro change: max TOA shift=8qbits, 2qbits TPU scenario exec.
123 #endif
124
125 #ifndef EPSILON_OFFS
126 #define EPSILON_OFFS ( 2L ) // offset change: 2qbits for TPU scenario exec.
127 #endif
128
129 #ifndef EPSILON_MEAS
130 #define EPSILON_MEAS ( 20L ) // margin kept between RX and PW meas or between PW meas
131 #endif
132
133 #ifndef SERV_OFFS_REST_LOAD
134 #define SERV_OFFS_REST_LOAD ( 1L ) // 1qbit TPU scen exec. for serv. cell offset restore
135 #endif
136
137 #define TPU_SLEEP_LOAD ( 2L ) // 2qbit TPU scen exec. for TPU sleep
138 #if (CODE_VERSION==SIMULATION)
139 #define DL_ABB_DELAY ( 32L ) // RX ABB filter delay
140 #else
141 #if (RF_FAM != 61)
142 #ifndef DL_ABB_DELAY //Flexi ABB Delays defines it in tpudrvXX.c
143 #define DL_ABB_DELAY ( 32L + 4L) // RX ABB filter delay
144 #endif
145 #endif
146 #if (RF_FAM == 61)
147 #ifndef DL_ABB_DELAY //Flexi ABB Delays defines it in tpudrvXX.c
148 #define DL_ABB_DELAY ( 41L + 4L) // RX DRP filter delay
149 #endif
150 #endif
151 #endif
152
153 // DMA threshold used for sample acquisition by the DSP
154 #if (CODE_VERSION==SIMULATION)
155 #define RX_DMA_THRES ( 1L )
156 #else
157 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
158 #define RX_DMA_THRES ( 2L )
159 #else
160 #define RX_DMA_THRES ( 1L )
161 #endif
162 #endif
163
164 // BDLENA durations are calculated for a DMA threshold of 1
165 // For a DMA threshold > 1 additional I/Q samples have to be acquired
166 // An increase of BDLENA length by 2qbit is sufficient to acquire one additional I/Q sample
167 // (ABB always outputs pairs of I/Q samples)
168 #define RX_DMA_DELAY (RX_DMA_THRES - 1) * 2
169
170 #if (CODE_VERSION==SIMULATION)
171 #define TULSET_DURATION ( 16L ) // Uplink power on setup time
172 #define BULRUDEL_DURATION ( 2L )
173 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
174 // 16 qbits are added because the Calibration time is reduced of 4 GSM bit
175 // due to a slow APC ramp of OMEGA (Cf. START_TX_NB)
176 #define UL_VEGA_DELAY ( TULSET_DURATION + BULRUDEL_DURATION +16L ) // = 18qbits, TX Vega delay
177 #endif
178 #endif
179
180 #define SB_MARGIN ( 23L * 4L ) // = 92
181 #define NB_MARGIN ( 3L * 4L ) // = 12
182
183 #ifndef TA_MAX //flexi Abb Delays defined in tpudrvXX.h
184 #define TA_MAX ( 63L * 4L ) // = 252
185 #endif
186
187 #define SB_BURST_DURATION ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation
188 #define NB_BURST_DURATION_DL ( TAIL_WIDTH + ( 142L * 4L) ) // = 580, required for Demodulation
189 #define PW_BURST_DURATION ( 64L * 4L ) // = 256
190 #define RA_BURST_DURATION ( EXTENDED_TAIL_WIDTH + TAIL_WIDTH + ( 77L * 4L ) ) // = 352 = 88*4
191 #define NB_BURST_DURATION_UL ( 2*TAIL_WIDTH + ( 142L * 4L) ) // = 592 = 148 * 4
192
193 // PRG_TX has become a variable and will be substracted directly in the code
194 #define TIME_OFFSET_TX ( PROVISION_TIME + (3L * TN_WIDTH)) // = 1902, Offset difference for TX with TA=0.
195
196 //================================
197 // Definitions used by TPU drivers
198 //================================
199
200 // BENA durations...
201 //------------------
202 #define SB_ACQUIS_DURATION ( SB_MARGIN + SB_BURST_DURATION + SB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 796 + DMA delay
203 #define NB_ACQUIS_DURATION ( NB_MARGIN + NB_BURST_DURATION_DL + NB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 636 + DMA delay
204 #define PW_ACQUIS_DURATION ( PW_BURST_DURATION + DL_ABB_DELAY + RX_DMA_DELAY ) // = 288 + DMA delay
205 #define FB_ACQUIS_DURATION ( ( D_NSUBB_IDLE * 48L * 4L ) + ( 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY ) // = 57056 + DMA delay
206 #if (L1_EDA) && (CODE_VERSION==SIMULATION)
207 #define FB26_ACQUIS_DURATION_DEFAULT ( ( D_NSUBB_DEDIC * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay
208 #define FB26_ACQUIS_DURATION_FOR_EDA ( ( D_NSUBB_DEDIC_EDA * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay
209 #else
210 #define FB26_ACQUIS_DURATION ( ( D_NSUBB_DEDIC * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY) // = 5984 + DMA delay
211 #endif
212
213 #define START_RX_FB ( PROVISION_TIME ) // = 66
214 #define START_RX_SB ( PROVISION_TIME ) // = 66
215 #define START_RX_SNB ( PROVISION_TIME ) // = 66
216 #define START_RX_PW_1 ( PROVISION_TIME ) // = 66
217 #define START_RX_FB26 ( PROVISION_TIME ) // = 66
218
219 #define START_TX_NB ( 0L )
220 #define START_TX_RA ( 0L )
221
222 #define STOP_RX_FB ( (PROVISION_TIME + FB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 2122
223 #define STOP_RX_SB ( (START_RX_SB + SB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 862
224 #if ((REL99 == 1) && (FF_BHO == 1))
225 #define STOP_RX_FBSB ( (STOP_RX_FB + 800L ) % TPU_CLOCK_RANGE ) // = 2922
226 #endif
227 #define STOP_RX_SNB ( (START_RX_SNB + NB_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 702
228 #define STOP_RX_PW_1 ( (START_RX_PW_1 + PW_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 354
229 #define STOP_RX_FB26 ( (START_RX_FB26 + FB26_ACQUIS_DURATION) % TPU_CLOCK_RANGE ) // = 4314
230
231 #if (REL99 == 1 && FF_RTD == 1) // RTD feature
232 #define RTD_UNIT_MARGIN ( ((TPU_CLOCK_RANGE-8)/128L) + 1 ) // unit of RTD is 1/64 TDMA frame
233 #define RTD_RIGHT_MARGIN ( (TA_MAX/2L) + (RTD_UNIT_MARGIN) )
234 #define RTD_LEFT_MARGIN ( RTD_RIGHT_MARGIN )
235 #endif
236
237 //================================
238 // Definitions used for GPRS
239 //================================
240
241 #if L1_GPRS
242 #ifdef L1P_DRIVE_C
243
244 // Window positions for RX normal burst reception durations
245 const UWORD16 RX_DOWN_TABLE[8] =
246 {
247 PROVISION_TIME + NB_ACQUIS_DURATION, //special case: only 1 RX, 151 IQ samples
248 PROVISION_TIME + 2*BP_DURATION + DL_ABB_DELAY, // 2 * 156.25 samples
249 PROVISION_TIME + 3*BP_DURATION + DL_ABB_DELAY, // 3 * 156.25 samples
250 PROVISION_TIME + 4*BP_DURATION + DL_ABB_DELAY, // 4 * 156.25 samples
251 PROVISION_TIME + 5*BP_DURATION + DL_ABB_DELAY, // 5 * 156.25 samples
252 PROVISION_TIME + 6*BP_DURATION + DL_ABB_DELAY, // 6 * 156.25 samples
253 PROVISION_TIME + 7*BP_DURATION + DL_ABB_DELAY, // 7 * 156.25 samples
254 PROVISION_TIME + 8*BP_DURATION + DL_ABB_DELAY // 8 * 156.25 samples
255 };
256
257 // Window positions for TX normal burst and PRACH transmission
258 const UWORD16 TX_TABLE[8] =
259 {
260 0,
261 BP_DURATION,
262 2*BP_DURATION,
263 3*BP_DURATION,
264 4*BP_DURATION,
265 5*BP_DURATION,
266 6*BP_DURATION,
267 7*BP_DURATION
268 };
269
270 #else
271
272 extern UWORD16 RX_DOWN_TABLE[8];
273 extern UWORD16 TX_TABLE[8];
274
275 #endif
276 #endif
277
278 //===============================================
279 // New Definitions for new WIN-ID implementation
280 //===============================================
281
282 #define BP_SPLIT_PW2 5
283 #define BP_SPLIT 32
284 #define FRAME_SPLIT 8*BP_SPLIT
285
286 // Load for TPU activity according to frame split
287 #define PWR_LOAD 1 + PW_ACQUIS_DURATION / (BP_DURATION/BP_SPLIT)
288 #define RX_LOAD 1 + NB_ACQUIS_DURATION / (BP_DURATION/BP_SPLIT)
289
290 #if L1_GPRS
291 #ifdef L1P_DRIVE_C
292
293 // RX split load in case of multislot
294 const UWORD16 RX_SPLIT_TABLE[8] =
295 {
296 1 + (NB_ACQUIS_DURATION ) / (BP_DURATION/BP_SPLIT),
297 1 + (2*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
298 1 + (3*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
299 1 + (4*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
300 1 + (5*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
301 1 + (6*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
302 1 + (7*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
303 1 + (8*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT)
304 };
305
306 #else
307
308 extern UWORD16 RX_SPLIT_TABLE[8];
309
310 #endif
311 #endif
312