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comparison L1/tpudrv/tpudrv.c @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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children 2dcce7bda202
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-1:000000000000 0:75a11d740a02
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename tpudrv.c
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8 /*
9 * TPUDRV.C
10 *
11 * TPU driver for Pole Star
12 *
13 *
14 * Copyright (c) Texas Instruments 1996
15 *
16 */
17
18 #include "config.h"
19 #include "l1_confg.h"
20 #include "l1_macro.h"
21 #include "../../bsp/iq.h"
22 #include "l1_const.h"
23 #include "l1_types.h"
24
25 #if (AUDIO_TASK == 1)
26 #include "l1audio_const.h"
27 #include "l1audio_cust.h"
28 #include "l1audio_defty.h"
29 #endif
30
31 #if (L1_GTT == 1)
32 #include "l1gtt_const.h"
33 #include "l1gtt_defty.h"
34 #endif
35
36 #if (L1_MIDI == 1)
37 #include "l1midi_defty.h"
38 #endif
39
40 #include "sys_types.h"
41
42 #if TESTMODE
43 #include "l1tm_defty.h"
44 #endif
45
46 #if (L1_MP3 == 1)
47 #include "l1mp3_defty.h"
48 #endif
49
50 #if (L1_MIDI == 1)
51 #include "l1midi_defty.h"
52 #endif
53
54 #if (L1_AAC == 1)
55 #include "l1aac_defty.h"
56 #endif
57 #include "l1_defty.h"
58 #include "tpudrv.h"
59 #include "sys_types.h"
60 #include "../../bsp/clkm.h"
61 #include "l1_time.h"
62 #include "l1_varex.h"
63 #include "l1_trace.h"
64
65 #if (L1_MADC_ON == 1)
66 #if (RF_FAM == 61)
67 #include "drp_api.h"
68 #include "l1_rf61.h"
69 #include "drp_drive.h"
70 #include "tpudrv61.h"
71 extern T_DRP_REGS_STR *drp_regs;
72 #endif
73 #endif //L1_MADC_ON
74
75 /* RFTime environment */
76 #if defined (HOST_TEST)
77 #include "hostmacros.h"
78 #endif
79
80
81 /*
82 * VEGA and OMEGA receive windows - Defined in Customer-specific file
83 */
84
85 extern UWORD32 debug_tpu;
86
87 #if ( OP_WCP == 1 ) && ( OP_L1_STANDALONE != 1 )
88 // WCS Patch : ADC during RX or TX
89 extern inline void GC_SetAdcInfo(unsigned char bTxBasedAdc);
90 #endif
91
92 /*
93 * Global Variables
94 */
95 // GSM1.5 : TPU MEMORY is 16-bit instead of 32 in Gemini/Polxx
96 //------------------------------------------------------------
97 SYS_UWORD16 *TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
98
99
100 /*--------------------------------------------------------------*/
101 /* TPU_Reset : Reset the TPU */
102 /*--------------------------------------------------------------*/
103 /* Parameters : on/off(1/0) */
104 /* Return : none */
105 /* Functionality : ) Reset the TPU */
106 /*--------------------------------------------------------------*/
107 void TPU_Reset(SYS_UWORD16 on)
108 {
109 if (on)
110 {
111 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_RESET;
112 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
113 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET));
114 }
115 else
116 {
117 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_RESET;
118 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
119 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET));
120 }
121 }
122
123 /*--------------------------------------------------------------*/
124 /* TSP_Reset : Reset the TSP */
125 /*--------------------------------------------------------------*/
126 /* Parameters : on/off(1/0) */
127 /* Return : none */
128 /* Functionality : ) Reset the TSP */
129 /*--------------------------------------------------------------*/
130 void TSP_Reset(SYS_UWORD16 on)
131 {
132 if (on)
133 {
134 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TSP_CTRL_RESET;
135 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
136 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET));
137 }
138 else
139 {
140 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TSP_CTRL_RESET;
141 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
142 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET));
143 }
144 }
145
146 /*--------------------------------------------------------------*/
147 /* TPU_SPIReset : Reset the SPI of the TPU */
148 /*--------------------------------------------------------------*/
149 /* Parameters : on/off(1/0) */
150 /* Return : none */
151 /* Functionality : ) the SPI of the TPU */
152 /*--------------------------------------------------------------*/
153
154 void TPU_SPIReset(SYS_UWORD16 on)
155 {
156 if (on)
157 {
158 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_SPI_RST;
159 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
160 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST));
161 }
162 else
163 {
164 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_SPI_RST;
165 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
166 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST));
167 }
168 }
169
170 /*--------------------------------------------------------------*/
171 /* TPU_ClkEnable : */
172 /*--------------------------------------------------------------*/
173 /* Parameters : on/off(1/0) */
174 /* Return : none */
175 /* Functionality : Enable the TPU clock */
176 /*--------------------------------------------------------------*/
177
178 void TPU_ClkEnable(SYS_UWORD16 on)
179 {
180 if (on)
181 {
182 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_CLK_EN;
183 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
184 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN));
185 }
186 else
187 {
188 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_CLK_EN;
189 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
190 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN));
191 }
192 }
193
194 /*--------------------------------------------------------------*/
195 /* TPU_Frame_ItOn : */
196 /*--------------------------------------------------------------*/
197 /* Parameters : bit of it to enable */
198 /* Return : none */
199 /* Functionality : Enable frame it */
200 /*--------------------------------------------------------------*/
201
202 /*-----------------------------------------------------------*/
203 /* Warning read modify write access to TPU_INT_CTRL register */
204 /* may generate problems using Hyperion. */
205 /*-----------------------------------------------------------*/
206
207 void TPU_FrameItOn(SYS_UWORD16 it)
208 {
209 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) &= ~it;
210 }
211
212 void TPU_FrameItEnable(void)
213 {
214 #if W_A_ITFORCE
215 (*(volatile SYS_UWORD16 *)TPU_INT_CTRL) |= TPU_INT_ITD_F;
216 #else
217 // enable IT_DSP generation on next frame
218 // reset by DSP when IT occurs
219 (*(volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_D_ENBL;
220 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
221 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL));
222 #endif
223 }
224
225 /*--------------------------------------------------------------*/
226 /* TPU_check_IT_DSP : */
227 /*--------------------------------------------------------------*/
228 /* Parameters : none */
229 /* Return : none */
230 /* Functionality : check if an IT DSP still pending */
231 /*--------------------------------------------------------------*/
232 BOOL TPU_check_IT_DSP(void)
233 { // return TRUE if an IT DSP still pending.
234 return( (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL) == TPU_CTRL_D_ENBL));
235 }
236
237 /*--------------------------------------------------------------*/
238 /* TPU_DisableAllIt : */
239 /*--------------------------------------------------------------*/
240 /* Parameters : none */
241 /* Return : none */
242 /* Functionality : Disabl all it */
243 /*--------------------------------------------------------------*/
244 void TPU_DisableAllIt()
245 {
246 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) |= TPU_INT_ITF_M | TPU_INT_ITP_M | TPU_INT_ITD_M;
247
248 }
249
250
251
252
253
254 /*
255 * TP_Program
256 *
257 * Write a null-terminated scenario into TPU memory at a given start address
258 * (Do not write terminating 0)
259 *
260 */
261 void *TP_Program(const SYS_UWORD16 *src)
262 {
263 /* Write TPU instructions until SLEEP */
264 while (*src)
265 {
266 *TP_Ptr++ = *src++;
267 }
268 #if 1 //(TOOL_CHOICE == 3) // 2.54 Migration
269 return((void *)NULL);
270 #endif // TOOL_CHOICE == 3
271 // return((void *)NULL);//ompas00090550
272
273 }
274
275
276
277 void TP_Reset(SYS_UWORD16 on)
278 {
279 if (on) {
280 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= (TPU_CTRL_RESET | TSP_CTRL_RESET);
281 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET)));
282 }
283 else {
284 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~(TPU_CTRL_RESET | TSP_CTRL_RESET);
285 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET)));
286 }
287 }
288
289 void TP_Enable(SYS_UWORD16 on)
290 {
291 if(on)
292 {
293 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_T_ENBL;
294
295 // Some time shall be wait before leaving the function to ensure that bit has been taken
296 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
297 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
298 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
299 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
300 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
301 }
302 else
303 {
304 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_T_ENBL;
305 // Some time shall be wait before leaving the function to ensure that bit has been taken
306 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
307 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
308 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
309 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
310 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
311 }
312 }
313
314
315 /*-----------------------------------------------------------------------*/
316 /* Function name: TPU_wait_idle */
317 /*-----------------------------------------------------------------------*/
318 /* */
319 /* Parameters: None */
320 /* */
321 /* Return: None */
322 /* */
323 /*-----------------------------------------------------------------------*/
324 /* Description: Wait until TPU scenario execution is complete */
325 /* */
326 /*-----------------------------------------------------------------------*/
327 void TPU_wait_idle(void)
328 {
329 while( ((*(volatile SYS_UWORD16 *) (TPU_CTRL)) & TPU_CTRL_TPU_IDLE) == TPU_CTRL_TPU_IDLE)
330 {
331 wait_ARM_cycles(convert_nanosec_to_cycles(3000));
332 }
333 }
334
335
336 /*
337 * l1dmacro_idle
338 *
339 * Write SLEEP instruction, start TPU and reset pointer
340 */
341 void l1dmacro_idle (void)
342 {
343 *TP_Ptr++ = TPU_SLEEP;
344
345 /* start TPU */
346 TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
347 TP_Enable(1);
348 }
349
350 /*
351 * l1dmacro_offset
352 *
353 * Set OFFSET register
354 *
355 */
356 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time)
357 {
358 // WARNING: 'relative time' and 'offset_value' must always be comprised
359 // between 0 and TPU_CLOCK_RANGE !!!
360
361 if (relative_time != IMM) // IMM indicates to set directly without AT
362 {
363 *TP_Ptr++ = TPU_FAT(relative_time);
364 }
365 *TP_Ptr++ = TPU_OFFSET(offset_value);
366 }
367
368 /*
369 * l1dmacro_synchro
370 *
371 * Set synchro register
372 */
373 void l1dmacro_synchro (UWORD32 when, UWORD32 value)
374 {
375 // WARNING: 'when' must always be comprised between 0 and TPU_CLOCK_RANGE !!!
376 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
377 trace_fct(CST_L1DMACRO_SYNCHRO, 1);//omaps00090550
378 #endif
379
380 if (value != IMM) // IMM indicates to set directly without AT
381 {
382 *TP_Ptr++ = TPU_FAT(when);
383 }
384
385 *TP_Ptr++ = TPU_SYNC(value);
386 l1s.tpu_offset_hw = value; // memorize the offset set into the TPU.
387 }
388
389
390 /*
391 * l1dmacro_adc_read
392 *
393 */
394 void l1dmacro_adc_read_rx(void)
395 {
396
397 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
398 // TSP needs to be configured in order to send serially to Omega
399
400 // *TP_Ptr++ = TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE); // Clock configuration
401 *TP_Ptr++ = TPU_WAIT (5);
402 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
403 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,STARTADC); // Load data to send
404 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
405 *TP_Ptr++ = TPU_WAIT (5);
406 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,0x00);
407 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
408
409 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
410 #if (GSM_IDLE_RAM == 0)
411 l1_trace_ADC(0);
412 #else
413 l1_trace_ADC_intram(0);
414 #endif
415 #endif
416 #endif
417
418 #if (L1_MADC_ON == 1)
419 #if (ANALOG == 11)
420
421 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
422 #if (GSM_IDLE_RAM == 0)
423 l1_trace_ADC(0);
424 #else
425 l1_trace_ADC_intram(0);
426 #endif
427 #endif
428 #endif
429
430 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
431 // WCS patch: ADC during RX
432 GC_SetAdcInfo(0);
433 #endif
434 #endif
435 }
436
437
438 #if (CODE_VERSION != SIMULATION)
439 #if (L1_MADC_ON ==1)
440 /*
441 * l1dmacro_adc_read_rx_cs_mode0
442 *
443 * Purpose:
444 * ======
445 * MADC is not enabled during CS_MODE0 periodically. MADC is enabled in CS_MODE0
446 * when Layer 1 receives MPHC_RXLEV_REQ from L23. However in CS_MODE0, MPHC_RXLEV_REQ
447 * is not received periodically. In case network is not found, the period between 2 MPHC_RXLEV_REQ
448 * increases and can be as high as 360 seconds (Maximum Value)
449 * This can result in battery related issues like phone powering off without MMI indication.
450 */
451
452
453 void l1dmacro_adc_read_rx_cs_mode0(void)
454 {
455 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,START_ADC);
456 *TP_Ptr++ = TPU_WAIT (2);
457 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,0);
458
459 #if (L1_MADC_ON == 1)
460 #if (ANALOG == 11)
461
462 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
463 #if (GSM_IDLE_RAM == 0)
464 l1_trace_ADC(0);
465 #else
466 l1_trace_ADC_intram(0);
467 #endif
468 #endif
469 #endif
470
471 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
472 // WCS patch: ADC during RX
473 GC_SetAdcInfo(0);
474 #endif
475 #endif
476 }
477
478
479 #endif //If MADC is enabled
480 #endif //If Not Simulation
481
482 /*
483 * l1dmacro_adc_read_tx
484 *
485 */
486
487
488 #if (ANALOG != 11)
489 void l1dmacro_adc_read_tx(UWORD32 when)
490 #else
491 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
492 #endif
493 {
494
495 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
496
497 *TP_Ptr++ = TPU_FAT (when);
498 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
499 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, STARTADC|BULON|BULENA); // Load data to send
500 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
501 *TP_Ptr++ = TPU_WAIT (5);
502 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, BULON|BULENA);
503 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
504
505 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
506 l1_trace_ADC(1);
507 #endif
508 #endif
509
510 #if (L1_MADC_ON == 1)
511 #if (ANALOG == 11)
512 *TP_Ptr++ = TPU_FAT (when);
513 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC);
514 *TP_Ptr++ = TPU_WAIT (2);
515 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
516
517 #if 1 // TEMP MEASUREMENT - uncomment and test after MADC
518 #if (RF_FAM == 61)
519 *TP_Ptr++ = TPU_MOVE(OCP_DATA_MSB, ((START_SCRIPT(DRP_TEMP_CONV))>>8) & 0xFF); \
520 *TP_Ptr++ = TPU_MOVE(OCP_DATA_LSB, (START_SCRIPT(DRP_TEMP_CONV)) & 0xFF); \
521 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_MSB, (((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)>>8) & 0xFF)); \
522 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_LSB, ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)) & 0xFF); \
523 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_START, 0x01); \
524 //TEMP_MEAS: Call TEMP Conv Script in DRP
525 //MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_TEMP_CONV),(UWORD16)(&drp_regs->SCRIPT_STARTL));
526 #endif
527
528 #endif
529
530 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
531 l1_trace_ADC(1);
532 #endif
533
534 #endif
535 #endif //L1_MADC_ON
536
537 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
538 // WCS patch: ADC during TX
539 GC_SetAdcInfo(1);
540 #endif
541
542
543 }
544
545
546 /*
547 #if (RF_FAM == 61)
548
549 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
550 {
551 int i;
552
553 *TP_Ptr++ = TPU_FAT (when);
554 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC);
555 *TP_Ptr++ = TPU_WAIT (2);
556 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
557
558 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
559 l1_trace_ADC(1);
560 #endif
561
562
563 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
564 // WCS patch: ADC during TX
565 GC_SetAdcInfo(1);
566 #endif
567 }
568
569 #endif
570 */
571
572 /*
573 * l1dmacro_set_frame_it
574 *
575 */
576 void l1dmacro_set_frame_it(void)
577 {
578 TPU_FrameItEnable();
579 }