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comparison L1/tpudrv/tpudrv.h @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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children b7d857ebc9ca
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1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename tpudrv.h
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8
9 /*
10 * Device addresses - GCS000
11 */
12 // GSM 1.5 : TPU / TSP addresses
13 //-------------------------------------
14
15 #if ((CHIPSET ==2) || (CHIPSET == 3) || (CHIPSET == 4))
16 #define TPU_ADDR 0xFFFE0000L //omaps00090550 // Hercule / Ulysse / Samson
17
18 #define TPU_RAM (TPU_ADDR + 0x1400)
19
20 #define TPU_REG (TPU_ADDR + 0x1000)
21 #define TSP_REG (TPU_ADDR + 0x0800)
22 #define TPU_TIM (TPU_ADDR + 0x2000)
23
24 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
25 #define TPU_ADDR 0xFFFF0000L // Strobe 1 address //omaps00090550
26
27 #define TPU_RAM 0xFFFF9000L // TPU RAM //omaps00090550
28
29 #define TPU_REG (TPU_ADDR + 0x1000) // TPU register
30 #define TSP_REG 0xFFFE0800L // TSP register //omaps00090550
31 #define TPU_TIM 0xFFFE2000L // ULPD register //omaps00090550
32
33 #elif (CHIPSET == 15)
34 #define TPU_ADDR 0xFFFFF000L // Strobe 1 address //omaps00090550
35
36 #define TPU_RAM 0xFFFF9000L // TPU RAM //omaps00090550
37
38 #define TPU_REG (TPU_ADDR) // TPU register
39
40 // TSP should be removed for Locosto. Leaving it as such as the TPU drivers are not yet ported.
41 #define TSP_REG 0xFFFE0800L // TSP register //omaps00090550
42 #define TPU_TIM 0xFFFE2000L // ULPD register //omaps00090550
43
44 #endif
45
46
47 /*
48 * Macros for defining TPU instructions
49 */
50 #define TPU_SLEEP 0
51 #define TPU_MOVE(addr,data) (0x8000 | ((data)<<5) | (addr))
52 #define TPU_AT(time) (0x2000 | (((time + 5000) % 5000)))
53 #define TPU_FAT(time) (0x2000 | (time)) // Fast version without modulo
54 #define TPU_SYNC(time) (0x6000 | (time))
55 #define TPU_WAIT(time) (0xA000 | (time))
56 #define TPU_OFFSET(time) (0x4000 | (time))
57 #define MOD5000(a) (((a) + 5000) % 5000)
58
59
60 /*
61 * TSP registers - defined in GCS004 - Time Serial Port
62 */
63 /*
64 * in TPU address space
65 */
66 // GSM 1.5 : TSP_TX_REG_1/2/3/4 instead of TSP_TX_U/M/L
67 // added TSP_SPI_SET1/2/3 to ctrl up to 5 periph.
68 //-----------------------------------------------------
69 #define TSP_CTRL1 0x00
70 #define TSP_CTRL2 0x01
71 #define TSP_TX_REG_1 0x04
72 #define TSP_TX_REG_2 0x03
73 #define TSP_TX_REG_3 0x02
74 #define TSP_TX_REG_4 0x05
75 #define TSP_ACT 0x06
76 #define TSP_ACTX 0x07
77 #define TSP_GAUGING_EN 0x11
78 #define TSP_SPI_SET1 0x09
79 #define TSP_SPI_SET2 0x0A
80 #define TSP_SPI_SET3 0x0B
81 #define TPU_IT_DSP_PG 0x10
82 #define TSP_GAUGING_EN 0x11
83
84 /*
85 * in ARM address space - defined in HYP004
86 */
87 #define TSP_RX_LSB (TSP_REG + 0x00)
88 #define TSP_RX_MSB (TSP_REG + 0x02)
89 #define TSP_TX_LSB (TSP_REG + 0x0c)
90 #define TSP_TX_MSB (TSP_REG + 0x0a)
91
92 /*
93 * TSP registers bit definitions
94 */
95 #define TC1_DEVICE0 0x00
96 #define TC1_DEVICE1 0x20
97 #define TC1_DEVICE2 0x40
98 #define TC1_DEVICE3 0x60
99 #define TC1_DEVICE4 0x80
100 #define TC2_RD 0x01
101 #define TC2_WR 0x02
102 #define TC2_EDGE_TRIG 0x40
103 #define TC2_RISING 0x80
104 #define TSP_CLK_RISE 0x01
105 #define TSP_ENA_POS 0x02
106 #define TSP_ENA_EDGE 0x04
107 #define GAUGING_START 0x01
108 #define GAUGING_STOP 0x00
109 #define TSP_ENA_POS_MSB 0x20
110
111
112
113 /*
114 * TPU registers - defined in HYP002
115 */
116 // GSM 1.5 : TPU reg are 16-bit access
117 //---------------------------------------
118 #define TPU_CTRL (TPU_REG + 0x00)
119 #define TPU_INT_CTRL (TPU_REG + 0x02)
120 #define TPU_INT_STAT (TPU_REG + 0x04)
121 #define TPU_OFFSET_REG (TPU_REG + 0x0C)
122 #define TPU_SYNCHRO_REG (TPU_REG + 0x0E)
123 #define TPU_DSP_PG (TPU_REG + 0x20)
124
125
126
127
128
129 /*
130 * TPU control register bits
131 */
132 // GSM 1.5 : TPU bits changed
133 //---------------------------------------
134 #define TPU_CTRL_RESET 0x0001
135 #define TSP_CTRL_RESET 0x0080
136 #define TPU_CTRL_T_PAGE 0x0002
137 #define TPU_CTRL_T_ENBL 0x0004
138 #define TPU_CTRL_D_ENBL 0x0010 // WARNING THIS BIT DOES NOT EXIST IN HYPERION
139 #define TPU_CTRL_SPI_RST 0x0080
140 #define TPU_CTRL_WAIT 0x0200
141 #define TPU_CTRL_CLK_EN 0x0400
142 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
143 #define TPU_CTRL_FULL_WRITE 0x0800
144 #endif
145
146
147
148
149 /*
150 * TPU interrupt control register bits
151 */
152
153
154 /* WARNING BUG IN HYPERION. */
155 /* READING TPU_INT_CRTL, TPU_INT_ITP_M BIT CONTENTS AFFECTS THE TPU_INT_ITD_M VALUE. */
156
157 #define TPU_INT_ITF_M 0x0001
158 #define TPU_INT_ITP_M 0x0002
159 #define TPU_INT_ITD_M 0x0004
160 #define TPU_INT_ITD_F 0x0008 // WARNING THIS BIT DOES NOT EXIST IN HYPERION
161
162 #define INT_FRAME 4 /* TPU frame interrupt */
163 #define INT_PAGE 5 /* TPU page interrupt */
164 #define INT_TSP 3 /* TSP interrupt */
165
166
167
168 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG==11))
169 // BB signals connected to serial link1
170 #define BULON 0x80 // bit6
171 #define BULCAL 0x40 // bit5
172 #define BULENA 0x20 // bit4
173 #define BDLON 0x10 // bit3
174 #define BDLCAL 0x08 // bit2
175 #define BDLENA 0x04 // bit1
176 #define STARTADC 0x02 // bit0
177 #endif
178
179 #if (RF_FAM == 61)
180 /* #define START_ADC 0x01 // TSPact 8 omaps00090550*/
181 // TSPACT
182 #define REG_SPI_ACT_U 0x07
183 #define REG_SPI_ACT_L 0x06
184
185 #endif
186 #define TPU_CTRL_TPU_IDLE 0x0100
187
188 /*
189 * GSM RF programming times in quarter bits
190 */
191 /**************************************************************************/
192 /**************************************************************************/
193 /****************************** W A R N I N G !!! *************************/
194 /******* This values are fine tuned for LAYER 1 . DO NOT MODIFY !!! *******/
195 /****** FOR ANY MODIFICATION , PLEASE CONTACT Texas Instruments Inc. ******/
196 /**************************************************************************/
197 /**************************************************************************/
198
199
200 /**************************************/
201 /* TPU Macros: prototypes functions */
202 /**************************************/
203 // TPU macros.
204 //------------
205 void l1dmacro_reset_hw (UWORD32 servingCellOffset);
206 void l1dmacro_init_hw (void);
207 void l1dmacro_idle (void);
208 void l1dmacro_rx_synth (SYS_UWORD16 radio_freq);
209 void l1dmacro_tx_synth (SYS_UWORD16 radio_freq);
210
211
212 #if (RF_FAM == 61)
213 void l1dmacro_agc (SYS_UWORD16 radio_freq, WORD8 gain, UWORD8 lna, UWORD8 if_ctl);
214 #endif
215 #if (RF_FAM != 61)
216 void l1dmacro_agc (SYS_UWORD16 radio_freq, WORD8 gain, UWORD8 lna);
217 #endif
218
219 void l1dmacro_afc (SYS_UWORD16 afc_value, UWORD8 win_id);
220 #if (L1_MADC_ON == 1)
221 #if (RF_FAM == 61)
222 void l1dmacro_rx_ms (SYS_UWORD16 radio_freq,UWORD8 adc_active);
223 void l1dmacro_rx_fb (SYS_UWORD16 radio_freq,UWORD8 adc_active);
224 void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq,UWORD8 adc_active);
225 #endif
226 #else
227 void l1dmacro_rx_ms (SYS_UWORD16 radio_freq);
228 void l1dmacro_rx_fb (SYS_UWORD16 radio_freq);
229 void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq);
230 #endif
231
232 void l1dmacro_offset (UWORD32 offset_value,
233 WORD32 relative_time);
234 void l1dmacro_synchro (UWORD32 when, UWORD32 value);
235 #if (L1_MADC_ON == 1)
236 #if (RF_FAM == 61)
237 void l1dmacro_rx_sb (SYS_UWORD16 radio_freq,UWORD8 adc_active);
238 void l1dmacro_rx_nb (SYS_UWORD16 radio_freq,UWORD8 adc_active, UWORD8 csf_filter_choice
239 #if (NEW_SNR_THRESHOLD == 1)
240 ,UWORD8 saic_flag
241 #endif /* NEW_SNR_THRESHOLD*/
242 );
243 #endif /* RF_FAM == 61*/
244 #else /* L1_MADC_ON == 1*/
245 void l1dmacro_rx_sb (SYS_UWORD16 radio_freq);
246 #if (RF_FAM == 61)
247 void l1dmacro_rx_nb (SYS_UWORD16 radio_freq, UWORD8 csf_filter_choice);
248 #else
249 void l1dmacro_rx_nb (SYS_UWORD16 radio_freq);
250 #endif // RF_FAM
251 #endif // L1_MADC_ON
252
253 void l1dmacro_tx_nb (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
254 void l1dmacro_tx_ra (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
255
256 #if (L1_MADC_ON == 1)
257 #if (RF_FAM == 61)
258 void l1dmacro_adc_read_tx (UWORD32 when, UWORD8 tx_up_state);
259 #endif
260 #endif
261 #if (RF_FAM != 61)
262 void l1dmacro_adc_read_tx (UWORD32 when);
263 #endif
264
265 void l1dmacro_adc_read_rx (void);
266
267 #if (CODE_VERSION != SIMULATION)
268 #if (L1_MADC_ON ==1)
269 void l1dmacro_adc_read_rx_cs_mode0(void);
270 #endif
271 #endif
272
273
274 void l1dmacro_set_frame_it (void);
275 void l1dmacro_init_hw_light (void);
276
277 #if TESTMODE
278 #if (L1_MADC_ON == 1)
279 #if (RF_FAM == 61)
280 void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr,UWORD8 adc_active, UWORD8 csf_filter_choice
281 #if (NEW_SNR_THRESHOLD == 1)
282 ,UWORD8 saic_flag
283 #endif /* NEW_SNR_THRESHOLD*/
284 );
285 #endif /* RF_FAM == 1*/
286 #else /* L1_MADC_ON == 1*/
287 #if (RF_RAM == 61)
288 void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 csf_filter_choice);
289 #else
290 void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
291 #endif /* RF_FAM */
292 #endif /* L1_MADC_ON */
293 void l1dmacro_tx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
294 void l1dmacro_stop_cont (void);
295 #endif /* TESTMODE */
296
297 /*
298 * TPU prototypes
299 */
300 void TP_PageIntHandler (void);
301 void TP_FrameIntHandler (void);
302 void TP_PageIntHandler (void);
303 void TP_FrameIntHandler (void);
304 void TPU_Reset(SYS_UWORD16 on);
305 void TSP_Reset(SYS_UWORD16 on);
306 void TPU_ClkEnable(SYS_UWORD16 on);
307 void TP_Reset(SYS_UWORD16 on);
308 void TP_Enable(SYS_UWORD16 on);
309 BOOL TPU_check_IT_DSP(void);
310
311
312 /*
313 * TPUDRV global variables
314 */
315 #ifdef TPUDRV_C
316 #define TP_GLOBAL
317 #else
318 #define TP_GLOBAL extern
319 #endif
320
321 TP_GLOBAL volatile UWORD32 TP_PageInt;
322 TP_GLOBAL volatile UWORD32 TP_FrameInt;