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comparison bsp/abb+spi/spi_drv.h @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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1 /******************************************************************************/
2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
3 /* */
4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This*/
6 /* product is protected under copyright law and trade secret law as an*/
7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All*/
8 /* rights reserved. */
9 /* */
10 /* */
11 /* Filename : spi_drv.h */
12 /* */
13 /* Description : SPI registers and bits definitions. */
14 /* Functions and macros to drive the SPI module. */
15 /* The Serial Port Interface is a bidirectional 3 lines */
16 /* interface dedicated to the transfer of data to and */
17 /* from up to 5 external devices offering a 3 lines */
18 /* serial interface. */
19 /* In this project, it is only used to connect the TI */
20 /* Analog BaseBand (ABB). */
21 /* It is assumed that the ABB is connected as the SPI */
22 /* device 0. */
23 /* */
24 /* This interface is specified to be compatible with */
25 /* the UMA1018M Philips, the FUJITSU MB15F02, the */
26 /* SIEMENS PMB2306T synthesizers and the TI ABB. */
27 /* */
28 /* This serial port is based on a looped shift-register */
29 /* thus allowing both transmit (PISO) and receive (SIPO) */
30 /* modes. */
31 /* */
32 /* */
33 /* Author : Pascal PUEL */
34 /* */
35 /* Version number : 1.28 */
36 /* */
37 /* Date and time : 07/01/03 */
38 /* */
39 /* Previous delta : Rework */
40 /* */
41 /******************************************************************************/
42
43 #ifndef __SPI_DRV_H__
44 #define __SPI_DRV_H__
45
46 #include "../../include/config.h"
47 #include "../../include/sys_types.h"
48
49 #include "../mem.h"
50
51 // SPI module registers definition
52 #define SPI_REG_SET1 (MEM_SPI + 0x00)
53 #define SPI_REG_SET2 (MEM_SPI + 0x02)
54 #define SPI_REG_CTRL (MEM_SPI + 0x04)
55 #define SPI_REG_STATUS (MEM_SPI + 0x06)
56 #define SPI_REG_TX_LSB (MEM_SPI + 0x08)
57 #define SPI_REG_TX_MSB (MEM_SPI + 0x0A)
58 #define SPI_REG_RX_LSB (MEM_SPI + 0x0C)
59 #define SPI_REG_RX_MSB (MEM_SPI + 0x0E)
60
61
62 // SPI module bits definition of register SPI_REG_SET1
63 #define SPI_CLK_OFF 0x0000 // default value
64 #define SPI_CLK_ON 0x0001
65 #define SPI_CLOCK_DIV_1 0x0000 // default value
66 #define SPI_CLOCK_DIV_2 0x0002
67 #define SPI_CLOCK_DIV_4 0x0004
68 #define SPI_CLOCK_DIV_8 0x0006
69 #define SPI_CLOCK_DIV_16 0x0008
70 #if (CHIPSET == 12)
71 #define SPI_CLOCK_DIV_32 0x000A
72 #define SPI_CLOCK_DIV_64 0x000C
73 #define SPI_CLOCK_DIV_128 0x000E
74 #endif
75 #define SPI_IT_MASK_0 0x0010 // default value
76 #define SPI_IT_DEMASK_0 0x0000
77 #define SPI_IT_MASK_1 0x0020 // default value
78 #define SPI_IT_DEMASK_1 0x0000
79
80
81 // SPI module bits definition of register SPI_REG_SET2
82 #define SPI_CLK_EDG_FALL 0x0000 // default value for device 0
83 #define SPI_CLK_EDG_RISE 0x0001
84 #define SPI_CLK_EDG_FALL_1 0x0000 // default value for device 1
85 #define SPI_CLK_EDG_RISE_1 0x0002
86 #define SPI_CLK_EDG_FALL_2 0x0000 // default value for device 2
87 #define SPI_CLK_EDG_RISE_2 0x0004
88 #define SPI_CLK_EDG_FALL_3 0x0000 // default value for device 3
89 #define SPI_CLK_EDG_RISE_3 0x0008
90 #define SPI_CLK_EDG_FALL_4 0x0000 // default value for device 4
91 #define SPI_CLK_EDG_RISE_4 0x0010
92 #define SPI_NTSPEN_NEG_LEV 0x0000 // default value for device 0
93 #define SPI_NTSPEN_POS_LEV 0x0020
94 #define SPI_NTSPEN_NEG_LEV_1 0x0000 // default value for device 1
95 #define SPI_NTSPEN_POS_LEV_1 0x0040
96 #define SPI_NTSPEN_NEG_LEV_2 0x0000 // default value for device 2
97 #define SPI_NTSPEN_POS_LEV_2 0x0080
98 #define SPI_NTSPEN_NEG_LEV_3 0x0000 // default value for device 3
99 #define SPI_NTSPEN_POS_LEV_3 0x0100
100 #define SPI_NTSPEN_NEG_LEV_4 0x0000 // default value for device 4
101 #define SPI_NTSPEN_POS_LEV_4 0x0200
102 #define SPI_NTSPEN_LEV_TRIG 0x0000 // default value for device 0
103 #define SPI_NTSPEN_EDG_TRIG 0x0400
104 #define SPI_NTSPEN_LEV_TRIG_1 0x0000 // default value for device 1
105 #define SPI_NTSPEN_EDG_TRIG_1 0x0800
106 #define SPI_NTSPEN_LEV_TRIG_2 0x0000 // default value for device 2
107 #define SPI_NTSPEN_EDG_TRIG_2 0x1000
108 #define SPI_NTSPEN_LEV_TRIG_3 0x0000 // default value for device 3
109 #define SPI_NTSPEN_EDG_TRIG_3 0x2000
110 #define SPI_NTSPEN_LEV_TRIG_4 0x0000 // default value for device 4
111 #define SPI_NTSPEN_EDG_TRIG_4 0x4000
112
113
114 // SPI module bits definition of register SPI_REG_CTRL
115 #define SPI_RDWR_DEACTIV 0x0000 // default value
116 #define SPI_RDWR_ACTIV 0x0001
117 #define SPI_WR_DEACTIV 0x0000 // default value
118 #define SPI_WR_ACTIV 0x0002
119 #define SPI_WNB_0 0x0000 // default value
120 #define SPI_WNB_1 0x0004
121 #define SPI_WNB_2 0x0008
122 #define SPI_WNB_3 0x000c
123 #define SPI_WNB_4 0x0010
124 #define SPI_WNB_5 0x0014
125 #define SPI_WNB_6 0x0018
126 #define SPI_WNB_7 0x001c
127 #define SPI_WNB_8 0x0020
128 #define SPI_WNB_9 0x0024
129 #define SPI_WNB_10 0x0028
130 #define SPI_WNB_11 0x002c
131 #define SPI_WNB_12 0x0030
132 #define SPI_WNB_13 0x0034
133 #define SPI_WNB_14 0x0038
134 #define SPI_WNB_15 0x003c
135 #define SPI_WNB_16 0x0040
136 #define SPI_WNB_17 0x0044
137 #define SPI_WNB_18 0x0048
138 #define SPI_WNB_19 0x004c
139 #define SPI_WNB_20 0x0050
140 #define SPI_WNB_21 0x0054
141 #define SPI_WNB_22 0x0058
142 #define SPI_WNB_23 0x005c
143 #define SPI_WNB_24 0x0060
144 #define SPI_WNB_25 0x0064
145 #define SPI_WNB_26 0x0068
146 #define SPI_WNB_27 0x006c
147 #define SPI_WNB_28 0x0070
148 #define SPI_WNB_29 0x0074
149 #define SPI_WNB_30 0x0078
150 #define SPI_WNB_31 0x007c
151
152
153 // SPI possible device IDs
154 #define SPI_DEV0 0x0000
155 #define SPI_DEV1 0x0080
156 #define SPI_DEV2 0x0100
157 #define SPI_DEV3 0x0180
158 #define SPI_DEV4 0x0200
159
160 // ABB should be mapped as device 0
161 #define ABB SPI_DEV0
162
163
164 // SPI module bits definition of register SPI_REG_STATUS
165 #define RE_ST 0x0001 // bit 0
166 #define WE_ST 0x0002 // bit 1
167
168
169 /* The ARM emulator requires the spi clock always ON to be able to access */
170 /* spi registers through a window.*/
171 /* But it's better to stop the SPI clock in the GSM application to reduce the power consumption. */
172 /* Validate the next line to reduce power consumption */
173 //#define SPI_CLK_LOW_POWER
174
175
176
177 // STRUCTURES
178 typedef struct
179 {
180 SYS_UWORD16 PrescVal;
181 SYS_UWORD16 DataTrLength;
182 SYS_UWORD16 DevAddLength;
183 SYS_UWORD16 DevId;
184 SYS_UWORD16 ClkEdge;
185 SYS_UWORD16 TspEnLevel;
186 SYS_UWORD16 TspEnForm;
187 }T_SPI_DEV; // T_SPI_DEV is used to define an SPI device
188
189
190 // MACROS
191 #define SPI_WRITE_TX_LSB(TxLsb) { \
192 * (volatile SYS_UWORD16 *) SPI_REG_TX_LSB = TxLsb; }
193
194 #define SPI_WRITE_TX_MSB(TxMsb) { \
195 * (volatile SYS_UWORD16 *) SPI_REG_TX_MSB = TxMsb; }
196
197 #define SPI_START_WRITE {* (volatile SYS_UWORD16 *) SPI_REG_CTRL |= SPI_WR_ACTIV; }
198
199 #define SPI_START_READ {* (volatile SYS_UWORD16 *) SPI_REG_CTRL |= SPI_RDWR_ACTIV; }
200
201 #define SPI_CLK_DISABLE { \
202 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_CLK_ON; }
203
204 #define SPI_CLK_ENABLE { \
205 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_CLK_ON; }
206
207 #define SPI_MaskIT_WR { \
208 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_IT_MASK_0; }
209
210 #define SPI_MaskIT_RD { \
211 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_IT_MASK_1; }
212
213 #define SPI_Mask_All_IT { \
214 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_IT_MASK_0 | SPI_IT_MASK_1); }
215
216 #define SPI_UnmaskIT_WR { \
217 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_IT_MASK_0; }
218
219 #define SPI_UnmaskIT_RD { \
220 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_IT_MASK_1; }
221
222 #define SPI_Unmask_All_IT { \
223 * (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~(SPI_IT_MASK_0 | SPI_IT_MASK_1); }
224
225 #define SPI_Ready_for_WR { \
226 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_0); }
227
228 #define SPI_Ready_for_RD { \
229 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_1); }
230
231 #define SPI_Ready_for_RDWR { \
232 * (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_0 | SPI_IT_MASK_1); }
233
234
235
236 // INLINE FUNCTIONS
237 /*-----------------------------------------------------------------------*/
238 /* SPI_ReadRX_LSB() */
239 /* */
240 /* This function returns the value of SPI_REG_RX_LSB register */
241 /* */
242 /*-----------------------------------------------------------------------*/
243 static inline SYS_UWORD16 SPI_ReadRX_LSB(void)
244 {
245 return * (volatile SYS_UWORD16 *) SPI_REG_RX_LSB;
246 }
247
248
249 /*-----------------------------------------------------------------------*/
250 /* SPI_ReadRX_MSB() */
251 /* */
252 /* This function returns the value of SPI_REG_RX_MSB register */
253 /* */
254 /*-----------------------------------------------------------------------*/
255 static inline SYS_UWORD16 SPI_ReadRX_MSB(void)
256 {
257 return * (volatile SYS_UWORD16 *) SPI_REG_RX_MSB;
258 }
259
260
261
262 /*-----------------------------------------------------------------------*/
263 /* SPI_ReadStatus() */
264 /* */
265 /* This function returns the value of SPI_REG_STATUS register */
266 /* */
267 /*-----------------------------------------------------------------------*/
268 static inline SYS_UWORD16 SPI_ReadStatus(void)
269 {
270 return * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
271 }
272
273
274
275 // PROTOTYPES
276 void SPI_InitDev(T_SPI_DEV *Device);
277
278 #endif // __SPI_DRV_H__