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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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1 /******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : clkm.h
12
13 Description : Header file for the CLKM module
14
15 Project : drivers
16
17 Author : pmonteil@tif.ti.com Patrice Monteil.
18
19 Version number : 1.10
20
21 Date and time : 10/23/01 14:34:54
22
23 Previous delta : 10/19/01 15:25:25
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_CLOCK/drivers1/common/SCCS/s.clkm.h
26
27 Sccs Id (SID) : '@(#) clkm.h 1.10 10/23/01 14:34:54 '
28
29 * FreeCalypso note: this version of clkm.h originates
30 * from the MV100-0.1.rar find.
31
32 *****************************************************************************/
33
34 #include "../include/config.h"
35 #include "../include/sys_types.h"
36
37 #define CLKM_ARM_CLK MEM_CLKM_ADDR /* CLKM ARM CLock Control reg.*/
38 #define CLKM_MCLK_EN 0x0001
39
40
41 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
42 #define MASK_CLKIN 0x0006
43 #endif
44
45 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
46 #define CLKM_CLKIN0 0x0002 // Mask to select between DPLL and VTCXO or CLKIN
47 #else
48 #define CLKM_LOW_FRQ 0x0002 // Mask to select low frequency input CLK_32K
49 #endif
50 #define CLKM_CLKIN_SEL 0x0004 // Mask to select between VTCXO and CLKIN
51
52 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
53 #define CLKM_ARM_MCLK_XP5 0x0008 // Mask to enable the 1.5 or 2.5 division factor
54 #define CLKM_MCLK_DIV 0x0070 // Mask to configure the division factor
55 #else
56 #define MASK_ARM_MCLK_1P5 0x0008 // Mask to enable the 1.5 division factor
57 #define CLKM_MCLK_DIV 0x0030 // Mask to configure the division factor
58 #endif
59
60 #define CLKM_DEEP_PWR 0x0f00 // Mask to configure deep power
61 #define CLKM_DEEP_SLEEP 0x1000 // Mask to configure deep sleep
62
63 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
64 #define CLKM_SEL_DPLL 0x0000 // Selection of DPLL for ARM clock generation
65 #define CLKM_SEL_VTCXO 0x0001 // Selection of VTCXO for ARM clock generation
66 #define CLKM_SEL_CLKIN 0x0003 // Selection of CLKIN for ARM clock generation
67
68 #define CLKM_ENABLE_XP5 0x0001 // Enable 1.5 or 2.5 division factor
69 #define CLKM_DISABLE_XP5 0x0000 // Disable 1.5 or 2.5 division factor
70
71 #define CLKM_ARM_MCLK_DIV_OFFSET 4 // Offset of ARM_MCLK_DIV bits in CNTL_ARM_CLK register
72
73 #define CLKM_ARM_CLK_RESET 0x1081 // Reset value of CNTL_ARM_CLK register
74 #endif
75
76 #define CLKM_CNTL_ARM_CLK (MEM_CLKM_ADDR + 0x00)
77 #define CLKM_CNTL_CLK (MEM_CLKM_ADDR + 2) /* CLKM Clock Control reg. */
78
79 #define CLKM_IRQ_DIS 0x0001 // IRQ clock is disabled and enabled according to the sleep command
80 #define CLKM_BRIDGE_DIS 0x0002 // BRIDGE clock is disabled and enabled according to the sleep command
81 #define CLKM_TIMER_DIS 0x0004 // TIMER clock is disabled and enabled according to the sleep command
82 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
83 #define CLKM_DPLL_DIS 0x0008 // DPLL is set in IDLE when both DSP and ARM are respectively in IDLE3 and sleep mode
84 #else
85 #define CLKM_PLL_SEL 0x0008 // CLKIN input is connected to the PLL
86 #endif
87 #define CLKM_CLKOUT_EN 0x0010 // Enable CLKOUT(2:0) output clocks
88 #if (CHIPSET == 4)
89 #define CLKM_EN_IDLE3_FLG 0x0020 // DSP idle flag control the API wait state
90 #define CLKM_VTCXO_26 0x0040 // VTCXO is divided by 2
91 #elif (CHIPSET == 6)
92 #define CLKM_VTCXO_26 0x0040 // VTCXO is divided by 2
93 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
94 #define CLKM_EN_IDLE3_FLG 0x0020 // DSP idle flag control the API wait state
95 #define CLKM_VCLKOUT_2 0x0040 // VTCXO is divided by 2
96 #define CLKM_VTCXO_2 0x0080 // Input clock to DPLL is divided by 2
97 #endif
98
99 #define CLKM_CNTL_RST (MEM_CLKM_ADDR + 4) /* CLKM Reset Control reg. */
100 #define CLKM_LEAD_RST 0x0002
101 #define CLKM_EXT_RST 0x0004
102
103 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
104 #define DPLL_LOCK 0x0001 // Mask of DPLL lock status
105 #define DPLL_BYPASS_DIV 0x000C // Mask of bypass mode configuration
106 #define DPLL_PLL_ENABLE 0x0010 // Enable DPLL
107 #define DPLL_PLL_DIV 0x0060 // Mask of division factor configuration
108 #define DPLL_PLL_MULT 0x0F80 // Mask of multiply factor configuration
109
110 #define DPLL_BYPASS_DIV_1 0x0 // Configuration of bypass mode divided by 1
111 #define DPLL_BYPASS_DIV_2 0x1 // Configuration of bypass mode divided by 2
112 #define DPLL_BYPASS_DIV_4 0x2 // Configuration of bypass mode divided by 4
113
114 #define DPLL_BYPASS_DIV_OFFSET 2 // Offset of bypass bits configuration
115 #define DPLL_PLL_DIV_OFFSET 5 // Offset of division bits configuration
116 #define DPLL_PLL_MULT_OFFSET 7 // Offset of multiply bits configuration
117
118 #define DPLL_LOCK_DIV_1 0x0000 // Divide by 1 when DPLL is locked
119 #define DPLL_LOCK_DIV_2 0x0001 // Divide by 2 when DPLL is locked
120 #define DPLL_LOCK_DIV_3 0x0002 // Divide by 3 when DPLL is locked
121 #define DPLL_LOCK_DIV_4 0x0003 // Divide by 4 when DPLL is locked
122
123 #else
124 #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6) /* Lead PLL */
125 #define CLKM_PLONOFF 0x0001 // PLL enable signal
126 #define CLKM_PLMUL 0x001e // Mask of multiply factor configuration
127 #define CLKM_PLLNDIV 0x0020 // PLL or divide mode selection
128 #define CLKM_PLDIV 0x0040 // Mask of multiply factor configuration
129 #define CLKM_LEAD_PLL_CNTL_MSK 0x00ef // Mask of PLL control register
130 #endif
131
132 #if (CHIPSET == 12)
133 #define CLKM_CNTL_CLK_DSP (MEM_CLKM_ADDR + 0x8A) /* CLKM CNTL_CLK_REG register */
134
135 #define CLKM_NB_DSP_DIV_VALUE 4
136
137 #define CLKM_DSP_DIV_1 0x00
138 #define CLKM_DSP_DIV_1_5 0x01
139 #define CLKM_DSP_DIV_2 0x02
140 #define CLKM_DSP_DIV_3 0x03
141
142 #define CLKM_DSP_DIV_MASK 0x0003
143
144 extern const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE];
145
146 /*---------------------------------------------------------------/
147 /* CLKM_DSP_DIV_FACTOR() */
148 /*--------------------------------------------------------------*/
149 /* Parameters : none */
150 /* Return : none */
151 /* Functionality : Set the DSP division factor */
152 /*--------------------------------------------------------------*/
153
154 #define CLKM_DSP_DIV_FACTOR(d_dsp_div) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP = d_dsp_div)
155
156
157 /*---------------------------------------------------------------/
158 /* CLKM_READ_DSP_DIV() */
159 /*--------------------------------------------------------------*/
160 /* Parameters : none */
161 /* Return : none */
162 /* Functionality : Read DSP division factor */
163 /*--------------------------------------------------------------*/
164
165 #define CLKM_READ_DSP_DIV ((* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP) & CLKM_DSP_DIV_MASK)
166
167 #define CLKM_GET_DSP_DIV_VALUE dsp_div_value[CLKM_READ_DSP_DIV]
168
169 #endif
170
171
172 /*---------------------------------------------------------------/
173 /* CLKM_SETLEADRESET() */
174 /*--------------------------------------------------------------*/
175 /* Parameters : none */
176 /* Return : none */
177 /* Functionality : Set the LEAD reset signal */
178 /*--------------------------------------------------------------*/
179
180 #define CLKM_SETLEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_LEAD_RST)
181
182 /*---------------------------------------------------------------/
183 /* CLKM_RELEASELEADRESET() */
184 /*--------------------------------------------------------------*/
185 /* Parameters : none */
186 /* Return : none */
187 /* Functionality : Release the LEAD reset signal */
188 /*--------------------------------------------------------------*/
189
190 #define CLKM_RELEASELEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_LEAD_RST)
191
192 /*---------------------------------------------------------------/
193 /* CLKM_SETEXTRESET() */
194 /*--------------------------------------------------------------*/
195 /* Parameters : none */
196 /* Return : none */
197 /* Functionality : Set the external reset signal */
198 /*--------------------------------------------------------------*/
199
200 #define CLKM_SETEXTRESET ( * (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_EXT_RST)
201
202 /*---------------------------------------------------------------/
203 /* CLKM_CLEAREXTRESET() */
204 /*--------------------------------------------------------------*/
205 /* Parameters : none */
206 /* Return : none */
207 /* Functionality : Clear the external reset signal */
208 /*--------------------------------------------------------------*/
209
210 #define CLKM_CLEAREXTRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_EXT_RST)
211
212
213 /*---------------------------------------------------------------/
214 /* CLKM_POWERDOWNARM() */
215 /*--------------------------------------------------------------*/
216 /* Parameters : none */
217 /* Return : none */
218 /* Functionality : Power down the ARM mcu */
219 /*--------------------------------------------------------------*/
220 #define CLKM_POWERDOWNARM (* (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_MCLK_EN)
221
222 /*---------------------------------------------------------------/
223 /* CLKM_SET1P5() */
224 /*--------------------------------------------------------------*/
225 /* Parameters : none */
226 /* Return : none */
227 /* Functionality : Set ARM_MCLK_1P5 bit */
228 /*--------------------------------------------------------------*/
229
230 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
231 #define CLKM_SETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= CLKM_ARM_MCLK_XP5)
232 #else
233 #define CLKM_SET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= 0x0008)
234 #endif
235
236 /*---------------------------------------------------------------/
237 /* CLKM_RESET1P5() */
238 /*--------------------------------------------------------------*/
239 /* Parameters : none */
240 /* Return : none */
241 /* Functionality : Reset ARM_MCLK_1P5 bit */
242 /*--------------------------------------------------------------*/
243
244 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
245 #define CLKM_RESETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_ARM_MCLK_XP5)
246 #else
247 #define CLKM_RESET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= 0xfff7)
248 #endif
249
250 /*---------------------------------------------------------------/
251 /* CLKM_INITCNTL() */
252 /*--------------------------------------------------------------*/
253 /* Parameters : value to write in the CNTL register */
254 /* Return : none */
255 /* Functionality :Initialize the CLKM Control Clock register */
256 /*--------------------------------------------------------------*/
257
258 #define CLKM_INITCNTL(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK = value)
259
260 /*
261 * NOTE: the version of the CLKM_INITCNTL() macro in the Sotomodem source
262 * does |= instead of =. It remains to be investigated which is more correct.
263 *
264 * For now I'll define the ORing version under a different (and more
265 * descriptive) name: CLKM_CNTL_OR.
266 */
267
268 #define CLKM_CNTL_OR(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= value)
269
270 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
271 /*---------------------------------------------------------------/
272 /* CLKM_INITLEADPLL() */
273 /*--------------------------------------------------------------*/
274 /* Parameters : value to write in the CNTL_PLL LEAD register */
275 /* Return : none */
276 /* Functionality :Initialize LEAD PLL control register */
277 /*--------------------------------------------------------------*/
278
279 #define CLKM_INITLEADPLL(value) (* (volatile SYS_UWORD16 *) CLKM_LEAD_PLL_CNTL = value)
280 #endif
281
282 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
283 /*---------------------------------------------------------------/
284 /* CLKM_DPLL_SWITH_OFF_MODE_CONFIG() */
285 /*--------------------------------------------------------------*/
286 /* Parameters : None */
287 /* Return : none */
288 /* Functionality : Configure DPLL switch off mode */
289 /*--------------------------------------------------------------*/
290
291 #define CLKM_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= \
292 (CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
293
294 /*---------------------------------------------------------------/
295 /* CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG() */
296 /*--------------------------------------------------------------*/
297 /* Parameters : None */
298 /* Return : none */
299 /* Functionality : Reset configuration of DPLL switch off mode */
300 /*--------------------------------------------------------------*/
301
302 #define CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &=\
303 ~(CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
304
305 /*---------------------------------------------------------------/
306 /* CLKM_FORCE_API_HOM_IN_IDLE3() */
307 /*--------------------------------------------------------------*/
308 /* Parameters : None */
309 /* Return : none */
310 /* Functionality : SAM/HOM wait-state register force to HOM when*/
311 /* DSP is in IDLE3 mode */
312 /*--------------------------------------------------------------*/
313
314 #define CLKM_FORCE_API_HOM_IN_IDLE3 (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_EN_IDLE3_FLG))
315
316 #if (CHIPSET == 4)
317 /*---------------------------------------------------------------/
318 /* CLKM_USE_VTCXO_26MHZ() */
319 /*--------------------------------------------------------------*/
320 /* Parameters : None */
321 /* Return : none */
322 /* Functionality : Divide by 2 the clock used by the peripheral */
323 /* when using external VTCXO at 26 MHz instead */
324 /* of 13MHz */
325 /*--------------------------------------------------------------*/
326
327 #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_26))
328
329 /*---------------------------------------------------------------/
330 /* CLKM_UNUSED_VTCXO_26MHZ() */
331 /*--------------------------------------------------------------*/
332 /* Parameters : None */
333 /* Return : none */
334 /* Functionality : Use VTCXO=13MHz */
335 /*--------------------------------------------------------------*/
336
337 #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VTCXO_26))
338 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
339 /*---------------------------------------------------------------/
340 /* CLKM_UNUSED_VTCXO_26MHZ() */
341 /*--------------------------------------------------------------*/
342 /* Parameters : None */
343 /* Return : none */
344 /* Functionality : Use VTCXO=13MHz */
345 /*--------------------------------------------------------------*/
346
347 #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_2))
348
349 #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VCLKOUT_2 | CLKM_VTCXO_2))
350 #endif
351
352
353 #define DPLL_SET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR |= DPLL_PLL_ENABLE)
354 #define DPLL_RESET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR &= ~DPLL_PLL_ENABLE)
355
356 #define DPLL_INIT_BYPASS_MODE(d_bypass_mode) { \
357 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~DPLL_BYPASS_DIV; \
358 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_bypass_mode << DPLL_BYPASS_DIV_OFFSET); \
359 }
360
361 #define DPLL_INIT_DPLL_CLOCK(d_pll_div, d_pll_mult) { \
362 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~(DPLL_PLL_DIV | DPLL_PLL_MULT); \
363 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_pll_div << DPLL_PLL_DIV_OFFSET) |\
364 (d_pll_mult << DPLL_PLL_MULT_OFFSET); \
365 }
366
367 #define DPLL_READ_DPLL_DIV ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_DIV) >> DPLL_PLL_DIV_OFFSET)
368 #define DPLL_READ_DPLL_MUL ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_MULT)>> DPLL_PLL_MULT_OFFSET)
369 #define DPLL_READ_DPLL_LOCK ( (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK)
370
371
372 #endif
373
374 /* ----- Prototypes ----- */
375
376 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
377 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5);
378 #else
379 void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div);
380 #endif
381
382 void wait_ARM_cycles(SYS_UWORD32 cpt_loop);
383 void initialize_wait_loop(void);
384 SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time);