FreeCalypso > hg > freecalypso-citrine

comparison bsp/init_target.c @ 0:75a11d740a02

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
parents
children
comparison
equal deleted inserted replaced
-1:000000000000 0:75a11d740a02
1 /*
2 * Init_Target() is the first function called from Application_Initialize().
3 * But unfortunately, our TCS211 semi-src has this function in a binary lib.
4 * I was able to find a conditioned-out version in the LoCosto source that
5 * seems to be a fit - so I'm going to massage it a bit to match the sequence
6 * of operations seen in the disassembly of our reference binary.
7 */
8
9 #include "../include/config.h"
10 #include "../include/sys_types.h"
11
12 #include "mem.h"
13 #include "clkm.h"
14 #include "armio.h"
15 #include "dma.h"
16 #include "timer.h"
17 #include "inth.h"
18 #include "iq.h"
19 #include "rhea_arm.h"
20 #include "ulpd.h"
21
22 #if !CONFIG_INCLUDE_L1
23 #include "timer2.h"
24 #endif
25
26 /* TPU_FREEZE is defined in l1_const.h */
27 #include "../L1/include/l1_confg.h"
28 #include "../L1/include/l1_const.h"
29
30 void Init_Target(void)
31 {
32 #if 1 //(PSP_STANDALONE == 0)
33 // RIF/SPI rising edge clock for ULYSSE
34 //--------------------------------------------------
35 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
36 #if ((CHIPSET >= 3))
37 #if (CHIPSET == 12)
38 F_CONF_RIF_RX_RISING_EDGE;
39 F_CONF_SPI_RX_RISING_EDGE;
40 #elif (CHIPSET == 15)
41 //do the DRP init here for Locosto
42 #if (L1_DRP == 1)
43 // drp_power_on(); This should be done after the script is downloaded.
44 #endif
45 #else
46 #if (BOARD==35)
47 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000;
48 #elif CONFIG_TARGET_PIRELLI // from disasm of original fw
49 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6050;
50 #else
51 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000;
52 #endif /* (BOARD == 35) */
53 #endif
54 #endif
55 #endif /* ANLG(ANALOG)) */
56
57 #if 0 //(OP_L1_STANDALONE == 1)
58 #if (BOARD == 40) || (BOARD == 41) || \
59 (BOARD == 42) || (BOARD == 43) || (BOARD == 45)
60 // enable 8 Ohm amplifier for audio on D-sample
61 AI_ConfigBitAsOutput (1);
62 AI_SetBit(1);
63 #elif (BOARD == 70) || (BOARD == 71)
64 //Locosto I-sample or UPP costo board.BOARD
65 // Initialize the ARMIO bits as per the I-sample spec
66 // FIXME
67 #endif
68 #endif /* (OP_L1_STANDALONE == 1) */
69 #endif /* PSP_STANDALONE ==0 */
70
71 // Watchdog
72 //--------------------------------------------------
73 TM_DisableWatchdog(); /* Disable Watchdog */
74 #if (CHIPSET == 12) || (CHIPSET == 15)
75 TM_SEC_DisableWatchdog();
76 #endif
77
78 freecalypso_disable_bootrom_pll();
79
80 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
81
82 /*
83 * Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules
84 */
85 // IRQ, Timer and bridge may SLEEP
86 // In first step, same configuration as SAMSON
87 //--------------------------------------------------
88 #if (CHIPSET == 12)
89 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_BRIDGE_DIS | CLKM_DPLL_DIS);
90 #elif (CHIPSET == 15)
91 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_CPORT_EN | CLKM_BRIDGE_DIS | 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/
92
93 #else
94 CLKM_CNTL_OR(CLKM_IRQ_DIS | CLKM_TIMER_DIS);
95
96 // Select VTCXO input frequency
97 //--------------------------------------------------
98 CLKM_UNUSED_VTCXO_26MHZ;
99
100 // Rita RF uses 26MHz VCXO
101 #if (RF_FAM == 12)
102 CLKM_USE_VTCXO_26MHZ;
103 #endif
104 // Renesas RF uses 26MHz on F-sample but 13MHz on TEB
105 #if (RF_FAM == 43) && (BOARD == 46)
106 CLKM_USE_VTCXO_26MHZ;
107 #endif
108 #endif
109
110 // Control HOM/SAM automatic switching
111 //--------------------------------------------------
112 *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG;
113
114 /*
115 * Disassembly of Init_Target() in init.obj in main.lib in the
116 * Leonardo reference version reveals that the code does the
117 * following at this point:
118 */
119 RHEA_INITRHEA(0,0,0xFF);
120 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
121 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
122 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
123 /* at this point the original code sets up the memory wait states */
124 /* we'll do it differently */
125 RHEA_INITAPI(0,1);
126 RHEA_INITARM(0,0);
127 DPLL_SET_PLL_ENABLE;
128
129 /*
130 * Disable and Clear all pending interrupts
131 */
132 #if (CHIPSET == 12) || (CHIPSET == 15)
133 F_INTH_DISABLE_ALL_IT; // MASK all it
134 F_INTH2_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH2 IRQ
135 F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ
136 F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ
137 F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source
138 #else
139 INTH_DISABLEALLIT;
140 INTH_RESETALLIT;
141 INTH_CLEAR; /* reset IRQ/FIQ source */
142 #endif
143
144 // INTH
145 //--------------------------------------------------
146 #if (CHIPSET == 12) || (CHIPSET == 15)
147 #if (GSM_IDLE_RAM != 0)
148 f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram); // setup configuration IT handlers
149 #else
150 f_inth_setup((T_INTH_CONFIG *)a_inth_config); // setup configuration IT handlers
151 #endif
152 #else
153 IQ_SetupInterrupts();
154 #endif
155
156 // DMA
157 //--------------------------------------------------
158 // channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same
159 #if 1 //(OP_L1_STANDALONE == 0)
160 DMA_ALLOCDMA(1,0,1,1); // Channel 1 used by DSP with RIF RX
161 #endif
162
163 /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
164
165 #else
166
167 // RHEA Bridge
168 //--------------------------------------------------
169 // ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F
170 RHEA_INITRHEA(0,0,0x7F);
171
172 #if (CHIPSET == 6)
173 // WS_H = 1 , WS_L = 15
174 RHEA_INITAPI(1,15); // should be 0x01E1 for 65 Mhz
175 #else
176 // WS_H = 0 , WS_L = 7
177 RHEA_INITAPI(0,7); // should be 0x0101 for 65 Mhz
178 #endif
179
180 // Write_en_0 = 0 , Write_en_1 = 0
181 RHEA_INITARM(0,0);
182
183 // INTH
184 //--------------------------------------------------
185 INTH_DISABLEALLIT; // MASK all it
186 INTH_CLEAR; // reset IRQ/FIQ source
187 IQ_SetupInterrupts();
188
189 // DMA
190 //--------------------------------------------------
191 // channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same
192 DMA_ALLOCDMA(1,0,1,1); // should be 0x25 (channel 1 = lead)
193
194 #if (CHIPSET == 6)
195 // Memory WS configuration for ULYSS/G1 (26 Mhz) board
196 //-----------------------------------------------------
197 MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0);
198 #endif
199
200 // CLKM
201 //--------------------------------------------------
202 CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */
203
204 #if (CHIPSET == 6)
205 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS | CLKM_VTCXO_26);
206 #else
207 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS);
208 #endif
209
210 #endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
211
212 // Freeze ULPD timer ....
213 //--------------------------------------------------
214 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_INIT_REG ) = 0;
215 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE;
216
217 // reset INC_SIXTEEN and INC_FRAC
218 //--------------------------------------------------
219 #if 0 //(OP_L1_STANDALONE == 1)
220 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE);
221 #else
222 ULDP_INCSIXTEEN_UPDATE(132); //32768.29038 =>132, 32500 => 133
223 // 26000 --> 166
224 ULDP_INCFRAC_UPDATE(15840); //32768.29038 =>15840, 32500 => 21845
225 // 26000 --> 43691
226 #endif /* OP_L1_STANDALONE */
227
228 // program ULPD WAKE-UP ....
229 //=================================================
230 #if (CHIPSET == 2)
231 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 2 frame
232 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 31 periods
233 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
234 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
235 #else
236 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames
237 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods
238 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
239 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
240 *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods
241 #endif
242
243 #if (CHIPSET == 15)
244 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SLEEPN) = SETUP_SLEEPZ; // 0
245 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SYSCLKEN) = SETUP_SYSCLKEN; // 255 clocks of 32 KHz for 7.8 ms DCXO delay for Locosto
246 *((volatile SYS_UWORD16 *)0xFFFEF192) = 0x1; //CLRZ
247 *((volatile SYS_UWORD16 *)0xFFFEF190) = 0x2; //SLPZ
248 *((volatile SYS_UWORD16 *)0xFFFEF18E)= 0x2; //SYSCLKEN
249 *((volatile SYS_UWORD16 *)0xFFFEF186) = 0x2; //CLK13_EN
250 *((volatile SYS_UWORD16 *)0xFFFEF18A) = 0x2; //DRP_DBB_SYSCLK
251 #endif
252
253 // Set Gauging versus HF (PLL)
254 //=================================================
255 ULDP_GAUGING_SET_HF; // Enable gauging versus HF
256 ULDP_GAUGING_HF_PLL; // Gauging versus PLL
257
258 // current supply for quartz oscillation
259 //=================================================
260 #if 0 //(OP_L1_STANDALONE == 1)
261 #if ((CHIPSET != 9) && (CHIPSET != 12) && (CHIPSET !=15)) // programming model changed for Ulysse C035, stay with default value
262 *(volatile SYS_UWORD16 *)QUARTZ_REG = 0x27;
263 #endif
264 #else
265 #if ((BOARD == 6) || (BOARD == 8) || (BOARD == 9) || (BOARD == 35) || (BOARD == 40) || (BOARD == 41))
266 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x27;
267 #elif (BOARD == 7)
268 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x24;
269 #endif
270 #endif /* OP_L1_STANDALONE */
271
272 // stop Gauging if any (debug purpose ...)
273 //--------------------------------------------------
274 if ( *((volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG) & ULDP_GAUGING_EN)
275 {
276 volatile int j;
277 ULDP_GAUGING_STOP; /* Stop the gauging */
278 /* wait for gauging it*/
279 // one 32khz period = 401 periods of 13Mhz
280 for (j=1; j<50; j++);
281 while (! (* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING);
282 }
283
284 #if 1 //(OP_L1_STANDALONE == 0)
285 AI_ClockEnable ();
286
287 #if (BOARD == 7)
288 // IOs configuration of the B-Sample in order to optimize the power consumption
289 AI_InitIOConfig();
290
291 // Set LPG instead of DSR_MODEM
292 *((volatile SYS_UWORD16 *) ASIC_CONF) |= 0x40;
293 // Reset the PERM_ON bit of LCR_REG
294 *((volatile SYS_UWORD16 *) MEM_LPG) &= ~(0x80);
295 #elif ((BOARD == 8) || (BOARD == 9))
296 // IOs configuration of the C-Sample in order to optimize the power consumption
297 AI_InitIOConfig();
298
299 // set the debug latch to 0x00.
300 *((volatile SYS_UWORD8 *) 0x2800000) = 0x00;
301 #elif ((BOARD == 35) || (BOARD == 46))
302 AI_InitIOConfig();
303 // CSMI INTERFACE
304 // Initialize CSMI clients for GSM control
305 // and Fax/Data services
306 CSMI_Init();
307 GC_Initialize(); // GSM control initialization
308 CU_Initialize(); // Trace initialization
309 CF_Initialize(); // Fax/Data pre-initialization
310 #elif ((BOARD == 40) || (BOARD == 41))
311 // IOs configuration of the D-Sample in order to optimize the power consumption
312 AI_InitIOConfig();
313
314 #ifdef BTEMOBILE
315 // Reset BT chip by toggling the Island's nRESET_OUT signal
316 *((volatile SYS_UWORD16 *) 0xFFFFFD04) |= 0x04;
317 *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4);
318 #endif
319
320 #if 0 // FreeCalypso
321 // set the debug latch to 0x0000.
322 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
323 #endif
324 #elif ((BOARD == 70) || (BOARD == 71))
325 AI_InitIOConfig();
326 /* Mark The System configuration According to I-Sample */
327 /* Adding GPIO Mux Setting Here */
328 pin_configuration_all(); // Init Tuned for Power Management
329 /* A22 is Enabled in int.s hence not Here */
330 /* FIXME: PULL_UP Enable and PULL UP Values Need to revisited */
331
332 /* Add code to find out the manufacture id of NOR flash*/
333
334 // Copy ffsdrv_device_id_read() function code to RAM. The only known
335 // way to determine the size of the code is to look either in the
336 // linker-generated map file or in the assember output file.
337 ffsdrv_copy_code_to_ram((UWORD16 *) detect_code,
338 (UWORD16 *) &ffsdrv_device_id_read,
339 sizeof(detect_code));
340
341 // Combine bit 0 of the thumb mode function pointer with the address
342 // of the code in RAM. Then call the detect function in RAM.
343 myfp = (pf_t) (((int) &ffsdrv_device_id_read & 1) | (int) detect_code);
344 (*myfp)(0x06000000, &manufact, device_id);
345
346 enable_ps_ram_burst();
347
348 if( 0x7e == device_id[0] )
349 {
350 enable_flash_burst();
351 flash_device_id = 0x7E;
352 }
353 else
354 {
355 enable_flash_burst_mirror();
356 flash_device_id = 0;
357 }
358
359 /* FreeCalypso: a bunch of dead code cut out */
360
361 #endif // BOARD
362
363 // Enable HW Timers 1 & 2
364 TM_EnableTimer (1);
365 TM_EnableTimer (2);
366
367 #if !CONFIG_INCLUDE_L1
368 Dtimer2_Init_cntl (1875, 1, 0, 1);
369 Dtimer2_Start (1);
370 #endif
371
372 #endif /* (OP_L1_STANDALONE == 0) */
373
374 }
375
376 /*
377 * Init_Unmask_IT() is the last function called from Application_Initialize();
378 * it also had to be reconstructed from disassembly.
379 */
380
381 void Init_Unmask_IT(void)
382 {
383 #if CONFIG_INCLUDE_L1
384 IQ_Unmask(IQ_FRAME);
385 #endif
386 IQ_Unmask(IQ_UART_IRDA_IT);
387 IQ_Unmask(IQ_UART_IT);
388 #if 0
389 IQ_Unmask(IQ_ARMIO);
390 #endif
391 #if L1_DYN_DSP_DWNLD
392 IQ_Unmask(IQ_API);
393 #endif
394 #if !CONFIG_INCLUDE_L1
395 IQ_Unmask(IQ_TIM2);
396 #endif
397 }