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comparison bsp/mem.h @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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1 /******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : mem.h
12
13 Description : Header file for the memory interface module
14
15 Project : Drivers
16
17 Author : proussel@ti.com Patrick Roussel.
18
19 Version number : 1.12
20
21 Date and time : 01/30/01 10:22:24
22
23 Previous delta : 12/19/00 14:24:11
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.mem.h
26
27 Sccs Id (SID) : '@(#) mem.h 1.12 01/30/01 10:22:24 '
28
29 *****************************************************************************/
30
31 #include "../include/config.h"
32
33 #define MEM_APIC_REG 0xffe00000 /* APIC register address */
34
35 #define MEM_STR1_ADDR 0xfffe0000 /* Strobe 1 : address */
36 #define MEM_STR1_CS 32 /* Strobe 1 : number of CS */
37 #define MEM_STR0_ADDR 0xffff0000 /* Strobe 0 : address */
38 #define MEM_STR0_CS 31 /* Strobe 0 : number of CS */
39
40
41 #define MEM_STR_LENGTH 2048 /* Strobe : length of a CS space */
42
43 #define MEM_UART_IRDA 0xFFFF5000
44 #define MEM_UART_MODEM 0xFFFF5800
45 #if (CHIPSET == 12)
46 #define MEM_UART_MODEM2 0xFFFFE000
47 #endif
48
49 #define MEM_RIF 0xFFFF7000
50
51 #define MEM_TCIF 0xFFFEA800
52 #define MEM_ICR 0xFFFEB000
53
54 /**** Generic masks ****/
55 #define BIT0 0x00000001L
56 #define BIT1 0x00000002L
57 #define BIT2 0x00000004L
58 #define BIT3 0x00000008L
59 #define BIT4 0x00000010L
60 #define BIT5 0x00000020L
61 #define BIT6 0x00000040L
62 #define BIT7 0x00000080L
63 #define BIT8 0x00000100L
64 #define BIT9 0x00000200L
65 #define BIT10 0x00000400L
66 #define BIT11 0x00000800L
67 #define BIT12 0x00001000L
68 #define BIT13 0x00002000L
69 #define BIT14 0x00004000L
70 #define BIT15 0x00008000L
71 #define BIT16 0x00010000L
72
73
74 #define MEM_DEV_ID0 0xFFFEF000
75 #define MEM_DEV_ID1 0xFFFEF002
76
77
78 // Register read and write macros.
79 #define READ_REGISTER_ULONG ( reg ) ( *(volatile unsigned long * const )( reg ) )
80 #define WRITE_REGISTER_ULONG ( reg, val ) ( *(volatile unsigned long * const )( reg ) ) = ( val )
81 #define READ_REGISTER_USHORT ( reg ) ( *(volatile unsigned short * const)( reg ) )
82 #define WRITE_REGISTER_USHORT( reg, val ) ( *(volatile unsigned short * const)( reg ) ) = ( val )
83 #define READ_REGISTER_UCHAR ( reg ) ( *(volatile unsigned char * const )( reg ) )
84 #define WRITE_REGISTER_UCHAR ( reg, val ) ( *(volatile unsigned char * const )( reg ) ) = ( val )
85
86
87 /**** External memory register ****/
88 #define MEM_TIMER_ADDR 0xfffff800 /* TIMER control register */
89 #if (CHIPSET == 12)
90 #define MEM_TIMER_SEC_ADDR 0xfffff880 /* TIMER Secure control register */
91 #endif
92
93 #define MEM_RHEA_CNTL 0xfffff900 /* memory RHEA control register */
94 #define MEM_API_CNTL 0xfffff902 /* memory API control register */
95 #define MEM_ARM_RHEA 0xfffff904 /* memory ARM/RHEA control register */
96 #define ENHANCED_RHEA_CNTL 0xfffff906 /* memory ARM/RHEA control register */
97
98 #define MEM_INTH_ADDR 0xfffffa00 /* INTH registers addr. */
99 #define MEM_REG_ADDR 0xfffffb00 /* memory i/f registers addr. */
100 #define MEM_REG_nCS0 (MEM_REG_ADDR + 0) /* nCS0 register address */
101 #define MEM_REG_nCS1 (MEM_REG_ADDR + 2) /* nCS1 register address */
102 #define MEM_REG_nCS2 (MEM_REG_ADDR + 4) /* nCS2 register address */
103 #define MEM_REG_nCS3 (MEM_REG_ADDR + 6) /* nCS3 register address */
104
105 #if ((CHIPSET == 3) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
106 #define MEM_REG_nCS4 (MEM_REG_ADDR + 8) /* nCS4 register address */
107 #define MEM_REG_nCS5 (MEM_REG_ADDR + 0xa) /* nCS5 register address */
108 #define MEM_REG_nCS6 (MEM_REG_ADDR + 0xc) /* nCS6 register address */
109 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
110 #define MEM_REG_nCS4 (MEM_REG_ADDR + 0xa) /* nCS4 register address */
111 #define MEM_REG_nCS6 (MEM_REG_ADDR + 0xc) /* nCS6 register address */
112 #define MEM_REG_nCS7 (MEM_REG_ADDR + 0x8) /* nCS7 register address */
113 #elif (CHIPSET == 12)
114 #define MEM_REG_nCS4 (MEM_REG_ADDR + 0x8) /* nCS4 register address */
115 #define MEM_REG_nCS5 (MEM_REG_ADDR + 0xa) /* nCS5 register address */
116 #define MEM_REG_DSPMS (MEM_REG_ADDR + 0x2e) /* DSPMS register address */
117 #else
118 #define MEM_REG_nCS4 (MEM_REG_ADDR + 8) /* nCS4 register address */
119 #define MEM_REG_nCS5 (MEM_REG_ADDR + 0xa) /* nCS5 register address */
120 #endif
121
122 #define MEM_CTRL_REG (MEM_REG_ADDR + 0xe) /* Control register address */
123
124 #if (CHIPSET == 12)
125 #define MEM_DMA_ADDR 0xffffe800 /* DMA controller reg. addr. */
126 #else
127 #define MEM_DMA_ADDR 0xfffffc00 /* DMA controller reg. addr. */
128 #endif
129
130 #define MEM_CLKM_ADDR 0xfffffd00 /* CLKM registers addr. */
131 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
132 #define MEM_DPLL_ADDR 0xffff9800 /* DPLL control register */
133 #endif
134
135 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
136 #define MEM_MPU_ADDR 0xFFFFFF00 /* Base address of MPU module */
137 #endif
138
139 #define RTC_XIO_START 0xfffe1800
140
141 #define ARM_CONF_REG 0xFFFEF006
142
143 #define MEM_SIM 0xFFFE0000
144 #define MEM_TSP 0xFFFE0800
145 #define MEM_TPU_REG 0xFFFE1000
146 #define MEM_TPU_RAM 0xFFFE1400
147 #define MEM_RTC 0xFFFE1800
148 #define MEM_ULPD 0xFFFE2000
149 #define MEM_SPI 0xFFFE3000
150 #define MEM_TIMER1 0xFFFE3800
151 #define MEM_UWIRE 0xFFFE4000
152 #define MEM_ARMIO 0xFFFE4800
153 #define MEM_TIMER2 0xFFFE6800
154 #define MEM_LPG 0xFFFE7800
155 #define MEM_PWL 0xFFFE8000
156 #define MEM_PWT 0xFFFE8800
157 #if (CHIPSET == 12)
158 #define MEM_KEYBOARD 0xFFFEB800
159 #endif
160 #define MEM_JTAGID_PART 0xFFFEF000 /* JTAG ID code register */
161 #define MEM_JTAGID_VER 0xFFFEF002 /* JTAG ID code register */
162 #if (CHIPSET != 12)
163 #define MEM_IO_SEL 0xFFFEF00A
164 #endif
165
166
167 /**** External memory register ****/
168
169 #define MEM_REG_WS 0x001f /* number of wait states */
170 #define MEM_REG_DVS 0x0060 /* device size */
171 #define MEM_REG_WE 0x0080 /* write enable */
172 #define MEM_REG_BIG 0x0100 /* big endian */
173
174 #define MEM_DVS_8 0 /* device size = 8 bits */
175 #define MEM_DVS_16 1 /* device size = 16 bits */
176 #define MEM_DVS_32 2 /* device size = 32 bits */
177
178
179 #define MEM_WRITE_DIS 0 /* write disable */
180 #define MEM_WRITE_EN 1 /* write enable */
181
182 #define MEM_LITTLE 0 /* little endian */
183 #define MEM_BIG 1 /* big endian */
184
185 #define MEM_NO_ADAPT 0 /* no memory adaptation */
186 #define MEM_ADAPT 1 /* memory adaptation */
187
188 /**** Memory control register ****/
189
190 #define MEM_CNTL_0_BIG 0x01 /* Big Endian for strobe 0 */
191 #define MEM_CNTL_0_ADAP 0x02 /* size adaptation for strobe 0 */
192 #define MEM_CNTL_1_BIG 0x04 /* Big Endian for strobe 1 */
193 #define MEM_CNTL_1_ADAP 0x08 /* size adaptation for strobe 1 */
194 #define MEM_CNTL_API_BIG 0x10 /* Big Endian for API */
195 #define MEM_CNTL_API_ADAP 0x20 /* size adaptation for API */
196 #define MEM_CNTL_DBG 0x40 /* debug */
197
198
199 #define ARM_CLK_SRC 0x04
200 #define ARM_MCLK_DIV 0x30
201 #define TPU_CLK_ENABLE 0x400
202
203 #if (CHIPSET == 12)
204 /**** DSP Memory shared register ****/
205
206 #define MEM_DSPMS_0_MB_TO_DSP ( 0 )
207 #define MEM_DSPMS_0_5_MB_TO_DSP ( 1 )
208
209 #endif
210
211 #if (CHIPSET == 12)
212 #define ASIC_CONF 0xfffef01c
213 #else
214 #define ASIC_CONF 0xfffef008
215 #endif
216
217 // duplicate definition with MEM_ARMIO !!
218 //#define ARMIO_ADDR 0xfffe4800
219
220 /**** Config registers ****/
221 #if (CHIPSET != 12)
222 #define QUARTZ_REG 0xfffef00c
223 #endif
224
225 #define MEM_INIT_CS0(d_ws, d_dvs, d_we, d_dc) ( \
226 *((volatile UWORD16 *) MEM_REG_nCS0 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
227
228 #define MEM_INIT_CS1(d_ws, d_dvs, d_we, d_dc) ( \
229 *((volatile UWORD16 *) MEM_REG_nCS1 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
230
231 #define MEM_INIT_CS2(d_ws, d_dvs, d_we, d_dc) ( \
232 *((volatile UWORD16 *) MEM_REG_nCS2 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
233
234 #define MEM_INIT_CS3(d_ws, d_dvs, d_we, d_dc) ( \
235 *((volatile UWORD16 *) MEM_REG_nCS3 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
236
237 #define MEM_INIT_CS4(d_ws, d_dvs, d_we, d_dc) ( \
238 *((volatile UWORD16 *) MEM_REG_nCS4 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
239
240 #if (CHIPSET == 12)
241 #define MEM_INIT_CS5(d_ws, d_dvs, d_we, d_dc) ( \
242 *((volatile UWORD16 *) MEM_REG_nCS5 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
243 #endif
244
245 #if ((CHIPSET == 3) || (CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
246 #define MEM_INIT_CS6(d_ws, d_dvs, d_we, d_dc) ( \
247 *((volatile UWORD16 *) MEM_REG_nCS6 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
248 #endif
249
250 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
251 #define MEM_INIT_CS7(d_ws, d_dvs, d_we, d_dc) ( \
252 *((volatile UWORD16 *) MEM_REG_nCS7 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
253 #endif
254
255 #if (CHIPSET == 12)
256 #define MEM_INIT_DSPMS(d_share) ( \
257 *((volatile UWORD16 *) MEM_REG_DSPMS ) = (d_share & 0x0003))
258 #endif
259
260 /********************** Prototypes ************************/
261
262 short MEM_InitCtrl(unsigned short Big0, unsigned short Adap0, unsigned short Big1, unsigned short Adap1,
263 unsigned short BigAPI, unsigned short AdapAPI, unsigned short debug);
264 short MEM_SetCtrlAPI(unsigned short Big, unsigned short Adap);