FreeCalypso > hg > freecalypso-citrine

comparison finlink/ld-script.src @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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1 dnl This ld script source is fed through m4 in order to fill in
2 dnl those settings which depend on the configuration.
3 dnl Memory region sizes are set in ../include/config.m4, generated
4 dnl by the configuration mechanism based on the selected target,
5 dnl and the Makefile prepends flash.m4 or xram.m4 to select the
6 dnl type of image we are linking: either the regular flashable image,
7 dnl or a RAM-only test image (to be loaded via fc-xram) that does not
8 dnl touch the flash and pretends as if the flash doesn't even exist.
9
10 /*
11 * FreeCalypso ld script for the Buildmem build
12 */
13
14 ENTRY(ifelse(Buildmem,XRAM,_FlashorXram_entry,_Flash_boot_entry))
15
16 include(`../include/config.m4')dnl
17 MEMORY {
18 ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1,
19 ` FLASH_OVERLAY : ORIGIN = 0, LENGTH = 0x2000')
20 ifelse(Buildmem,FLASH,
21 ` FLASH : ORIGIN = FLASHIMAGE_BASE_ADDR,
22 LENGTH = CONFIG_FWFLASH_SIZE - FLASHIMAGE_BASE_ADDR')
23 IRAM : ORIGIN = 0x00800000, LENGTH = CONFIG_IRAM_SIZE
24 XRAM : ORIGIN = 0x01000000, LENGTH = CONFIG_XRAM_SIZE
25 }
26 ifelse(FFS_IN_RAM,1,`
27 RAMFFS_BLKSIZE_BYTES = 1 << RAMFFS_BLKSIZE_LOG2;
28 RAMFFS_TOTAL_SIZE = RAMFFS_BLKSIZE_BYTES * RAMFFS_NBLOCKS;
29 ')dnl
30
31 SECTIONS {
32 dnl The following sections exist only in the flashImage build,
33 dnl and only on targets that use the Calypso boot ROM.
34 ifelse(Buildmem-FLASH_BOOT_VIA_BOOTROM,FLASH-1,
35 ` /* Part of flash overlaid by the boot ROM */
36 bootrom.overlay 0 : {
37 *(bootrom.overlay)
38 } > FLASH_OVERLAY
39
40 /* code that enables the boot ROM and jumps to it */
41 bootrom.switch : {
42 *(bootrom.switch)
43 } > IRAM AT> FLASH_OVERLAY
44 __romswitch_ram_addr = ADDR(bootrom.switch);
45 __romswitch_flash_addr = LOADADDR(bootrom.switch);
46 __romswitch_size = SIZEOF(bootrom.switch);
47 ')dnl
48
49 dnl all flashImage builds
50 ifelse(Buildmem,FLASH,
51 ` /* Flash boot entry point */
52 flashboot.text FLASHIMAGE_BASE_ADDR : {
53 *(flashboot.text)
54 } > FLASH
55 ')dnl
56
57 /* XIP code, going into flash or XRAM emulating flash */
58 xip.text : {
59 *(xip.text*)
60 xipcode.o(.text*)
61 *comlib.a:(.text*)
62 *libdsp.a:(.text*)
63 *libdti.a:(.text*)
64 *libgdi.a:(.text*)
65 *libplus.xip.a:(.text*)
66 *libgpf.xip.a:(.text*)
67 *libccd.a:(.text*)
68 *librv.a:(.text*)
69 *libsprintf.a:(.text*)
70 /* let's put the ARM->Thumb veneers in the XIP section */
71 *(.glue_7)
72 } > Buildmem
73
74 /* copy-to-IRAM code */
75 iram.text 0x80001C : {
76 /* the 7 exception and interrupt vectors @ 0x80001C */
77 *(iram.vectors)
78 *(iram.text*)
79 iramcode.o(.text*)
80 *libplus.iram.a:(.text*)
81 *libgpf.iram.a:(.text*)
82 *libiram.a:(.text*)
83 *libc.a:(.text*)
84 *libgcc.a:(.text*)
85 } > IRAM Put_in_flash
86 ifelse(Buildmem,FLASH,
87 ` __iramtext_ram_addr = ADDR(iram.text);
88 __iramtext_flash_addr = LOADADDR(iram.text);
89 __iramtext_size = SIZEOF(iram.text);
90 ')dnl
91
92 /* all .rodata will stay in flash */
93 .rodata : {
94 *(.rodata*)
95 } > Buildmem
96
97 /*
98 * All .data will go into XRAM.
99 * For the flash build we'll have a step that copies
100 * the .data section from flash to XRAM; for the RAM-only
101 * build it goes directly into XRAM and stays there.
102 */
103 .data : {
104 *(.data*)
105 } > XRAM Put_in_flash
106 ifelse(Buildmem,FLASH,
107 ` __initdata_ram_addr = ADDR(.data);
108 __initdata_flash_addr = LOADADDR(.data);
109 __initdata_size = SIZEOF(.data);
110 ')dnl
111
112 /* we have two kinds of BSS: internal and external */
113 int.bss (NOLOAD) : {
114 *(int.bss*)
115 *(.l1s_global)
116 iramcode.o(.bss* COMMON)
117 *libplus.iram.a:(.bss* COMMON)
118 *libgpf.iram.a:(.bss* COMMON)
119 *libiram.a:(.bss* COMMON)
120 *libc.a:(.bss* COMMON)
121 *libgcc.a:(.bss* COMMON)
122 . = ALIGN(4);
123 } > IRAM
124 __intbss_start = ADDR(int.bss);
125 __intbss_size = SIZEOF(int.bss);
126
127 ext.bss (NOLOAD) : {
128 *(ext.bss*)
129 xipcode.o(.bss* COMMON)
130 *comlib.a:(.bss* COMMON)
131 *libdsp.a:(.bss* COMMON)
132 *libdti.a:(.bss* COMMON)
133 *libgdi.a:(.bss* COMMON)
134 *libplus.xip.a:(.bss* COMMON)
135 *libgpf.xip.a:(.bss* COMMON)
136 *libccd.a:(.bss* COMMON)
137 *librv.a:(.bss* COMMON)
138 *libsprintf.a:(.bss* COMMON)
139 . = ALIGN(4);
140 } > XRAM
141 __extbss_start = ADDR(ext.bss);
142 __extbss_size = SIZEOF(ext.bss);
143
144 /* finally, we have "raw RAM": like BSS, but we don't zero it out */
145 int.ram (NOLOAD) : {
146 *(int.ram*)
147 *(system_stack)
148 *(irq_stack)
149 *(fiq_stack)
150 *(timer_hisr_stack)
151 . = ALIGN(4);
152 _iram_end = .;
153 } > IRAM
154
155 ext.ram (NOLOAD) : {
156 *(ext.ram*)
157 *(except_stack)
158 . = ALIGN(4);
159 ifelse(FFS_IN_RAM,1,
160 ` _RAMFFS_area = .;
161 . += RAMFFS_TOTAL_SIZE;
162 ')dnl
163 _xram_end = .;
164 } > XRAM
165 }