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comparison g23m-aci/uart/uart_kers.c @ 0:75a11d740a02

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initial import of gsm-fw from freecalypso-sw rev 1033:5ab737ac3ad7
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 09 Jun 2016 00:02:41 +0000
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-1:000000000000 0:75a11d740a02
1 /*
2 +-----------------------------------------------------------------------------
3 | Project :
4 | Modul :
5 +-----------------------------------------------------------------------------
6 | Copyright 2002 Texas Instruments Berlin, AG
7 | All rights reserved.
8 |
9 | This file is confidential and a trade secret of Texas
10 | Instruments Berlin, AG
11 | The receipt of or possession of this file does not convey
12 | any rights to reproduce or disclose its contents or to
13 | manufacture, use, or sell anything it may describe, in
14 | whole, or in part, without the specific written consent of
15 | Texas Instruments Berlin, AG.
16 +-----------------------------------------------------------------------------
17 | Purpose : This modul is part of the entity UART and implements all
18 | functions to handles the incoming process internal signals as
19 | described in the SDL-documentation (KER-statemachine)
20 +-----------------------------------------------------------------------------
21 */
22
23 #ifndef UART_KERS_C
24 #define UART_KERS_C
25 #endif /* !UART_KERS_C */
26
27 #include "config.h"
28 #include "fixedconf.h"
29 #include "condat-features.h"
30
31 #define ENTITY_UART
32
33 /*
34 * Turn off spurious LINT warnings
35 */
36 /*lint -e415 access of out-of-bounds pointer */
37
38 /*==== INCLUDES =============================================================*/
39
40 #ifdef WIN32
41 #include "nucleus.h"
42 #endif /* WIN32 */
43 #include "typedefs.h" /* to get Condat data types */
44 #include "vsi.h" /* to get a lot of macros */
45 #include "macdef.h" /* to get a lot of macros */
46 #include "custom.h"
47 #include "gsm.h" /* to get a lot of macros */
48 #include "cnf_uart.h" /* to get cnf-definitions */
49 #include "mon_uart.h" /* to get mon-definitions */
50 #include "prim.h" /* to get the definitions of used SAP and directions */
51 #include "dti.h" /* to get dti lib */
52 #include "pei.h" /* to get PEI interface */
53 #ifdef FF_MULTI_PORT
54 #include "gsi.h" /* to get definitions of serial driver */
55 #else /* FF_MULTI_PORT */
56 #ifdef _TARGET_
57 #include "../../serial/serialswitch.h"
58 #include "../../serial/traceswitch.h"
59 #else /* _TARGET_ */
60 #include "serial_dat.h" /* to get definitions of serial driver */
61 #endif /* _TARGET_ */
62 #endif /* FF_MULTI_PORT */
63 #include "uart.h" /* to get the global entity definitions */
64
65 #ifdef FF_MULTI_PORT
66 #include "uart_ptxs.h" /* to get signal definitions for service TX */
67 #include "uart_prxs.h" /* to get rx signals */
68 #else /* FF_MULTI_PORT */
69 #include "uart_txs.h" /* to get signal definitions of service TX */
70 #include "uart_rxs.h" /* to get signal definitions of service RX */
71 #endif /* FF_MULTI_PORT */
72 #include "uart_dtxs.h" /* to get signal definitions of service DTX */
73 #include "uart_drxs.h" /* to get signal definitions of service DRX */
74 #include "uart_kerf.h" /* to get function definitions of service KER */
75 #include "uart_rts.h" /* to get signal definitions of service RT */
76
77 #ifndef _TARGET_
78 #include <stdio.h> /* to get sprintf */
79 #endif /* !_TARGET_ */
80 #include <string.h> /* JK, delete warnings: to get memcpy */
81
82 /*==== CONST ================================================================*/
83
84 /*==== LOCAL VARS ===========================================================*/
85
86 /*==== PRIVATE FUNCTIONS ====================================================*/
87
88 /*==== PUBLIC FUNCTIONS =====================================================*/
89
90
91
92 /*
93 +------------------------------------------------------------------------------
94 | Function : sig_drx_ker_line_states_ind
95 +------------------------------------------------------------------------------
96 | Description : Handles the internal signal SIG_DRX_KER_LINE_STATES_IND
97 |
98 | Parameters : dlc_instance - dlc instance wich belongs to calling DRX
99 | st_flow - flow control state (X bit)
100 | st_line_sa - line state SA
101 | st_line_sa - line state SB
102 | st_break_len - break state
103 |
104 +------------------------------------------------------------------------------
105 */
106 GLOBAL void sig_drx_ker_line_states_ind(UBYTE dlc_instance,
107 UBYTE st_flow,
108 UBYTE st_line_sa,
109 UBYTE st_line_sb,
110 USHORT st_break_len)
111 {
112 T_DLC* dlc;
113 ULONG old_lines;
114 ULONG new_lines;
115
116 TRACE_ISIG( "sig_drx_ker_line_states_ind" );
117
118 /*
119 * set DLC
120 */
121 dlc = &uart_data->dlc_table[dlc_instance];
122
123 switch( GET_STATE( UART_SERVICE_KER ) )
124 {
125 case KER_READY:
126 /*
127 * check for changed line states
128 */
129 old_lines = dlc->lines & (UART_SA_TX_MASK |
130 UART_SB_TX_MASK |
131 UART_X_TX_MASK |
132 UART_BRK_TX_MASK);
133 new_lines = ((ULONG)st_line_sa << UART_SA_TX_POS) |
134 ((ULONG)st_line_sb << UART_SB_TX_POS) |
135 ((ULONG)st_flow << UART_X_TX_POS);
136 if(st_break_len NEQ DTI_BREAK_OFF)
137 {
138 TRACE_EVENT("send Break");
139 new_lines|= UART_BRK_TX_MASK;
140 }
141
142 if(old_lines NEQ new_lines)
143 {
144 /*
145 * trace changes
146 */
147 if(new_lines & UART_X_TX_MASK)
148 {
149 if(!(old_lines & UART_X_TX_MASK))
150 {
151 TRACE_EVENT("TX Flow Control: stop");
152 }
153 }
154 else if(old_lines & UART_X_TX_MASK)
155 {
156 TRACE_EVENT("TX Flow Control: start");
157 }
158
159 if(new_lines & UART_SA_TX_MASK)
160 {
161 if(!(old_lines & UART_SA_TX_MASK))
162 {
163 TRACE_EVENT("DSR: off");
164 }
165 }
166 else if(old_lines & UART_SA_TX_MASK)
167 {
168 TRACE_EVENT("DSR: on");
169 }
170
171 if(new_lines & UART_SB_TX_MASK)
172 {
173 if(!(old_lines & UART_SB_TX_MASK))
174 {
175 TRACE_EVENT("DCD: off");
176 }
177 }
178 else if(old_lines & UART_SB_TX_MASK)
179 {
180 TRACE_EVENT("DCD: on");
181 }
182
183 /*
184 * send new line states
185 * but flush UART before
186 */
187 dlc->lines&= ~(UART_SA_TX_MASK |
188 UART_SB_TX_MASK |
189 UART_X_TX_MASK |
190 UART_BRK_TX_MASK |
191 UART_BRKLEN_TX_MASK);
192
193 if(st_break_len NEQ DTI_BREAK_OFF)
194 new_lines|= ((ULONG)st_break_len << UART_BRKLEN_TX_POS);
195
196 dlc->lines|= new_lines;
197
198 dlc->received_prim|= UART_DTI_DATA_REQ_MASK;
199
200 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
201 {
202 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
203 sig_ker_tx_flush_req();
204 }
205 }
206 break;
207
208 case KER_MUX:
209 /*
210 * check for changed line states
211 */
212 old_lines = dlc->lines & (UART_CTS_MASK |
213 UART_DSR_MASK |
214 UART_DCD_MASK |
215 UART_BRK_TX_MASK);
216 new_lines = ((ULONG)st_flow << UART_CTS_POS) |
217 ((ULONG)st_line_sa << UART_DSR_POS) |
218 ((ULONG)st_line_sb << UART_DCD_POS);
219
220 if(st_break_len NEQ DTI_BREAK_OFF)
221 {
222 TRACE_EVENT_P1("send Break - DLCI=%d", dlc->dlci);
223 new_lines|= UART_BRK_TX_MASK;
224 }
225
226 if(old_lines NEQ new_lines)
227 {
228 /*
229 * trace changes
230 */
231 if(new_lines & UART_CTS_MASK)
232 {
233 if(!(old_lines & UART_CTS_MASK))
234 {
235 TRACE_EVENT_P1("TX Flow Control: stop - DLCI=%d", dlc->dlci);
236 }
237 }
238 else if(old_lines & UART_CTS_MASK)
239 {
240 TRACE_EVENT_P1("TX Flow Control: start - DLCI=%d", dlc->dlci);
241 }
242
243 if(new_lines & UART_DSR_MASK)
244 {
245 if(!(old_lines & UART_DSR_MASK))
246 {
247 TRACE_EVENT_P1("DSR: off - DLCI=%d", dlc->dlci);
248 }
249 }
250 else if(old_lines & UART_DSR_MASK)
251 {
252 TRACE_EVENT_P1("DSR: on - DLCI=%d", dlc->dlci);
253 }
254
255 if(new_lines & UART_DCD_MASK)
256 {
257 if(!(old_lines & UART_DCD_MASK))
258 {
259 TRACE_EVENT_P1("DCD: off - DLCI=%d", dlc->dlci);
260 }
261 }
262 else if(old_lines & UART_DCD_MASK)
263 {
264 TRACE_EVENT_P1("DCD: on - DLCI=%d", dlc->dlci);
265 }
266 /*
267 * build and send MSC command
268 */
269 dlc->lines&= ~(UART_CTS_MASK |
270 UART_DSR_MASK |
271 UART_DCD_MASK |
272 UART_BRK_TX_MASK |
273 UART_BRKLEN_TX_MASK);
274
275 if(st_break_len NEQ DTI_BREAK_OFF)
276 new_lines|= ((ULONG)st_break_len << UART_BRKLEN_TX_POS);
277
278 dlc->lines|= new_lines;
279 ker_mux_send_line_states(dlc_instance);
280 }
281 break;
282
283 default:
284 TRACE_ERROR( "SIG_DRX_KER_LINE_STATES_IND unexpected" );
285 break;
286 }
287 } /* sig_drx_ker_line_states_ind() */
288
289
290
291 /*
292 +------------------------------------------------------------------------------
293 | Function : sig_dtx_ker_enable_ind
294 +------------------------------------------------------------------------------
295 | Description : Handles the internal signal SIG_DTX_KER_ENABLE_IND
296 |
297 | Parameters : dlc_instance - dlc instance wich belongs to calling DTX
298 |
299 +------------------------------------------------------------------------------
300 */
301 GLOBAL void sig_dtx_ker_enable_ind (UBYTE dlc_instance)
302 {
303 TRACE_ISIG( "sig_dtx_ker_enable_ind" );
304
305 switch( GET_STATE( UART_SERVICE_KER ) )
306 {
307 case KER_MUX:
308 /*
309 * build and send MSC command
310 * enable flow control in line states
311 */
312 uart_data->dlc_table[dlc_instance].lines&= ~UART_FC_TX_MASK;
313 /*
314 * send new line states
315 */
316 ker_mux_send_line_states(dlc_instance);
317 break;
318
319 case KER_READY:
320 break;
321
322 default:
323 TRACE_ERROR( "SIG_DTX_KER_ENABLE_IND unexpected" );
324 break;
325 }
326 } /* sig_dtx_ker_enable_ind() */
327
328
329
330 /*
331 +------------------------------------------------------------------------------
332 | Function : sig_dtx_ker_disable_ind
333 +------------------------------------------------------------------------------
334 | Description : Handles the internal signal SIG_DTX_KER_DISABLE_IND
335 |
336 | Parameters : dlc_instance - dlc instance wich belongs to calling DTX
337 |
338 +------------------------------------------------------------------------------
339 */
340 GLOBAL void sig_dtx_ker_disable_ind (UBYTE dlc_instance)
341 {
342 TRACE_ISIG( "sig_dtx_ker_disable_ind" );
343
344 switch( GET_STATE( UART_SERVICE_KER ) )
345 {
346 case KER_MUX:
347 /*
348 * build and send MSC command
349 * disable flow control in line states
350 */
351 uart_data->dlc_table[dlc_instance].lines|= UART_FC_TX_MASK;
352 /*
353 * send new line states
354 */
355 ker_mux_send_line_states(dlc_instance);
356 break;
357
358 case KER_READY:
359 break;
360
361 default:
362 TRACE_ERROR( "SIG_DTX_KER_DISABLE_IND unexpected" );
363 break;
364 }
365 } /* sig_dtx_ker_disable_ind() */
366
367
368
369 /*
370 +------------------------------------------------------------------------------
371 | Function : sig_dtx_ker_escape_detected_ind
372 +------------------------------------------------------------------------------
373 | Description : Handles the internal signal SIG_DTX_KER_ESCAPE_DETECTED_IND
374 |
375 | Parameters : dlc_instance - dlc instance wich belongs to calling DTX
376 |
377 +------------------------------------------------------------------------------
378 */
379 GLOBAL void sig_dtx_ker_escape_detected_ind (U8 dlc_instance)
380 {
381 T_DLC *dlc;
382
383 TRACE_FUNCTION( "sig_dtx_ker_escape_detected_ind" );
384
385 /*
386 * set DLC
387 */
388 dlc = &uart_data->dlc_table[dlc_instance];
389 {
390 PALLOC (uart_detected_ind, UART_DETECTED_IND);
391 uart_detected_ind->device = uart_data->device;
392 uart_detected_ind->dlci = dlc->dlci;
393 uart_detected_ind->cause = UART_DETECT_ESC;
394 PSEND (hCommMMI, uart_detected_ind);
395 }
396 } /* sig_dtx_ker_escape_detected_ind() */
397
398
399
400 /*
401 +------------------------------------------------------------------------------
402 | Function : sig_any_ker_flushed_ind
403 +------------------------------------------------------------------------------
404 | Description : Handles the internal signal SIG_ANY_KER_FLUSHED_IND
405 |
406 | Parameters : dlc_instance - dlc instance wich belongs to this signal
407 |
408 +------------------------------------------------------------------------------
409 */
410 GLOBAL void sig_any_ker_flushed_ind (UBYTE dlc_instance)
411 {
412 T_DLC* dlc;
413 UBYTE i;
414
415 TRACE_ISIG( "sig_any_ker_flushed_ind" );
416
417 /*
418 * reset flush indicator
419 */
420 dlc = &uart_data->dlc_table[dlc_instance];
421 dlc->flushed = TRUE;
422 /*
423 * if the primitive which has triggered the flush belongs to the whole port
424 * we will check each DLC for flush, if it only belongs to this DLC we start
425 * TX flushing immediately
426 */
427 if(uart_data->ker.received_prim)
428 {
429 /*
430 * check each DLC
431 */
432 for(i = 0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
433 {
434 dlc = &uart_data->dlc_table[i];
435 if(dlc->flushed NEQ TRUE)
436 return;
437 }
438 }
439 /*
440 * start TX flushing
441 */
442 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
443 sig_ker_tx_flush_req();
444 } /* sig_any_ker_flushed_ind() */
445
446
447
448 /*
449 +------------------------------------------------------------------------------
450 | Function : sig_tx_ker_flushed_ind
451 +------------------------------------------------------------------------------
452 | Description : Handles the internal signal SIG_TX_KER_FLUSHED_IND
453 |
454 | Parameters : no parameters
455 |
456 +------------------------------------------------------------------------------
457 */
458 GLOBAL void sig_tx_ker_flushed_ind ()
459 {
460 T_DLC* dlc;
461 UBYTE i;
462 #ifndef _SIMULATION_
463 USHORT error_code;
464 #endif
465 TRACE_ISIG( "sig_tx_ker_flushed_ind" );
466
467 if(uart_data->ker.flush_state EQ UART_KER_TX_FLUSH)
468 {
469 /*
470 * primitives of the port
471 */
472 /*
473 * UART_PARAMETERS_REQ
474 */
475 if(uart_data->ker.received_prim & UART_PARAMETERS_REQ_MASK)
476 {
477 /*
478 * disable UART while set new communication parameters
479 */
480 #ifdef _SIMULATION_
481 {
482 /*
483 * send DTI_GETDATA_REQ
484 */
485 PALLOC (dti_getdata_req, DTI2_GETDATA_REQ);
486 dti_getdata_req->link_id = LINK_DISABLE_PORT_1; /* for disable */
487 PSEND (hCommMMI, dti_getdata_req);
488 }
489 #else /* _SIMULATION_ */
490 #ifndef FF_MULTI_PORT
491 if((error_code = UF_Enable (uart_data->device, FALSE)) NEQ UF_OK)
492 {
493 TRACE_ERROR_P2("UF Driver: Can't disable UART, [%d], uart_kerp.c(%d)",
494 error_code,__LINE__);
495 }
496 #endif /* !FF_MULTI_PORT */
497 #endif /* _SIMULATION */
498 /*
499 * set new parameters
500 */
501 ker_setupUart();
502 #ifdef _SIMULATION_
503 {
504 /*
505 * send DTI_GETDATA_REQ
506 */
507 PALLOC (dti_getdata_req, DTI2_GETDATA_REQ);
508 dti_getdata_req->link_id = LINK_ENABLE_PORT_1; /* for enable */
509 PSEND (hCommMMI, dti_getdata_req);
510 }
511 #else /* _SIMULATION_ */
512 #ifndef FF_MULTI_PORT
513 if((error_code = UF_Enable (uart_data->device, TRUE)) NEQ UF_OK)
514 {
515 TRACE_ERROR_P2("UF Driver: Can't enable UART, [%d], uart_kerp.c(%d)",
516 error_code,__LINE__);
517 }
518 #endif /* !FF_MULTI_PORT */
519 #endif /* _SIMULATION */
520 /*
521 * restart suspended read and write procedures
522 */
523 sig_ker_tx_restart_write_req();
524 sig_ker_rx_restart_read_req();
525 /*
526 * send confirm primitive
527 */
528 {
529 PALLOC (uart_parameters_cnf, UART_PARAMETERS_CNF);
530 uart_parameters_cnf->device = uart_data->device;
531 PSEND (hCommMMI, uart_parameters_cnf);
532 }
533 }
534
535 /*
536 * UART_DISABLE_REQ
537 */
538 if(uart_data->ker.received_prim & UART_DISABLE_REQ_MASK)
539 {
540 switch( GET_STATE( UART_SERVICE_KER ) )
541 {
542 case KER_MUX:
543 case KER_MUX_ESTABLISH:
544 case KER_MUX_DLC_CLOSING:
545 case KER_MUX_CLOSING:
546 case KER_MUX_CLOSED:
547 /*
548 * stop timers and
549 * remove all DLC instances
550 */
551 ker_mux_close_down();
552 break;
553
554 case KER_READY:
555 /*
556 * close dlc channel
557 */
558 ker_mux_dlc_release(UART_CONTROL_INSTANCE);
559 break;
560
561 case KER_DEAD:
562 break;
563
564 default:
565 TRACE_ERROR( "SIG_TX_KER_FLUSHED_IND unexpected" );
566 break;
567 }
568
569 SET_STATE( UART_SERVICE_KER, KER_DEAD );
570
571 /*
572 * disable UART
573 */
574 #ifdef _SIMULATION_
575 {
576 /*
577 * send DTI_GETDATA_REQ
578 */
579 PALLOC (dti_getdata_req, DTI2_GETDATA_REQ);
580 dti_getdata_req->link_id = LINK_DISABLE_PORT_1; /* for disable */
581 PSEND (hCommMMI, dti_getdata_req);
582 }
583 #else /* _SIMULATION_ */
584 #ifndef FF_MULTI_PORT
585 if((error_code = UF_Enable (uart_data->device, FALSE)) NEQ UF_OK)
586 {
587 TRACE_ERROR_P2("UF Driver: Can't disable UART, [%d], uart_kerp.c(%d)",
588 error_code,__LINE__);
589 }
590 #endif /* !FF_MULTI_PORT */
591 #endif /* _SIMULATION */
592 sig_ker_rx_dead_mode_req();
593 sig_ker_tx_dead_mode_req();
594 /*
595 * send confirm primitive
596 */
597 {
598 PALLOC (uart_disable_cnf, UART_DISABLE_CNF);
599 uart_disable_cnf->device = uart_data->device;
600 PSEND (hCommMMI, uart_disable_cnf);
601 }
602 }
603
604 /*
605 * UART_MUX_START_REQ
606 */
607 if(uart_data->ker.received_prim & UART_MUX_START_REQ_MASK)
608 {
609 switch( GET_STATE( UART_SERVICE_KER ) )
610 {
611 case KER_READY:
612 /*
613 * close dlc channel
614 */
615 ker_mux_dlc_release(UART_CONTROL_INSTANCE);
616 break;
617
618 default:
619 TRACE_ERROR( "SIG_TX_KER_FLUSHED_IND unexpected" );
620 break;
621 }
622
623 SET_STATE( UART_SERVICE_KER, KER_MUX_ESTABLISH );
624
625 /*
626 * set RX and TX service in mux mode
627 */
628 sig_ker_rx_mux_mode_req();
629 sig_ker_tx_mux_mode_req();
630 /*
631 * start reception
632 */
633 MALLOC(uart_data->ker.rx_data_desc, (USHORT)(sizeof(T_desc2) -
634 1 +
635 uart_data->n1 +
636 2));
637 uart_data->ker.rx_data_desc->next = (ULONG)NULL;
638 uart_data->ker.rx_data_desc->len = 0;
639 sig_ker_rx_ready_to_receive_req(uart_data->ker.rx_data_desc,
640 0,
641 (USHORT)(uart_data->n1 + 2));
642 /*
643 * start timer
644 */
645 sig_ker_rt_start_t3_req();
646
647 /*
648 * send confirm primitive
649 */
650 {
651 PALLOC (uart_mux_start_cnf, UART_MUX_START_CNF);
652 uart_mux_start_cnf->device = uart_data->device;
653 PSEND (hCommMMI, uart_mux_start_cnf);
654 }
655 }
656
657 /*
658 * UART_MUX_CLOSE_REQ
659 */
660 if(uart_data->ker.received_prim & UART_MUX_CLOSE_REQ_MASK)
661 {
662 switch( GET_STATE( UART_SERVICE_KER ) )
663 {
664 case KER_MUX_CLOSED:
665 if(uart_data->ker.receiving_state NEQ UART_KER_RECEIVING)
666 {
667 PALLOC(uart_mux_close_ind, UART_MUX_CLOSE_IND);
668 SET_STATE( UART_SERVICE_KER, KER_READY );
669 /*
670 * stop receiving
671 */
672 sig_ker_rx_not_ready_to_receive_req();
673 MFREE_DESC2(uart_data->ker.rx_data_desc);
674 uart_data->ker.rx_data_desc = NULL;
675 /*
676 * set dlc values
677 */
678 dlc = &uart_data->dlc_table[UART_CONTROL_INSTANCE];
679 dlc->drx = &uart_data->drx_base[0];
680 dlc->dtx = &uart_data->dtx_base[0];
681 dlc->dlci = 0;
682 dlc->priority = 0;
683 /*
684 * set RX and TX in ready mode
685 */
686 sig_ker_rx_ready_mode_req();
687 sig_ker_tx_ready_mode_req();
688 /*
689 * set frame size for ready mode
690 */
691 uart_data->n1 = UART_N1_READY_MODE;
692 /*
693 * set DRX and DTX in ready mode
694 */
695 uart_data->dtx = dlc->dtx;
696 uart_data->drx = dlc->drx;
697 sig_ker_drx_ready_mode_req(UART_CONTROL_INSTANCE);
698 sig_ker_dtx_ready_mode_req(UART_CONTROL_INSTANCE);
699 /*
700 * inform ACI about entering ready mode
701 */
702 uart_mux_close_ind->device = uart_data->device;
703 PSEND(hCommMMI, uart_mux_close_ind);
704 }
705 break;
706
707 default:
708 TRACE_ERROR( "SIG_TX_KER_FLUSHED_IND unexpected" );
709 break;
710 }
711 }
712
713 /*
714 * no more UART port related primitives
715 * so clear all flags
716 */
717 uart_data->ker.received_prim = 0;
718
719 /*
720 * primitives of the DLC
721 */
722 for(i = 0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
723 {
724 dlc = &uart_data->dlc_table[i];
725 if(dlc->received_prim)
726 {
727 /*
728 * UART_RING_REQ
729 * UART_DCD_REQ
730 * DTI_DATA_REQ (line states)
731 */
732 if((dlc->received_prim & UART_RING_REQ_MASK) ||
733 (dlc->received_prim & UART_DCD_REQ_MASK) ||
734 (dlc->received_prim & UART_DTI_DATA_REQ_MASK))
735 {
736 /*
737 * send new line states
738 */
739 switch( GET_STATE( UART_SERVICE_KER ) )
740 {
741 case KER_READY:
742 sig_ker_tx_line_states_req(UART_CONTROL_INSTANCE);
743 break;
744
745 case KER_MUX:
746 /*
747 * send MSC frame to peer
748 */
749 ker_mux_send_line_states (uart_data->dlc_instance[dlc->dlci]);
750 break;
751
752 default:
753 if(dlc->received_prim & UART_RING_REQ_MASK)
754 {
755 TRACE_ERROR( "UART_RING_REQ unexpected" );
756 }
757 if(dlc->received_prim & UART_DCD_REQ_MASK)
758 {
759 TRACE_ERROR( "UART_DCD_REQ unexpected" );
760 }
761 break;
762 }
763 /*
764 * send confirm primitives
765 */
766 if(dlc->received_prim & UART_RING_REQ_MASK)
767 {
768 PALLOC (uart_ring_cnf, UART_RING_CNF);
769 uart_ring_cnf->device = uart_data->device;
770 uart_ring_cnf->dlci = dlc->dlci;
771 PSEND (hCommMMI, uart_ring_cnf);
772 }
773 if(dlc->received_prim & UART_DCD_REQ_MASK)
774 {
775 PALLOC (uart_dcd_cnf, UART_DCD_CNF);
776 uart_dcd_cnf->device = uart_data->device;
777 uart_dcd_cnf->dlci = dlc->dlci;
778 PSEND (hCommMMI, uart_dcd_cnf);
779 }
780 }
781 /*
782 * no more DLC related primitives
783 * so clear all flags
784 */
785 dlc->received_prim = 0;
786 }
787 }
788 uart_data->ker.flush_state = UART_KER_NOT_FLUSHING;
789 }
790 } /* sig_tx_ker_flushed_ind() */
791
792
793
794 /*
795 +------------------------------------------------------------------------------
796 | Function : sig_tx_ker_sending_ind
797 +------------------------------------------------------------------------------
798 | Description : Handles the internal signal SIG_TX_KER_SENDING_IND
799 |
800 | Parameters : no parameters
801 |
802 +------------------------------------------------------------------------------
803 */
804 GLOBAL void sig_tx_ker_sending_ind ()
805 {
806 TRACE_ISIG( "sig_tx_ker_sending_ind" );
807
808 switch( GET_STATE( UART_SERVICE_KER ) )
809 {
810 case KER_MUX_ESTABLISH:
811 case KER_MUX:
812 case KER_MUX_DLC_CLOSING:
813 case KER_MUX_CLOSING:
814 case KER_MUX_CLOSED:
815 uart_data->ker.sending_state = UART_KER_SENDING;
816 break;
817
818 default:
819 TRACE_ERROR( "SIG_TX_KER_SENDING_IND unexpected" );
820 break;
821 }
822 } /* sig_tx_ker_sending_ind() */
823
824
825
826 /*
827 +------------------------------------------------------------------------------
828 | Function : sig_tx_ker_data_sent_ind
829 +------------------------------------------------------------------------------
830 | Description : Handles the internal signal SIG_TX_KER_DATA_SENT_IND
831 |
832 | Parameters : rest_data - not yet sent data
833 | write_pos - position where the not yet sent data starts
834 |
835 +------------------------------------------------------------------------------
836 */
837 GLOBAL void sig_tx_ker_data_sent_ind (T_desc2* rest_data, USHORT read_pos)
838 {
839 TRACE_ISIG( "sig_tx_ker_data_sent_ind" );
840
841 /*
842 * free sent data descriptor
843 */
844 MFREE_DESC2(uart_data->ker.tx_data_desc);
845 uart_data->ker.tx_data_desc = NULL;
846 uart_data->ker.sending_state = UART_KER_NOT_SENDING;
847 if(uart_data->ker.tx_data_waiting)
848 {
849 /*
850 * send next descriptor in waiting queue
851 */
852 uart_data->ker.tx_data_desc = uart_data->ker.tx_data_waiting;
853 uart_data->ker.tx_data_waiting =
854 (T_desc2*)uart_data->ker.tx_data_waiting->next;
855 /*
856 * only one descriptor is sent at a time
857 */
858 uart_data->ker.tx_data_desc->next = (ULONG)NULL;
859 sig_ker_tx_data_available_req( uart_data->ker.tx_data_desc, 0);
860 }
861 else
862 {
863 switch( GET_STATE( UART_SERVICE_KER ) )
864 {
865 case KER_MUX_ESTABLISH:
866 case KER_MUX:
867 case KER_MUX_DLC_CLOSING:
868 case KER_MUX_CLOSING:
869 break;
870
871 case KER_MUX_CLOSED:
872 /*
873 * flush UART before enter ready mode
874 */
875 uart_data->ker.received_prim|= UART_MUX_CLOSE_REQ_MASK;
876
877 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
878 {
879 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
880 sig_ker_tx_flush_req();
881 }
882 break;
883
884 default:
885 TRACE_ERROR( "SIG_TX_KER_DATA_SENT_IND unexpected" );
886 break;
887 }
888 }
889 } /* sig_tx_ker_data_sent_ind() */
890
891
892
893 /*
894 +------------------------------------------------------------------------------
895 | Function : sig_rx_ker_receiving_ind
896 +------------------------------------------------------------------------------
897 | Description : Handles the internal signal SIG_RX_KER_RECEIVING_IND
898 |
899 | Parameters : no parameters
900 |
901 +------------------------------------------------------------------------------
902 */
903 GLOBAL void sig_rx_ker_receiving_ind ()
904 {
905 TRACE_ISIG( "sig_rx_ker_receiving_ind" );
906
907 switch( GET_STATE( UART_SERVICE_KER ) )
908 {
909 case KER_MUX_ESTABLISH:
910 case KER_MUX:
911 case KER_MUX_DLC_CLOSING:
912 case KER_MUX_CLOSING:
913 case KER_MUX_CLOSED:
914 uart_data->ker.receiving_state = UART_KER_RECEIVING;
915 break;
916 default:
917 TRACE_ERROR( "SIG_RX_KER_RECEIVING_IND unexpected" );
918 break;
919 }
920 } /* sig_rx_ker_receiving_ind() */
921
922
923
924 /*
925 +------------------------------------------------------------------------------
926 | Function : sig_rx_ker_data_received_ind
927 +------------------------------------------------------------------------------
928 | Description : Handles the internal signal SIG_RX_KER_DATA_RECEIVED_IND
929 | which is used to process a received frame.
930 |
931 | Precondition is that the frame has a length >2 without flags.
932 |
933 | Parameters : received_data - received data
934 | write_pos - write position for the next reception
935 |
936 +------------------------------------------------------------------------------
937 */
938 GLOBAL void sig_rx_ker_data_received_ind (T_desc2* received_data,
939 USHORT write_pos)
940 {
941 UBYTE i;
942 UBYTE dlci;
943 T_DLC* dlc;
944 ULONG forward;
945 BOOL continuous;
946
947 TRACE_ISIG( "sig_rx_ker_data_received_ind" );
948
949 #ifndef _TARGET_
950 if(received_data->len)
951 {
952 USHORT pos;
953 char buf[90];
954 /*
955 * trace output
956 */
957 TRACE_EVENT("======= IN");
958 i = 0;
959 pos = 0;
960 while(pos < received_data->len)
961 {
962 i+= sprintf(&buf[i], "0x%02x, ", received_data->buffer[pos]);
963 pos++;
964 if(i > 80)
965 {
966 TRACE_EVENT( buf );
967 i = 0;
968 }
969 else if(pos >= received_data->len)
970 {
971 TRACE_EVENT( buf );
972 }
973 }
974 }
975 #endif /* !_TARGET_ */
976
977 uart_data->ker.receiving_state = UART_KER_NOT_RECEIVING;
978
979 switch( GET_STATE( UART_SERVICE_KER ) )
980 {
981 case KER_MUX_ESTABLISH:
982 if(received_data->len EQ 0)
983 {
984 /*
985 * prepare next reception
986 */
987 sig_ker_rx_ready_to_receive_req(received_data,
988 write_pos,
989 (USHORT)(uart_data->n1 + 2));
990 break;
991 }
992 dlci = received_data->buffer[UART_OFFSET_ADDRESS] >> UART_DLCI_POS;
993 if((dlci EQ UART_DLCI_CONTROL) &&
994 (received_data->buffer[UART_OFFSET_CONTROL] EQ UART_SABM_FRAME))
995 {
996 /*
997 * analyze SABM frame
998 */
999 forward = 0;
1000 ker_receive_sabm_frame(&forward, received_data);
1001 /*
1002 * set dlc value
1003 */
1004 dlc = &uart_data->dlc_table[UART_CONTROL_INSTANCE];
1005 if((forward & UART_FORWARD_SABM) &&
1006 (dlc->connection_state EQ UART_CONNECTION_SABM_RCVD) &&
1007 (uart_data->dlc_instance[dlci] NEQ UART_CONTROL_INSTANCE))
1008 {
1009 SET_STATE( UART_SERVICE_KER, KER_MUX );
1010 /*
1011 * stop timer
1012 */
1013 sig_ker_rt_stop_t3_req();
1014 /*
1015 * setup dlc parameter
1016 */
1017 uart_data->dlc_instance[dlci] = UART_CONTROL_INSTANCE;
1018 dlc->connection_state = UART_CONNECTION_OPEN;
1019 /*
1020 * set priority
1021 */
1022 dlc->priority = 0;
1023 /*
1024 * send response frame
1025 */
1026 if(forward & UART_FORWARD_RESPONSE)
1027 {
1028 ker_mux_send_frame(received_data);
1029 /*
1030 * prepare next reception
1031 */
1032 MALLOC(received_data, (USHORT)(sizeof(T_desc2) - 1
1033 + uart_data->n1
1034 + 2));
1035 received_data->next = (ULONG)NULL;
1036 }
1037 }
1038 }
1039 /*
1040 * prepare next reception
1041 */
1042 received_data->len = 0;
1043 uart_data->ker.rx_data_desc = received_data;
1044 sig_ker_rx_ready_to_receive_req(received_data,
1045 0,
1046 (USHORT)(uart_data->n1 + 2));
1047 break;
1048
1049 case KER_MUX:
1050 if(received_data->len EQ 0)
1051 {
1052 /*
1053 * prepare next reception
1054 */
1055 sig_ker_rx_ready_to_receive_req(received_data,
1056 write_pos,
1057 (USHORT)(uart_data->n1 + 2));
1058 break;
1059 }
1060 /*
1061 * analyze frame and messages
1062 */
1063 forward = 0;
1064 switch(received_data->buffer[UART_OFFSET_CONTROL])
1065 {
1066 case UART_SABM_FRAME:
1067 ker_receive_sabm_frame(&forward, received_data);
1068 break;
1069
1070 case UART_UA_FRAME:
1071 ker_receive_ua_frame(&forward, received_data);
1072 break;
1073
1074 case UART_DM_CONTROL_FRAME:
1075 case UART_DM_DATA_FRAME:
1076 ker_receive_dm_frame(&forward, received_data);
1077 break;
1078
1079 case UART_DISC_FRAME:
1080 ker_receive_disc_frame(&forward, received_data);
1081 break;
1082
1083 case UART_UIH_CONTROL_FRAME:
1084 ker_receive_uih_control_frame(&forward, received_data);
1085 break;
1086
1087 case UART_UIH_DATA_FRAME:
1088 ker_receive_uih_data_frame(&forward, received_data);
1089 break;
1090
1091 default:
1092 {
1093 TRACE_EVENT_P2("Warning: Unexpected HDLC value: %d, uart_kers.c(%d)",
1094 received_data->buffer[UART_OFFSET_CONTROL], __LINE__);
1095 break;
1096 }
1097 }
1098 /*
1099 * remove resonded frames and send next frames in command queue
1100 */
1101 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1102 {
1103 dlc = &uart_data->dlc_table[i];
1104 switch(dlc->connection_state)
1105 {
1106 case UART_CONNECTION_OPEN:
1107 case UART_CONNECTION_DISC_SENT:
1108 if((dlc->last_command NEQ NULL) &&
1109 (dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1110 UART_UIH_CONTROL_FRAME) &&
1111 (dlc->last_command->len EQ UART_OFFSET_INFO))
1112 {
1113 /*
1114 * remove responded UIH frame
1115 */
1116 MFREE_DESC2(dlc->last_command);
1117 dlc->last_command = NULL;
1118 uart_data->ker.nr_t2--;
1119 if( uart_data->ker.nr_t2 EQ 0 )
1120 sig_ker_rt_stop_t2_req();
1121 }
1122 if((dlc->last_command EQ NULL) &&
1123 (dlc->next_command NEQ NULL))
1124 {
1125 T_desc2* temp_desc;
1126 /*
1127 * transmit next command frame
1128 */
1129 dlc->last_command = dlc->next_command;
1130 dlc->next_command = (T_desc2*)dlc->next_command->next;
1131 dlc->last_command->next = (ULONG)NULL;
1132
1133 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 +
1134 dlc->last_command->len));
1135 temp_desc->next = (ULONG)NULL;
1136 temp_desc->len = dlc->last_command->len;
1137 memcpy(temp_desc->buffer,
1138 dlc->last_command->buffer,
1139 dlc->last_command->len);
1140
1141 dlc->retransmissions = 0;
1142 ker_mux_send_frame(temp_desc);
1143
1144 if(dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1145 UART_UIH_CONTROL_FRAME)
1146 {
1147 uart_data->ker.nr_t2++;
1148 sig_ker_rt_start_t2_req();
1149 }
1150 else
1151 {
1152 uart_data->ker.nr_t1++;
1153 sig_ker_rt_start_t1_req();
1154 }
1155 }
1156 break;
1157
1158 case UART_CONNECTION_DEAD:
1159 break;
1160
1161 default:
1162 {
1163 TRACE_EVENT_P2("Unexpected DLC connection state: %d, uart_kers.c(%d)",
1164 dlc->connection_state, __LINE__);
1165 break;
1166 }
1167 }
1168 }
1169 /*
1170 * process results of analysis
1171 */
1172 if(forward)
1173 {
1174 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1175 {
1176 if(i NEQ UART_CONTROL_INSTANCE)
1177 {
1178 /*
1179 * set dlc values
1180 */
1181 dlc = &uart_data->dlc_table[i];
1182 dlci = dlc->dlci;
1183 /*
1184 * channel to open
1185 */
1186 if((forward & UART_FORWARD_SABM) &&
1187 (dlc->connection_state EQ UART_CONNECTION_SABM_RCVD) &&
1188 (uart_data->dlc_instance[dlci] NEQ i))
1189 {
1190 PALLOC(uart_mux_dlc_establish_ind, UART_MUX_DLC_ESTABLISH_IND);
1191 /*
1192 * setup dlc parameter
1193 */
1194 uart_data->dlc_instance[dlci] = i;
1195 dlc->drx = &uart_data->drx_base[i];
1196 dlc->dtx = &uart_data->dtx_base[i];
1197 /*
1198 * set priority
1199 */
1200 if(dlci < 8)
1201 dlc->priority = 7;
1202 else if(dlci < 16)
1203 dlc->priority = 15;
1204 else if(dlci < 24)
1205 dlc->priority = 23;
1206 else if(dlci < 32)
1207 dlc->priority = 31;
1208 else if(dlci < 40)
1209 dlc->priority = 39;
1210 else if(dlci < 48)
1211 dlc->priority = 47;
1212 else if(dlci < 56)
1213 dlc->priority = 55;
1214 else
1215 dlc->priority = 61;
1216 /*
1217 * store response frame and
1218 * clear appropriate bit in forward mask
1219 */
1220 dlc->next_command = received_data;
1221 forward &= ~UART_FORWARD_RESPONSE;
1222 /*
1223 * create new reception frame
1224 */
1225 MALLOC(received_data, (USHORT)(sizeof(T_desc2) - 1
1226 + uart_data->n1
1227 + 2));
1228 received_data->next = (ULONG)NULL;
1229 /*
1230 * inform ACI about new DLC
1231 */
1232 uart_mux_dlc_establish_ind->device = uart_data->device;
1233 uart_mux_dlc_establish_ind->dlci = dlci;
1234 uart_mux_dlc_establish_ind->
1235 convergence = UART_MUX_CONVERGENCE_UOS;
1236 uart_mux_dlc_establish_ind->n1 = uart_data->n1;
1237 uart_mux_dlc_establish_ind->
1238 service = UART_MUX_SERVICE_AT;
1239 PSEND (hCommMMI, uart_mux_dlc_establish_ind);
1240 }
1241 /*
1242 * channel to close
1243 */
1244 if((forward & UART_FORWARD_DLC_RELEASE) &&
1245 (dlc->connection_state EQ UART_CONNECTION_DEAD) &&
1246 (dlci NEQ UART_DLCI_INVALID))
1247 {
1248 PALLOC(uart_mux_dlc_release_ind, UART_MUX_DLC_RELEASE_IND);
1249 /*
1250 * release channel
1251 */
1252 ker_mux_dlc_release(i);
1253 /*
1254 * inform ACI about DLC release
1255 */
1256 uart_mux_dlc_release_ind->device = uart_data->device;
1257 uart_mux_dlc_release_ind->dlci = dlci;
1258 PSEND(hCommMMI, uart_mux_dlc_release_ind);
1259 }
1260 /*
1261 * set Flow Control ON
1262 */
1263 if((forward & UART_FORWARD_FCON) &&
1264 (dlc->connection_state EQ UART_CONNECTION_OPEN) &&
1265 (!(dlc->lines & UART_FC_RX_MASK)))
1266 {
1267 uart_data->drx = dlc->drx;
1268 sig_ker_drx_enable_req();
1269 }
1270 /*
1271 * set Flow Control OFF
1272 */
1273 if((forward & UART_FORWARD_FCOFF) &&
1274 (dlc->connection_state EQ UART_CONNECTION_OPEN) &&
1275 (!(dlc->lines & UART_FC_RX_MASK)))
1276 {
1277 uart_data->drx = dlc->drx;
1278 sig_ker_drx_disable_req();
1279 }
1280 /*
1281 * send status lines
1282 */
1283 if((forward & UART_FORWARD_MSC) &&
1284 (dlc->connection_state EQ UART_CONNECTION_OPEN))
1285 {
1286 UBYTE st_flow;
1287 UBYTE st_line_sa;
1288 UBYTE st_break_len;
1289 /*
1290 * send primitive if DTR drop is detected
1291 */
1292 if(dlc->lines & UART_DTR_MASK)
1293 {
1294 PALLOC (uart_detected_ind, UART_DETECTED_IND);
1295 uart_detected_ind->device = uart_data->device;
1296 uart_detected_ind->dlci = dlc->dlci;
1297 uart_detected_ind->cause = UART_DETECT_DTR;
1298 PSEND (hCommMMI, uart_detected_ind);
1299 }
1300 /*
1301 * set line states
1302 */
1303 if(dlc->lines & UART_RTS_MASK)
1304 st_flow = DTI_FLOW_OFF;
1305 else
1306 st_flow = DTI_FLOW_ON;
1307 if(dlc->lines & UART_DTR_MASK)
1308 st_line_sa = DTI_SA_OFF;
1309 else
1310 st_line_sa = DTI_SA_ON;
1311 /*
1312 * set break
1313 */
1314 if(dlc->lines & UART_BRK_RX_MASK)
1315 st_break_len = (UBYTE)((dlc->lines & UART_BRKLEN_RX_MASK) >>
1316 UART_BRKLEN_RX_POS);
1317 else
1318 st_break_len = DTI_BREAK_OFF;
1319 /*
1320 * send flow control signals
1321 */
1322 if(uart_data->ker.data_flow_tx EQ UART_FLOW_ENABLED)
1323 {
1324 uart_data->drx = dlc->drx;
1325 if(dlc->lines & UART_FC_RX_MASK)
1326 sig_ker_drx_disable_req();
1327 else
1328 sig_ker_drx_enable_req();
1329 }
1330 /*
1331 * send line states
1332 */
1333 uart_data->dtx = dlc->dtx;
1334 sig_ker_dtx_line_states_req(st_flow,
1335 st_line_sa,
1336 DTI_SB_ON,
1337 st_break_len);
1338 }
1339 }
1340 }
1341 /*
1342 * send response frame
1343 */
1344 if(forward & UART_FORWARD_RESPONSE)
1345 {
1346 ker_mux_send_frame(received_data);
1347 uart_data->ker.rx_data_desc = NULL;
1348 }
1349 /*
1350 * Close-Down multiplexer
1351 */
1352 if(forward & UART_FORWARD_CLD)
1353 {
1354 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSED );
1355 /*
1356 * stop timers and
1357 * remove all DLC instances
1358 */
1359 ker_mux_close_down();
1360 /*
1361 * flush UART before change the state
1362 */
1363 if(uart_data->ker.tx_data_desc EQ NULL)
1364 {
1365 uart_data->ker.received_prim|= UART_MUX_CLOSE_REQ_MASK;
1366
1367 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
1368 {
1369 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
1370 sig_ker_tx_flush_req();
1371 }
1372 }
1373 }
1374 }
1375 /*
1376 * prepare next reception
1377 */
1378 if(forward & UART_FORWARD_RESPONSE)
1379 {
1380 MALLOC(received_data, (USHORT)(sizeof(T_desc2) - 1
1381 + uart_data->n1
1382 + 2));
1383 received_data->next = (ULONG)NULL;
1384 }
1385 received_data->len = 0;
1386 uart_data->ker.rx_data_desc = received_data;
1387 sig_ker_rx_ready_to_receive_req(received_data,
1388 0,
1389 (USHORT)(uart_data->n1 + 2));
1390 break;
1391
1392 case KER_MUX_DLC_CLOSING:
1393 if(received_data->len EQ 0)
1394 {
1395 /*
1396 * prepare next reception
1397 */
1398 sig_ker_rx_ready_to_receive_req(received_data,
1399 write_pos,
1400 (USHORT)(uart_data->n1 + 2));
1401 break;
1402 }
1403 /*
1404 * analyze frame and messages
1405 */
1406 forward = 0;
1407 switch(received_data->buffer[UART_OFFSET_CONTROL])
1408 {
1409 case UART_SABM_FRAME:
1410 ker_receive_sabm_frame(&forward, received_data);
1411 break;
1412
1413 case UART_UA_FRAME:
1414 ker_receive_ua_frame(&forward, received_data);
1415 break;
1416
1417 case UART_DM_CONTROL_FRAME:
1418 case UART_DM_DATA_FRAME:
1419 ker_receive_dm_frame(&forward, received_data);
1420 break;
1421
1422 case UART_DISC_FRAME:
1423 ker_receive_disc_frame(&forward, received_data);
1424 break;
1425
1426 case UART_UIH_CONTROL_FRAME:
1427 ker_receive_uih_control_frame(&forward, received_data);
1428 break;
1429
1430 case UART_UIH_DATA_FRAME:
1431 ker_receive_uih_data_frame(&forward, received_data);
1432 break;
1433
1434 default:
1435 {
1436 TRACE_EVENT_P2("Warning: Unexpected HDLC value: %d, uart_kers.c(%d)",
1437 received_data->buffer[UART_OFFSET_CONTROL], __LINE__);
1438 break;
1439 }
1440 }
1441 /*
1442 * remove resonded frames and send next frames in command queue
1443 */
1444 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1445 {
1446 dlc = &uart_data->dlc_table[i];
1447 switch(dlc->connection_state)
1448 {
1449 case UART_CONNECTION_OPEN:
1450 case UART_CONNECTION_DISC_SENT:
1451 if((dlc->last_command NEQ NULL) &&
1452 (dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1453 UART_UIH_CONTROL_FRAME) &&
1454 (dlc->last_command->len EQ UART_OFFSET_INFO))
1455 {
1456 /*
1457 * remove responded UIH frame
1458 */
1459 MFREE_DESC2(dlc->last_command);
1460 dlc->last_command = NULL;
1461 uart_data->ker.nr_t2--;
1462 if( uart_data->ker.nr_t2 EQ 0 )
1463 sig_ker_rt_stop_t2_req();
1464 }
1465 if((dlc->last_command EQ NULL) &&
1466 (dlc->next_command NEQ NULL))
1467 {
1468 T_desc2* temp_desc;
1469 /*
1470 * transmit next command frame
1471 */
1472 dlc->last_command = dlc->next_command;
1473 dlc->next_command = (T_desc2*)dlc->next_command->next;
1474 dlc->last_command->next = (ULONG)NULL;
1475
1476 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 +
1477 dlc->last_command->len));
1478 temp_desc->next = (ULONG)NULL;
1479 temp_desc->len = dlc->last_command->len;
1480 memcpy(temp_desc->buffer,
1481 dlc->last_command->buffer,
1482 dlc->last_command->len);
1483
1484 dlc->retransmissions = 0;
1485 ker_mux_send_frame(temp_desc);
1486
1487 if(dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1488 UART_UIH_CONTROL_FRAME)
1489 {
1490 uart_data->ker.nr_t2++;
1491 sig_ker_rt_start_t2_req();
1492 }
1493 else
1494 {
1495 uart_data->ker.nr_t1++;
1496 sig_ker_rt_start_t1_req();
1497 }
1498 }
1499 break;
1500
1501 case UART_CONNECTION_DEAD:
1502 break;
1503
1504 default:
1505 {
1506 TRACE_EVENT_P2("Unexpected DLC connection state: %d, uart_kers.c(%d)",
1507 dlc->connection_state, __LINE__);
1508 break;
1509 }
1510 }
1511 }
1512 /*
1513 * process results of analysis
1514 */
1515 if(forward)
1516 {
1517 continuous = FALSE;
1518 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1519 {
1520 if(i NEQ UART_CONTROL_INSTANCE)
1521 {
1522 /*
1523 * set dlc values
1524 */
1525 dlc = &uart_data->dlc_table[i];
1526 dlci = dlc->dlci;
1527 /*
1528 * channel to open
1529 */
1530 if((forward & UART_FORWARD_SABM) &&
1531 (dlc->connection_state EQ UART_CONNECTION_SABM_RCVD))
1532 {
1533 /*
1534 * reject all attempts to open a channel
1535 */
1536 received_data->buffer[UART_OFFSET_CONTROL] =
1537 UART_DM_CONTROL_FRAME;
1538 /*
1539 * release channel
1540 */
1541 ker_mux_dlc_release(i);
1542 }
1543 /*
1544 * channel to close
1545 */
1546 if((forward & UART_FORWARD_DLC_RELEASE) &&
1547 (dlc->connection_state EQ UART_CONNECTION_DEAD) &&
1548 (dlci NEQ UART_DLCI_INVALID))
1549 {
1550 /*
1551 * release channel
1552 */
1553 ker_mux_dlc_release(i);
1554 }
1555 if(dlc->connection_state NEQ UART_CONNECTION_DEAD)
1556 continuous = TRUE;
1557 }
1558 }
1559 /*
1560 * send response frame
1561 */
1562 if(forward & UART_FORWARD_RESPONSE)
1563 {
1564 ker_mux_send_frame(received_data);
1565 uart_data->ker.rx_data_desc = NULL;
1566 }
1567 /*
1568 * Close-Down multiplexer
1569 */
1570 if(forward & UART_FORWARD_CLD)
1571 {
1572 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSED );
1573 /*
1574 * stop timers and
1575 * remove all DLC instances
1576 */
1577 ker_mux_close_down();
1578 /*
1579 * flush UART before change the state
1580 */
1581 if(uart_data->ker.tx_data_desc EQ NULL)
1582 {
1583 uart_data->ker.received_prim|= UART_MUX_CLOSE_REQ_MASK;
1584
1585 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
1586 {
1587 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
1588 sig_ker_tx_flush_req();
1589 }
1590 }
1591 }
1592 /*
1593 * change state if all channels are closed
1594 */
1595 else if(continuous EQ FALSE)
1596 {
1597 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSING );
1598 /*
1599 * build and send CLD command frame:
1600 */
1601 ker_mux_send_close_down();
1602 /*
1603 * start timer
1604 */
1605 sig_ker_rt_start_t3_req();
1606 }
1607 }
1608 /*
1609 * prepare next reception
1610 */
1611 if(forward & UART_FORWARD_RESPONSE)
1612 {
1613 MALLOC(received_data, (USHORT)(sizeof(T_desc2) - 1
1614 + uart_data->n1
1615 + 2));
1616 received_data->next = (ULONG)NULL;
1617 }
1618 received_data->len = 0;
1619 uart_data->ker.rx_data_desc = received_data;
1620 sig_ker_rx_ready_to_receive_req(received_data,
1621 0,
1622 (USHORT)(uart_data->n1 + 2));
1623 break;
1624
1625 case KER_MUX_CLOSING:
1626 if(received_data->len EQ 0)
1627 {
1628 /*
1629 * prepare next reception
1630 */
1631 sig_ker_rx_ready_to_receive_req(received_data,
1632 write_pos,
1633 (USHORT)(uart_data->n1 + 2));
1634 break;
1635 }
1636 /*
1637 * analyze frame and messages
1638 */
1639 forward = 0;
1640 switch(received_data->buffer[UART_OFFSET_CONTROL])
1641 {
1642 case UART_SABM_FRAME:
1643 ker_receive_sabm_frame(&forward, received_data);
1644 break;
1645
1646 case UART_UA_FRAME:
1647 ker_receive_ua_frame(&forward, received_data);
1648 break;
1649
1650 case UART_DM_CONTROL_FRAME:
1651 case UART_DM_DATA_FRAME:
1652 ker_receive_dm_frame(&forward, received_data);
1653 break;
1654
1655 case UART_DISC_FRAME:
1656 ker_receive_disc_frame(&forward, received_data);
1657 break;
1658
1659 case UART_UIH_CONTROL_FRAME:
1660 ker_receive_uih_control_frame(&forward, received_data);
1661 break;
1662
1663 case UART_UIH_DATA_FRAME:
1664 ker_receive_uih_data_frame(&forward, received_data);
1665 break;
1666
1667 default:
1668 {
1669 TRACE_EVENT_P2("Warning: Unexpected HDLC value: %d, uart_kers.c(%d)",
1670 received_data->buffer[UART_OFFSET_CONTROL], __LINE__);
1671 break;
1672 }
1673 }
1674 /*
1675 * remove resonded frames and send next frames in command queue
1676 */
1677 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1678 {
1679 dlc = &uart_data->dlc_table[i];
1680 switch(dlc->connection_state)
1681 {
1682 case UART_CONNECTION_OPEN:
1683 case UART_CONNECTION_DISC_SENT:
1684 if((dlc->last_command NEQ NULL) &&
1685 (dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1686 UART_UIH_CONTROL_FRAME) &&
1687 (dlc->last_command->len EQ UART_OFFSET_INFO))
1688 {
1689 /*
1690 * remove responded UIH frame
1691 */
1692 MFREE_DESC2(dlc->last_command);
1693 dlc->last_command = NULL;
1694 uart_data->ker.nr_t2--;
1695 if( uart_data->ker.nr_t2 EQ 0 )
1696 sig_ker_rt_stop_t2_req();
1697 }
1698 if((dlc->last_command EQ NULL) &&
1699 (dlc->next_command NEQ NULL))
1700 {
1701 T_desc2* temp_desc;
1702 /*
1703 * transmit next command frame
1704 */
1705 dlc->last_command = dlc->next_command;
1706 dlc->next_command = (T_desc2*)dlc->next_command->next;
1707 dlc->last_command->next = (ULONG)NULL;
1708
1709 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 +
1710 dlc->last_command->len));
1711 temp_desc->next = (ULONG)NULL;
1712 temp_desc->len = dlc->last_command->len;
1713 memcpy(temp_desc->buffer,
1714 dlc->last_command->buffer,
1715 dlc->last_command->len);
1716
1717 dlc->retransmissions = 0;
1718 ker_mux_send_frame(temp_desc);
1719
1720 if(dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
1721 UART_UIH_CONTROL_FRAME)
1722 {
1723 uart_data->ker.nr_t2++;
1724 sig_ker_rt_start_t2_req();
1725 }
1726 else
1727 {
1728 uart_data->ker.nr_t1++;
1729 sig_ker_rt_start_t1_req();
1730 }
1731 }
1732 break;
1733
1734 case UART_CONNECTION_DEAD:
1735 break;
1736
1737 default:
1738 {
1739 TRACE_EVENT_P2("Unexpected DLC connection state: %d, uart_kers.c(%d)",
1740 dlc->connection_state,__LINE__);
1741 break;
1742 }
1743 }
1744 }
1745 /*
1746 * process results of analysis
1747 */
1748 if(forward)
1749 {
1750 for(i=0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++)
1751 {
1752 if(i NEQ UART_CONTROL_INSTANCE)
1753 {
1754 /*
1755 * set dlc values
1756 */
1757 dlc = &uart_data->dlc_table[i];
1758 dlci = dlc->dlci;
1759 /*
1760 * channel to open
1761 */
1762 if((forward & UART_FORWARD_SABM) &&
1763 (dlc->connection_state EQ UART_CONNECTION_SABM_RCVD))
1764 {
1765 /*
1766 * reject all attempts to open a channel
1767 */
1768 received_data->buffer[UART_OFFSET_CONTROL] =
1769 UART_DM_CONTROL_FRAME;
1770 /*
1771 * release channel
1772 */
1773 ker_mux_dlc_release(i);
1774 }
1775 /*
1776 * channel to close
1777 */
1778 if((forward & UART_FORWARD_DLC_RELEASE) &&
1779 (dlc->connection_state EQ UART_CONNECTION_DEAD) &&
1780 (dlci NEQ UART_DLCI_INVALID))
1781 {
1782 /*
1783 * release channel
1784 */
1785 ker_mux_dlc_release(i);
1786 }
1787 }
1788 }
1789 /*
1790 * send response frame
1791 */
1792 if(forward & UART_FORWARD_RESPONSE)
1793 {
1794 ker_mux_send_frame(received_data);
1795 uart_data->ker.rx_data_desc = NULL;
1796 }
1797 /*
1798 * Close-Down multiplexer
1799 */
1800 if(forward & UART_FORWARD_CLD)
1801 {
1802 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSED );
1803 /*
1804 * stop timers and
1805 * remove all DLC instances
1806 */
1807 ker_mux_close_down();
1808 /*
1809 * flush UART before change the state
1810 */
1811 if(uart_data->ker.tx_data_desc EQ NULL)
1812 {
1813 uart_data->ker.received_prim|= UART_MUX_CLOSE_REQ_MASK;
1814
1815 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
1816 {
1817 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
1818 sig_ker_tx_flush_req();
1819 }
1820 }
1821 }
1822 }
1823 /*
1824 * prepare next reception
1825 */
1826 if(forward & UART_FORWARD_RESPONSE)
1827 {
1828 MALLOC(received_data, (USHORT)(sizeof(T_desc2) - 1
1829 + uart_data->n1
1830 + 2));
1831 received_data->next = (ULONG)NULL;
1832 }
1833 received_data->len = 0;
1834 uart_data->ker.rx_data_desc = received_data;
1835 sig_ker_rx_ready_to_receive_req(received_data,
1836 0,
1837 (USHORT)(uart_data->n1 + 2));
1838 break;
1839
1840 case KER_MUX_CLOSED:
1841 if((uart_data->ker.tx_data_desc EQ NULL) &&
1842 (uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING))
1843 {
1844 PALLOC(uart_mux_close_ind, UART_MUX_CLOSE_IND);
1845 SET_STATE( UART_SERVICE_KER, KER_READY );
1846 /*
1847 * free receiving buffer
1848 */
1849 MFREE_DESC2(uart_data->ker.rx_data_desc);
1850 uart_data->ker.rx_data_desc = NULL;
1851 /*
1852 * set dlc values
1853 */
1854 dlc = &uart_data->dlc_table[UART_CONTROL_INSTANCE];
1855 dlc->drx = &uart_data->drx_base[0];
1856 dlc->dtx = &uart_data->dtx_base[0];
1857 dlc->dlci = 0;
1858 dlc->priority = 0;
1859 /*
1860 * set RX and TX in ready mode
1861 */
1862 sig_ker_rx_ready_mode_req();
1863 sig_ker_tx_ready_mode_req();
1864 /*
1865 * set frame size for ready mode
1866 */
1867 uart_data->n1 = UART_N1_READY_MODE;
1868 /*
1869 * set DRX and DTX in ready mode
1870 */
1871 uart_data->dtx = dlc->dtx;
1872 uart_data->drx = dlc->drx;
1873 sig_ker_drx_ready_mode_req(UART_CONTROL_INSTANCE);
1874 sig_ker_dtx_ready_mode_req(UART_CONTROL_INSTANCE);
1875 /*
1876 * inform ACI about entering ready mode
1877 */
1878 uart_mux_close_ind->device = uart_data->device;
1879 PSEND(hCommMMI, uart_mux_close_ind);
1880 }
1881 else if(received_data->len EQ 0)
1882 {
1883 /*
1884 * prepare next reception
1885 */
1886 sig_ker_rx_ready_to_receive_req(received_data,
1887 write_pos,
1888 (USHORT)(uart_data->n1 + 2));
1889 }
1890 else
1891 {
1892 /*
1893 * prepare next reception
1894 */
1895 received_data->len = 0;
1896 sig_ker_rx_ready_to_receive_req(received_data,
1897 0,
1898 (USHORT)(uart_data->n1 + 2));
1899 }
1900 break;
1901
1902 default:
1903 TRACE_ERROR( "SIG_RX_KER_DATA_RECEIVED_IND unexpected" );
1904 break;
1905 }
1906 } /* sig_rx_ker_data_received_ind() */
1907
1908
1909
1910 /*
1911 +------------------------------------------------------------------------------
1912 | Function : sig_rx_ker_line_states_ind
1913 +------------------------------------------------------------------------------
1914 | Description : Handles the internal signal SIG_RX_KER_LINE_STATES_IND
1915 |
1916 | Parameters : line_states - new line states
1917 |
1918 +------------------------------------------------------------------------------
1919 */
1920 GLOBAL void sig_rx_ker_line_states_ind (ULONG line_states)
1921 {
1922 T_DLC* dlc;
1923 UBYTE st_flow;
1924 UBYTE st_line_sa;
1925 UBYTE st_line_sb;
1926 UBYTE st_break_len;
1927
1928 TRACE_ISIG( "sig_rx_ker_line_states_ind" );
1929
1930 /*
1931 * set DLC
1932 */
1933 dlc = &uart_data->dlc_table[UART_CONTROL_INSTANCE];
1934 /*
1935 * send primitive if escape sequence or DTR drop is detected
1936 */
1937 if(line_states & UART_ESC_RX_MASK)
1938 {
1939 PALLOC (uart_detected_ind, UART_DETECTED_IND);
1940 uart_detected_ind->device = uart_data->device;
1941 uart_detected_ind->dlci = dlc->dlci;
1942 uart_detected_ind->cause = UART_DETECT_ESC;
1943 PSEND (hCommMMI, uart_detected_ind);
1944 }
1945 if((line_states & UART_DTR_MASK) AND
1946 (!(dlc->lines & UART_DTR_MASK)))
1947 {
1948 PALLOC (uart_detected_ind, UART_DETECTED_IND);
1949 uart_detected_ind->device = uart_data->device;
1950 uart_detected_ind->dlci = dlc->dlci;
1951 uart_detected_ind->cause = UART_DETECT_DTR;
1952 PSEND (hCommMMI, uart_detected_ind);
1953 }
1954
1955 switch( GET_STATE( UART_SERVICE_KER ) )
1956 {
1957 case KER_READY:
1958 /*
1959 * set line states
1960 */
1961 if(line_states & UART_X_RX_MASK)
1962 st_flow = DTI_FLOW_OFF;
1963 else
1964 st_flow = DTI_FLOW_ON;
1965
1966 if(line_states & UART_SA_RX_MASK)
1967 st_line_sa = DTI_SA_OFF;
1968 else
1969 st_line_sa = DTI_SA_ON;
1970
1971 if(line_states & UART_SB_RX_MASK)
1972 st_line_sb = DTI_SB_OFF;
1973 else
1974 st_line_sb = DTI_SB_ON;
1975
1976 if(line_states & UART_BRK_RX_MASK)
1977 st_break_len = (UBYTE)((line_states & UART_BRKLEN_RX_MASK)
1978 >> UART_BRKLEN_RX_POS);
1979 else
1980 st_break_len = DTI_BREAK_OFF;
1981
1982 uart_data->dtx = dlc->dtx;
1983 sig_ker_dtx_line_states_req(st_flow,
1984 st_line_sa,
1985 st_line_sb,
1986 st_break_len);
1987 break;
1988
1989 case KER_MUX_ESTABLISH:
1990 case KER_MUX:
1991 case KER_MUX_DLC_CLOSING:
1992 case KER_MUX_CLOSING:
1993 case KER_MUX_CLOSED:
1994 break;
1995
1996 default:
1997 TRACE_ERROR( "SIG_RX_KER_LINE_STATES_IND unexpected" );
1998 break;
1999 }
2000 /*
2001 * store new line states
2002 */
2003 dlc->lines &= ~(UART_X_RX_MASK |
2004 UART_SA_RX_MASK |
2005 UART_SB_RX_MASK |
2006 UART_ESC_RX_MASK |
2007 UART_BRK_RX_MASK |
2008 UART_BRKLEN_RX_MASK);
2009 line_states&= ~(UART_ESC_RX_MASK |
2010 UART_BRK_RX_MASK |
2011 UART_BRKLEN_RX_MASK);
2012 dlc->lines |= line_states;
2013 } /* sig_rx_ker_line_states_ind() */
2014
2015
2016
2017 /*
2018 +------------------------------------------------------------------------------
2019 | Function : sig_rt_ker_timeout_t1_ind
2020 +------------------------------------------------------------------------------
2021 | Description : Handles the internal signal SIG_RT_KER_TIMEOUT_T1_IND
2022 |
2023 | Parameters : no parameters
2024 |
2025 +------------------------------------------------------------------------------
2026 */
2027 GLOBAL void sig_rt_ker_timeout_t1_ind ()
2028 {
2029 UBYTE i;
2030 T_desc2* temp_desc;
2031 T_DLC* dlc;
2032 UBYTE j;
2033 UBYTE dlci;
2034 ULONG forward;
2035 BOOL continuous;
2036
2037 TRACE_ISIG( "sig_rt_ker_timeout_t1_ind" );
2038
2039 for( i = 0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++ )
2040 {
2041 /*
2042 * set dlc value
2043 */
2044 dlc = &uart_data->dlc_table[i];
2045 switch(dlc->connection_state)
2046 {
2047 case UART_CONNECTION_OPEN:
2048 case UART_CONNECTION_DISC_SENT:
2049 /*
2050 * T1 is used for non UIH Control frames
2051 */
2052 if((dlc->last_command NEQ NULL) &&
2053 (dlc->last_command->buffer[UART_OFFSET_CONTROL] NEQ
2054 UART_UIH_CONTROL_FRAME))
2055 {
2056 if(dlc->retransmissions < uart_data->ker.n2)
2057 {
2058 /*
2059 * retransmission of Control frame
2060 */
2061 dlc->retransmissions++;
2062 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1
2063 + dlc->last_command->len));
2064
2065 temp_desc->next = (ULONG)NULL;
2066 temp_desc->len = dlc->last_command->len;
2067 memcpy(temp_desc->buffer,
2068 dlc->last_command->buffer,
2069 dlc->last_command->len);
2070
2071 ker_mux_send_frame( temp_desc );
2072 }
2073 else
2074 {
2075 /*
2076 * maximum number of retransmissions reached
2077 */
2078 switch( GET_STATE( UART_SERVICE_KER ) )
2079 {
2080 case KER_MUX:
2081 /*
2082 * act as on reception of a DM frame
2083 */
2084 /*
2085 * create DM frame
2086 */
2087 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 + 2));
2088 temp_desc->next = (ULONG)NULL;
2089 temp_desc->len = 2;
2090 memcpy(temp_desc->buffer, dlc->last_command->buffer, 2)
2091 ;/*lint !e419 !e420 apparent data overrun and access beyond array*/
2092 temp_desc->buffer[UART_OFFSET_CONTROL] = UART_DM_CONTROL_FRAME;
2093 /*
2094 * act as on reception of a DM frame
2095 */
2096 forward = 0;
2097 ker_receive_dm_frame(&forward, temp_desc);
2098 /*
2099 * process results of analysis
2100 */
2101 if(forward)
2102 {
2103 for(j=0; j <= UART_MAX_NUMBER_OF_CHANNELS; j++)
2104 {
2105 if(j NEQ UART_CONTROL_INSTANCE)
2106 {
2107 /*
2108 * set dlc values
2109 */
2110 dlc = &uart_data->dlc_table[j];
2111 dlci = dlc->dlci;
2112 /*
2113 * channel to close
2114 */
2115 if((forward & UART_FORWARD_DLC_RELEASE) &&
2116 (dlc->connection_state EQ UART_CONNECTION_DEAD) &&
2117 (dlci NEQ UART_DLCI_INVALID))
2118 {
2119 PALLOC(uart_mux_dlc_release_ind,
2120 UART_MUX_DLC_RELEASE_IND);
2121 /*
2122 * release channel
2123 */
2124 ker_mux_dlc_release(j);
2125 /*
2126 * inform ACI about DLC release
2127 */
2128 uart_mux_dlc_release_ind->device = uart_data->device;
2129 uart_mux_dlc_release_ind->dlci = dlci;
2130 PSEND(hCommMMI, uart_mux_dlc_release_ind);
2131 }
2132 }
2133 }
2134 }
2135 break;
2136
2137 case KER_MUX_DLC_CLOSING:
2138 /*
2139 * act as on reception of a DM frame
2140 */
2141 /*
2142 * create DM frame
2143 */
2144 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 + 2));
2145 temp_desc->next = (ULONG)NULL;
2146 temp_desc->len = 2;
2147 memcpy(temp_desc->buffer, dlc->last_command->buffer, 2)
2148 ;/*lint !e419 !e420 apparent data overrun and access beyond array*/
2149 temp_desc->buffer[UART_OFFSET_CONTROL] = UART_DM_CONTROL_FRAME;
2150 /*
2151 * act as on reception of a DM frame
2152 */
2153 forward = 0;
2154 ker_receive_dm_frame(&forward, temp_desc);
2155 /*
2156 * process results of analysis
2157 */
2158 if(forward)
2159 {
2160 continuous = FALSE;
2161 for(j=0; j <= UART_MAX_NUMBER_OF_CHANNELS; j++)
2162 {
2163 if(j NEQ UART_CONTROL_INSTANCE)
2164 {
2165 /*
2166 * set dlc values
2167 */
2168 dlc = &uart_data->dlc_table[j];
2169 dlci = dlc->dlci;
2170 /*
2171 * channel to close
2172 */
2173 if((forward & UART_FORWARD_DLC_RELEASE) &&
2174 (dlc->connection_state EQ UART_CONNECTION_DEAD) &&
2175 (dlci NEQ UART_DLCI_INVALID))
2176 {
2177 /*
2178 * release channel
2179 */
2180 ker_mux_dlc_release(j);
2181 }
2182 if(dlc->connection_state NEQ UART_CONNECTION_DEAD)
2183 continuous = TRUE;
2184 }
2185 }
2186 /*
2187 * change state if all channels are closed
2188 */
2189 if(continuous EQ FALSE)
2190 {
2191 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSING );
2192 /*
2193 * build and send CLD command frame:
2194 */
2195 ker_mux_send_close_down();
2196 /*
2197 * start timer
2198 */
2199 sig_ker_rt_start_t3_req();
2200 }
2201 }
2202 break;
2203
2204 case KER_MUX_CLOSING:
2205 /*
2206 * do not care about retransmission couter
2207 * retransmission stops if T3 expires
2208 */
2209 dlc->retransmissions++;
2210 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1
2211 + dlc->last_command->len));
2212
2213 temp_desc->next = (ULONG)NULL;
2214 temp_desc->len = dlc->last_command->len;
2215 memcpy(temp_desc->buffer,
2216 dlc->last_command->buffer,
2217 dlc->last_command->len);
2218
2219 ker_mux_send_frame( temp_desc );
2220 break;
2221
2222 default:
2223 TRACE_ERROR( "SIG_RT_KER_TIMEOUT_T1_IND unexpected" );
2224 break;
2225 }
2226 }
2227 }
2228 break;
2229
2230 case UART_CONNECTION_DEAD:
2231 break;
2232
2233 default:
2234 {
2235 TRACE_EVENT_P2("Unexpected DLC connection state: %d, uart_kers.c(%d)",
2236 dlc->connection_state, __LINE__);
2237 break;
2238 }
2239 }
2240 }
2241 if(uart_data->ker.nr_t1)
2242 {
2243 /*
2244 * restart timer t1
2245 */
2246 sig_ker_rt_start_t1_req();
2247 }
2248 } /* sig_rt_ker_timeout_t1_ind() */
2249
2250
2251
2252 /*
2253 +------------------------------------------------------------------------------
2254 | Function : sig_rt_ker_timeout_t2_ind
2255 +------------------------------------------------------------------------------
2256 | Description : Handles the internal signal SIG_RT_KER_TIMEOUT_T2_IND
2257 |
2258 | This signal means that no response to a sent command frame
2259 | was received within the allowed time. It is assumed that
2260 | the frame has been lost and a retransmission is done if the
2261 | maximum number of retransmissions is not reached yet.
2262 |
2263 | Parameters : no parameters
2264 |
2265 +------------------------------------------------------------------------------
2266 */
2267 GLOBAL void sig_rt_ker_timeout_t2_ind ()
2268 {
2269 UBYTE i;
2270 T_desc2* temp_desc;
2271 T_DLC* dlc;
2272
2273 TRACE_ISIG( "sig_rt_ker_timeout_t2_ind" );
2274
2275 for( i = 0; i <= UART_MAX_NUMBER_OF_CHANNELS; i++ )
2276 {
2277 /*
2278 * set dlc value
2279 */
2280 dlc = &uart_data->dlc_table[i];
2281 switch(dlc->connection_state)
2282 {
2283 case UART_CONNECTION_OPEN:
2284 case UART_CONNECTION_DISC_SENT:
2285 /*
2286 * T2 is only used for UIH Control frames
2287 */
2288 if((dlc->last_command NEQ NULL) &&
2289 (dlc->last_command->buffer[UART_OFFSET_CONTROL] EQ
2290 UART_UIH_CONTROL_FRAME))
2291 {
2292 if(dlc->retransmissions < uart_data->ker.n2)
2293 {
2294 /*
2295 * retransmission of Control frame
2296 */
2297 dlc->retransmissions++;
2298 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1
2299 + dlc->last_command->len));
2300
2301 temp_desc->next = (ULONG)NULL;
2302 temp_desc->len = dlc->last_command->len;
2303 memcpy(temp_desc->buffer,
2304 dlc->last_command->buffer,
2305 dlc->last_command->len);
2306
2307 ker_mux_send_frame( temp_desc );
2308 }
2309 else
2310 {
2311 /*
2312 * maximum number of retransmissions reached
2313 */
2314 switch( GET_STATE( UART_SERVICE_KER ) )
2315 {
2316 case KER_MUX:
2317 case KER_MUX_DLC_CLOSING:
2318 /*
2319 * skip this frame and send next frame
2320 */
2321 /*
2322 * remove current UIH frame
2323 */
2324 MFREE_DESC2(dlc->last_command);
2325 dlc->last_command = NULL;
2326 uart_data->ker.nr_t2--;
2327 if(dlc->next_command)
2328 {
2329 /*
2330 * transmit next command frame
2331 */
2332 dlc->last_command = dlc->next_command;
2333 dlc->next_command = (T_desc2*)dlc->next_command->next;
2334 dlc->last_command->next = (ULONG)NULL;
2335
2336 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1 +
2337 dlc->last_command->len));
2338 temp_desc->next = (ULONG)NULL;
2339 temp_desc->len = dlc->last_command->len;
2340 memcpy(temp_desc->buffer,
2341 dlc->last_command->buffer,
2342 dlc->last_command->len);
2343
2344 dlc->retransmissions = 0;
2345 ker_mux_send_frame(temp_desc);
2346 uart_data->ker.nr_t2++;
2347 }
2348 break;
2349
2350 case KER_MUX_CLOSING:
2351 /*
2352 * do not care about retransmission couter
2353 * retransmission stops if T3 expires
2354 */
2355 dlc->retransmissions++;
2356 MALLOC(temp_desc, (USHORT)(sizeof( T_desc2 ) - 1
2357 + dlc->last_command->len));
2358
2359 temp_desc->next = (ULONG)NULL;
2360 temp_desc->len = dlc->last_command->len;
2361 memcpy(temp_desc->buffer,
2362 dlc->last_command->buffer,
2363 dlc->last_command->len);
2364
2365 ker_mux_send_frame( temp_desc );
2366 break;
2367
2368 default:
2369 TRACE_ERROR( "SIG_RT_KER_TIMEOUT_T2_IND unexpected" );
2370 break;
2371 }
2372 }
2373 }
2374 break;
2375
2376 case UART_CONNECTION_DEAD:
2377 break;
2378
2379 default:
2380 {
2381 TRACE_EVENT_P2("Unexpected DLC connection state: %d, uart_kers.c(%d)",
2382 dlc->connection_state, __LINE__);
2383 break;
2384 }
2385 }
2386 }
2387 if(uart_data->ker.nr_t2)
2388 {
2389 /*
2390 * restart timer t2
2391 */
2392 sig_ker_rt_start_t2_req();
2393 }
2394 } /* sig_rt_ker_timeout_t2_ind() */
2395
2396
2397
2398 /*
2399 +------------------------------------------------------------------------------
2400 | Function : sig_rt_ker_timeout_t3_ind
2401 +------------------------------------------------------------------------------
2402 | Description : Handles the internal signal SIG_RT_KER_TIMEOUT_T3_IND
2403 |
2404 | Parameters : no parameters
2405 |
2406 +------------------------------------------------------------------------------
2407 */
2408 GLOBAL void sig_rt_ker_timeout_t3_ind ()
2409 {
2410 TRACE_ISIG( "sig_rt_ker_timeout_t3_ind" );
2411
2412 switch( GET_STATE( UART_SERVICE_KER ) )
2413 {
2414 case KER_MUX_ESTABLISH:
2415 case KER_MUX_CLOSING:
2416 SET_STATE( UART_SERVICE_KER, KER_MUX_CLOSED );
2417 /*
2418 * stop timers and
2419 * remove all DLC instances
2420 */
2421 ker_mux_close_down();
2422 if(uart_data->ker.tx_data_desc EQ NULL)
2423 {
2424 uart_data->ker.received_prim|= UART_MUX_CLOSE_REQ_MASK;
2425
2426 if(uart_data->ker.flush_state EQ UART_KER_NOT_FLUSHING)
2427 {
2428 uart_data->ker.flush_state = UART_KER_TX_FLUSH;
2429 sig_ker_tx_flush_req();
2430 }
2431 }
2432 break;
2433
2434 default:
2435 TRACE_ERROR( "SIG_RT_KER_TIMEOUT_T3_IND unexpected" );
2436 break;
2437 }
2438 } /* sig_rt_ker_timeout_t3_ind() */
2439
2440
2441 /*
2442 +------------------------------------------------------------------------------
2443 | Function : sig_rt_ker_timeout_tesd_ind
2444 +------------------------------------------------------------------------------
2445 | Description : Handles the internal signal SIG_RT_KER_TIMEOUT_TESD_IND
2446 |
2447 | This signal means that the trailing guard period has completed.
2448 |
2449 | Parameters : no parameters
2450 |
2451 +------------------------------------------------------------------------------
2452 */
2453 GLOBAL void sig_rt_ker_timeout_tesd_ind ()
2454 {
2455 UBYTE i;
2456
2457 TRACE_ISIG( "sig_rt_ker_timeout_tesd_ind" );
2458
2459 switch( GET_STATE( UART_SERVICE_KER ) )
2460 {
2461 case KER_READY:
2462 case KER_MUX:
2463 for( i = 0; i < UART_MAX_NUMBER_OF_CHANNELS; i++ )
2464 { /*
2465 * set current dtx
2466 */
2467 uart_data->dtx = &uart_data->dtx_base[i];
2468 sig_ker_dtx_timeout_tesd_req();
2469 }
2470 break;
2471
2472 default:
2473 TRACE_ERROR( "SIG_RT_KER_TIMEOUT_TESD_IND unexpected" );
2474 break;
2475 }
2476 } /* sig_rt_ker_timeout_tesd_ind() */
2477